drivers/mmc/sdmmcreg.h

   1 /*      $NetBSD: sdmmcreg.h,v 1.8 2012/01/27 03:07:21 matt Exp $        */
   2 /*      $OpenBSD: sdmmcreg.h,v 1.4 2009/01/09 10:55:22 jsg Exp $        */
   3
   4 /*
   5  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
   6  *
   7  * Permission to use, copy, modify, and distribute this software for any
   8  * purpose with or without fee is hereby granted, provided that the above
   9  * copyright notice and this permission notice appear in all copies.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  */
  19
  20 #ifndef _SDMMCREG_H_
  21 #define _SDMMCREG_H_
  22
  23 /* MMC commands */                              /* response type */
  24 #define MMC_GO_IDLE_STATE               0       /* R0 */
  25 #define MMC_SEND_OP_COND                1       /* R3 */
  26 #define MMC_ALL_SEND_CID                2       /* R2 */
  27 #define MMC_SET_RELATIVE_ADDR           3       /* R1 */
  28 #define MMC_SWITCH                      6       /* R1b */
  29 #define MMC_SELECT_CARD                 7       /* R1 */
  30 #define MMC_SEND_EXT_CSD                8       /* R1 */
  31 #define MMC_SEND_CSD                    9       /* R2 */
  32 #define MMC_SEND_CID                    10      /* R2 */
  33 #define MMC_STOP_TRANSMISSION           12      /* R1b */
  34 #define MMC_SEND_STATUS                 13      /* R1 */
  35 #define MMC_INACTIVE_STATE              15      /* R0 */
  36 #define MMC_SET_BLOCKLEN                16      /* R1 */
  37 #define MMC_READ_BLOCK_SINGLE           17      /* R1 */
  38 #define MMC_READ_BLOCK_MULTIPLE         18      /* R1 */
  39 #define MMC_SET_BLOCK_COUNT             23      /* R1 */
  40 #define MMC_WRITE_BLOCK_SINGLE          24      /* R1 */
  41 #define MMC_WRITE_BLOCK_MULTIPLE        25      /* R1 */
  42 #define MMC_PROGRAM_CSD                 27      /* R1 */
  43 #define MMC_SET_WRITE_PROT              28      /* R1b */
  44 #define MMC_SET_CLR_WRITE_PROT          29      /* R1b */
  45 #define MMC_SET_SEND_WRITE_PROT         30      /* R1 */
  46 #define MMC_TAG_SECTOR_START            32      /* R1 */
  47 #define MMC_TAG_SECTOR_END              33      /* R1 */
  48 #define MMC_UNTAG_SECTOR                34      /* R1 */
  49 #define MMC_TAG_ERASE_GROUP_START       35      /* R1 */
  50 #define MMC_TAG_ERASE_GROUP_END         36      /* R1 */
  51 #define MMC_UNTAG_ERASE_GROUP           37      /* R1 */
  52 #define MMC_ERASE                       38      /* R1b */
  53 #define MMC_LOCK_UNLOCK                 42      /* R1b */
  54 #define MMC_APP_CMD                     55      /* R1 */
  55 #define MMC_READ_OCR                    58      /* R3 */
  56
  57 /* SD commands */                       /* response type */
  58 #define SD_SEND_RELATIVE_ADDR           3       /* R6 */
  59 #define SD_SEND_SWITCH_FUNC             6       /* R1 */
  60 #define SD_SEND_IF_COND                 8       /* R7 */
  61
  62 /* SD application commands */                   /* response type */
  63 #define SD_APP_SET_BUS_WIDTH            6       /* R1 */
  64 #define SD_APP_OP_COND                  41      /* R3 */
  65 #define SD_APP_SEND_SCR                 51      /* R1 */
  66
  67 /* OCR bits */
  68 #define MMC_OCR_MEM_READY               (1U<<31)/* memory power-up status bit */
  69 #define MMC_OCR_HCS                     (1<<30)
  70 #define MMC_OCR_3_5V_3_6V               (1<<23)
  71 #define MMC_OCR_3_4V_3_5V               (1<<22)
  72 #define MMC_OCR_3_3V_3_4V               (1<<21)
  73 #define MMC_OCR_3_2V_3_3V               (1<<20)
  74 #define MMC_OCR_3_1V_3_2V               (1<<19)
  75 #define MMC_OCR_3_0V_3_1V               (1<<18)
  76 #define MMC_OCR_2_9V_3_0V               (1<<17)
  77 #define MMC_OCR_2_8V_2_9V               (1<<16)
  78 #define MMC_OCR_2_7V_2_8V               (1<<15)
  79 #define MMC_OCR_2_6V_2_7V               (1<<14)
  80 #define MMC_OCR_2_5V_2_6V               (1<<13)
  81 #define MMC_OCR_2_4V_2_5V               (1<<12)
  82 #define MMC_OCR_2_3V_2_4V               (1<<11)
  83 #define MMC_OCR_2_2V_2_3V               (1<<10)
  84 #define MMC_OCR_2_1V_2_2V               (1<<9)
  85 #define MMC_OCR_2_0V_2_1V               (1<<8)
  86 #define MMC_OCR_1_9V_2_0V               (1<<7)
  87 #define MMC_OCR_1_8V_1_9V               (1<<6)
  88 #define MMC_OCR_1_7V_1_8V               (1<<5)
  89 #define MMC_OCR_1_6V_1_7V               (1<<4)
  90
  91 /* R1 response type bits */
  92 #define MMC_R1_READY_FOR_DATA           (1<<8)  /* ready for next transfer */
  93 #define MMC_R1_APP_CMD                  (1<<5)  /* app. commands supported */
  94
  95 /* 48-bit response decoding (32 bits w/o CRC) */
  96 #define MMC_R1(resp)                    ((resp)[0])
  97 #define MMC_R3(resp)                    ((resp)[0])
  98 #define SD_R6(resp)                     ((resp)[0])
  99 #define MMC_R7(resp)                    ((resp)[0])
 100 #define MMC_SPI_R1(resp)                ((resp)[0])
 101 #define MMC_SPI_R7(resp)                ((resp)[1])
 102
 103 /* RCA argument and response */
 104 #define MMC_ARG_RCA(rca)                ((rca) << 16)
 105 #define SD_R6_RCA(resp)                 (SD_R6((resp)) >> 16)
 106
 107 /* bus width argument */
 108 #define SD_ARG_BUS_WIDTH_1              0
 109 #define SD_ARG_BUS_WIDTH_4              2
 110
 111 /* EXT_CSD fields */
 112 #define EXT_CSD_BUS_WIDTH               183     /* WO */
 113 #define EXT_CSD_HS_TIMING               185     /* R/W */
 114 #define EXT_CSD_REV                     192     /* RO */
 115 #define EXT_CSD_STRUCTURE               194     /* RO */
 116 #define EXT_CSD_CARD_TYPE               196     /* RO */
 117
 118 /* EXT_CSD field definitions */
 119 #define EXT_CSD_CMD_SET_NORMAL          (1U << 0)
 120 #define EXT_CSD_CMD_SET_SECURE          (1U << 1)
 121 #define EXT_CSD_CMD_SET_CPSECURE        (1U << 2)
 122
 123 /* EXT_CSD_BUS_WIDTH */
 124 #define EXT_CSD_BUS_WIDTH_1             0       /* 1 bit mode */
 125 #define EXT_CSD_BUS_WIDTH_4             1       /* 4 bit mode */
 126 #define EXT_CSD_BUS_WIDTH_8             2       /* 8 bit mode */
 127
 128 /* EXT_CSD_STRUCTURE */
 129 #define EXT_CSD_STRUCTURE_VER_1_0       0       /* CSD Version No.1.0 */
 130 #define EXT_CSD_STRUCTURE_VER_1_1       1       /* CSD Version No.1.1 */
 131 #define EXT_CSD_STRUCTURE_VER_1_2       2       /* Version 4.1-4.2-4.3 */
 132
 133 /* EXT_CSD_CARD_TYPE */
 134 #define EXT_CSD_CARD_TYPE_26M           (1 << 0)
 135 #define EXT_CSD_CARD_TYPE_52M           (1 << 1)
 136
 137 /* MMC_SWITCH access mode */
 138 #define MMC_SWITCH_MODE_CMD_SET         0x00    /* Change the command set */
 139 #define MMC_SWITCH_MODE_SET_BITS        0x01    /* Set bits in value */
 140 #define MMC_SWITCH_MODE_CLEAR_BITS      0x02    /* Clear bits in value */
 141 #define MMC_SWITCH_MODE_WRITE_BYTE      0x03    /* Set target to value */
 142
 143 /* SPI mode reports R1/R2(SEND_STATUS) status. */
 144 #define R1_SPI_IDLE             (1 << 0)
 145 #define R1_SPI_ERASE_RESET      (1 << 1)
 146 #define R1_SPI_ILLEGAL_COMMAND  (1 << 2)
 147 #define R1_SPI_COM_CRC          (1 << 3)
 148 #define R1_SPI_ERASE_SEQ        (1 << 4)
 149 #define R1_SPI_ADDRESS          (1 << 5)
 150 #define R1_SPI_PARAMETER        (1 << 6)
 151 /* R1 bit 7 is always zero */
 152 #define R2_SPI_CARD_LOCKED      (1 << 8)
 153 #define R2_SPI_WP_ERASE_SKIP    (1 << 9)        /* or lock/unlock fail */
 154 #define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
 155 #define R2_SPI_ERROR            (1 << 10)
 156 #define R2_SPI_CC_ERROR         (1 << 11)
 157 #define R2_SPI_CARD_ECC_ERROR   (1 << 12)
 158 #define R2_SPI_WP_VIOLATION     (1 << 13)
 159 #define R2_SPI_ERASE_PARAM      (1 << 14)
 160 #define R2_SPI_OUT_OF_RANGE     (1 << 15)       /* or CSD overwrite */
 161 #define R2_SPI_CSD_OVERWRITE    R2_SPI_OUT_OF_RANGE
 162
 163 /* MMC R2 response (CSD) */
 164 #define MMC_CSD_CSDVER(resp)            MMC_RSP_BITS((resp), 126, 2)
 165 #define  MMC_CSD_CSDVER_1_0             0
 166 #define  MMC_CSD_CSDVER_1_1             1
 167 #define  MMC_CSD_CSDVER_1_2             2 /* MMC 4.1 - 4.2 - 4.3 */
 168 #define  MMC_CSD_CSDVER_EXT_CSD         3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */
 169 #define MMC_CSD_MMCVER(resp)            MMC_RSP_BITS((resp), 122, 4)
 170 #define  MMC_CSD_MMCVER_1_0             0 /* MMC 1.0 - 1.2 */
 171 #define  MMC_CSD_MMCVER_1_4             1 /* MMC 1.4 */
 172 #define  MMC_CSD_MMCVER_2_0             2 /* MMC 2.0 - 2.2 */
 173 #define  MMC_CSD_MMCVER_3_1             3 /* MMC 3.1 - 3.3 */
 174 #define  MMC_CSD_MMCVER_4_0             4 /* MMC 4.1 - 4.2 - 4.3 */
 175 #define MMC_CSD_TAAC(resp)              MMC_RSP_BITS((resp), 112, 8)
 176 #define MMC_CSD_TAAC_MANT(resp)         MMC_RSP_BITS((resp), 115, 4)
 177 #define MMC_CSD_TAAC_EXP(resp)          MMC_RSP_BITS((resp), 112, 3)
 178 #define MMC_CSD_NSAC(resp)              MMC_RSP_BITS((resp), 104, 8)
 179 #define MMC_CSD_TRAN_SPEED(resp)        MMC_RSP_BITS((resp), 96, 8)
 180 #define MMC_CSD_TRAN_SPEED_MANT(resp)   MMC_RSP_BITS((resp), 99, 4)
 181 #define MMC_CSD_TRAN_SPEED_EXP(resp)    MMC_RSP_BITS((resp), 96, 3)
 182 #define MMC_CSD_READ_BL_LEN(resp)       MMC_RSP_BITS((resp), 80, 4)
 183 #define MMC_CSD_C_SIZE(resp)            MMC_RSP_BITS((resp), 62, 12)
 184 #define MMC_CSD_CAPACITY(resp)          ((MMC_CSD_C_SIZE((resp))+1) << \
 185                                          (MMC_CSD_C_SIZE_MULT((resp))+2))
 186 #define MMC_CSD_C_SIZE_MULT(resp)       MMC_RSP_BITS((resp), 47, 3)
 187 #define MMC_CSD_R2W_FACTOR(resp)        MMC_RSP_BITS((resp), 26, 3)
 188 #define MMC_CSD_WRITE_BL_LEN(resp)      MMC_RSP_BITS((resp), 22, 4)
 189
 190 /* MMC v1 R2 response (CID) */
 191 #define MMC_CID_MID_V1(resp)            MMC_RSP_BITS((resp), 104, 24)
 192 #define MMC_CID_PNM_V1_CPY(resp, pnm)                                   \
 193         do {                                                            \
 194                 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8);                 \
 195                 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8);                 \
 196                 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8);                 \
 197                 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8);                 \
 198                 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8);                 \
 199                 (pnm)[5] = MMC_RSP_BITS((resp), 56, 8);                 \
 200                 (pnm)[6] = MMC_RSP_BITS((resp), 48, 8);                 \
 201                 (pnm)[7] = '\0';                                        \
 202         } while (/*CONSTCOND*/0)
 203 #define MMC_CID_REV_V1(resp)            MMC_RSP_BITS((resp), 40, 8)
 204 #define MMC_CID_PSN_V1(resp)            MMC_RSP_BITS((resp), 16, 24)
 205 #define MMC_CID_MDT_V1(resp)            MMC_RSP_BITS((resp), 8, 8)
 206
 207 /* MMC v2 R2 response (CID) */
 208 #define MMC_CID_MID_V2(resp)            MMC_RSP_BITS((resp), 120, 8)
 209 #define MMC_CID_OID_V2(resp)            MMC_RSP_BITS((resp), 104, 16)
 210 #define MMC_CID_PNM_V2_CPY(resp, pnm)                                   \
 211         do {                                                            \
 212                 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8);                 \
 213                 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8);                 \
 214                 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8);                 \
 215                 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8);                 \
 216                 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8);                 \
 217                 (pnm)[5] = MMC_RSP_BITS((resp), 56, 8);                 \
 218                 (pnm)[6] = '\0';                                        \
 219         } while (/*CONSTCOND*/0)
 220 #define MMC_CID_PSN_V2(resp)            MMC_RSP_BITS((resp), 16, 32)
 221
 222 /* SD R2 response (CSD) */
 223 #define SD_CSD_CSDVER(resp)             MMC_RSP_BITS((resp), 126, 2)
 224 #define  SD_CSD_CSDVER_1_0              0
 225 #define  SD_CSD_CSDVER_2_0              1
 226 #define SD_CSD_MMCVER(resp)             MMC_RSP_BITS((resp), 122, 4)
 227 #define SD_CSD_TAAC(resp)               MMC_RSP_BITS((resp), 112, 8)
 228 #define SD_CSD_TAAC_EXP(resp)           MMC_RSP_BITS((resp), 115, 4)
 229 #define SD_CSD_TAAC_MANT(resp)          MMC_RSP_BITS((resp), 112, 3)
 230 #define  SD_CSD_TAAC_1_5_MSEC           0x26
 231 #define SD_CSD_NSAC(resp)               MMC_RSP_BITS((resp), 104, 8)
 232 #define SD_CSD_SPEED(resp)              MMC_RSP_BITS((resp), 96, 8)
 233 #define SD_CSD_SPEED_MANT(resp)         MMC_RSP_BITS((resp), 99, 4)
 234 #define SD_CSD_SPEED_EXP(resp)          MMC_RSP_BITS((resp), 96, 3)
 235 #define  SD_CSD_SPEED_25_MHZ            0x32
 236 #define  SD_CSD_SPEED_50_MHZ            0x5a
 237 #define SD_CSD_CCC(resp)                MMC_RSP_BITS((resp), 84, 12)
 238 #define  SD_CSD_CCC_BASIC               (1 << 0)        /* basic */
 239 #define  SD_CSD_CCC_BR                  (1 << 2)        /* block read */
 240 #define  SD_CSD_CCC_BW                  (1 << 4)        /* block write */
 241 #define  SD_CSD_CCC_ERACE               (1 << 5)        /* erase */
 242 #define  SD_CSD_CCC_WP                  (1 << 6)        /* write protection */
 243 #define  SD_CSD_CCC_LC                  (1 << 7)        /* lock card */
 244 #define  SD_CSD_CCC_AS                  (1 << 8)        /*application specific*/
 245 #define  SD_CSD_CCC_IOM                 (1 << 9)        /* I/O mode */
 246 #define  SD_CSD_CCC_SWITCH              (1 << 10)       /* switch */
 247 #define SD_CSD_READ_BL_LEN(resp)        MMC_RSP_BITS((resp), 80, 4)
 248 #define SD_CSD_READ_BL_PARTIAL(resp)    MMC_RSP_BITS((resp), 79, 1)
 249 #define SD_CSD_WRITE_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 78, 1)
 250 #define SD_CSD_READ_BLK_MISALIGN(resp)  MMC_RSP_BITS((resp), 77, 1)
 251 #define SD_CSD_DSR_IMP(resp)            MMC_RSP_BITS((resp), 76, 1)
 252 #define SD_CSD_C_SIZE(resp)             MMC_RSP_BITS((resp), 62, 12)
 253 #define SD_CSD_CAPACITY(resp)           ((SD_CSD_C_SIZE((resp))+1) << \
 254                                          (SD_CSD_C_SIZE_MULT((resp))+2))
 255 #define SD_CSD_VDD_R_CURR_MIN(resp)     MMC_RSP_BITS((resp), 59, 3)
 256 #define SD_CSD_VDD_R_CURR_MAX(resp)     MMC_RSP_BITS((resp), 56, 3)
 257 #define SD_CSD_VDD_W_CURR_MIN(resp)     MMC_RSP_BITS((resp), 53, 3)
 258 #define SD_CSD_VDD_W_CURR_MAX(resp)     MMC_RSP_BITS((resp), 50, 3)
 259 #define  SD_CSD_VDD_RW_CURR_100mA       0x7
 260 #define  SD_CSD_VDD_RW_CURR_80mA        0x6
 261 #define SD_CSD_V2_C_SIZE(resp)          MMC_RSP_BITS((resp), 48, 22)
 262 #define SD_CSD_V2_CAPACITY(resp)        ((SD_CSD_V2_C_SIZE((resp))+1) << 10)
 263 #define SD_CSD_V2_BL_LEN                0x9 /* 512 */
 264 #define SD_CSD_C_SIZE_MULT(resp)        MMC_RSP_BITS((resp), 47, 3)
 265 #define SD_CSD_ERASE_BLK_EN(resp)       MMC_RSP_BITS((resp), 46, 1)
 266 #define SD_CSD_SECTOR_SIZE(resp)        MMC_RSP_BITS((resp), 39, 7) /* +1 */
 267 #define SD_CSD_WP_GRP_SIZE(resp)        MMC_RSP_BITS((resp), 32, 7) /* +1 */
 268 #define SD_CSD_WP_GRP_ENABLE(resp)      MMC_RSP_BITS((resp), 31, 1)
 269 #define SD_CSD_R2W_FACTOR(resp)         MMC_RSP_BITS((resp), 26, 3)
 270 #define SD_CSD_WRITE_BL_LEN(resp)       MMC_RSP_BITS((resp), 22, 4)
 271 #define  SD_CSD_RW_BL_LEN_2G            0xa
 272 #define  SD_CSD_RW_BL_LEN_1G            0x9
 273 #define SD_CSD_WRITE_BL_PARTIAL(resp)   MMC_RSP_BITS((resp), 21, 1)
 274 #define SD_CSD_FILE_FORMAT_GRP(resp)    MMC_RSP_BITS((resp), 15, 1)
 275 #define SD_CSD_COPY(resp)               MMC_RSP_BITS((resp), 14, 1)
 276 #define SD_CSD_PERM_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 13, 1)
 277 #define SD_CSD_TMP_WRITE_PROTECT(resp)  MMC_RSP_BITS((resp), 12, 1)
 278 #define SD_CSD_FILE_FORMAT(resp)        MMC_RSP_BITS((resp), 10, 2)
 279
 280 /* SD R2 response (CID) */
 281 #define SD_CID_MID(resp)                MMC_RSP_BITS((resp), 120, 8)
 282 #define SD_CID_OID(resp)                MMC_RSP_BITS((resp), 104, 16)
 283 #define SD_CID_PNM_CPY(resp, pnm)                                       \
 284         do {                                                            \
 285                 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8);                 \
 286                 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8);                 \
 287                 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8);                 \
 288                 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8);                 \
 289                 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8);                 \
 290                 (pnm)[5] = '\0';                                        \
 291         } while (/*CONSTCOND*/0)
 292 #define SD_CID_REV(resp)                MMC_RSP_BITS((resp), 56, 8)
 293 #define SD_CID_PSN(resp)                MMC_RSP_BITS((resp), 24, 32)
 294 #define SD_CID_MDT(resp)                MMC_RSP_BITS((resp), 8, 12)
 295
 296 /* SCR (SD Configuration Register) */
 297 #define SCR_STRUCTURE(scr)              MMC_RSP_BITS((scr), 60, 4)
 298 #define  SCR_STRUCTURE_VER_1_0          0 /* Version 1.0 */
 299 #define SCR_SD_SPEC(scr)                MMC_RSP_BITS((scr), 56, 4)
 300 #define  SCR_SD_SPEC_VER_1_0            0 /* Version 1.0 and 1.01 */
 301 #define  SCR_SD_SPEC_VER_1_10           1 /* Version 1.10 */
 302 #define  SCR_SD_SPEC_VER_2              2 /* Version 2.00 or Version 3.0X */
 303 #define SCR_DATA_STAT_AFTER_ERASE(scr)  MMC_RSP_BITS((scr), 55, 1)
 304 #define SCR_SD_SECURITY(scr)            MMC_RSP_BITS((scr), 52, 3)
 305 #define  SCR_SD_SECURITY_NONE           0 /* no security */
 306 #define  SCR_SD_SECURITY_1_0            1 /* security protocol 1.0 */
 307 #define  SCR_SD_SECURITY_1_0_2          2 /* security protocol 1.0 */
 308 #define SCR_SD_BUS_WIDTHS(scr)          MMC_RSP_BITS((scr), 48, 4)
 309 #define  SCR_SD_BUS_WIDTHS_1BIT         (1 << 0) /* 1bit (DAT0) */
 310 #define  SCR_SD_BUS_WIDTHS_4BIT         (1 << 2) /* 4bit (DAT0-3) */
 311 #define SCR_RESERVED(scr)               MMC_RSP_BITS((scr), 32, 16)
 312 #define SCR_RESERVED2(scr)              MMC_RSP_BITS((scr), 0, 32)
 313
 314 /* Status of Switch Function */
 315 #define SFUNC_STATUS_GROUP(status, group) \
 316         be16toh(__bitfield((uint32_t *)(status), (7 - (group)) << 4, 16))
 317
 318 /* Might be slow, but it should work on big and little endian systems. */
 319
 320
 321 /* The macro used to do a (start)-8 to work around a bug in hardware see sdhc.c
 322  * of the openbsd mmc code driver.
 323  */
 324 #define MMC_RSP_BITS(resp, start, len)  __bitfield((resp), (start), (len))
 325 static inline int
 326 __bitfield(uint32_t *src, int start, int len)
 327 {
 328         uint8_t *sp;
 329         uint32_t dst, mask;
 330         int shift, bs, bc;
 331
 332         if (start < 0 || len < 0 || len > 32)
 333                 return 0;
 334
 335         dst = 0;
 336         mask = len % 32 ? UINT_MAX >> (32 - (len % 32)) : UINT_MAX;
 337         shift = 0;
 338
 339         while (len > 0) {
 340                 sp = (uint8_t *)src + start / 8;
 341                 bs = start % 8;
 342                 bc = 8 - bs;
 343                 if (bc > len)
 344                         bc = len;
 345                 dst |= (*sp >> bs) << shift;
 346                 shift += bc;
 347                 start += bc;
 348                 len -= bc;
 349         }
 350
 351         dst &= mask;
 352         return (int)dst;
 353 }
 354
 355 #endif  /* _SDMMCREG_H_ */