drivers/tty/arch/arm/omap_serial.h

   1 #ifndef _OMAP_SERIAL_H
   2 #define _OMAP_SERIAL_H
   3
   4 /* UART register map */
   5 #define OMAP3_UART1_BASE 0x4806A000 /* UART1 physical address */
   6 #define OMAP3_UART2_BASE 0x4806C000 /* UART2 physical address */
   7 #define OMAP3_UART3_BASE 0x49020000 /* UART3 physical address */
   8
   9 /* UART registers */
  10 #define OMAP3_THR               0       /* Transmit holding register */
  11 #define OMAP3_RHR               0       /* Receive holding register */
  12 #define OMAP3_DLL               0       /* Divisor latches low */
  13 #define OMAP3_DLH               1       /* Divisor latches high */
  14 #define OMAP3_IER               1       /* Interrupt enable register */
  15 #define OMAP3_IIR               2       /* Interrupt identification register */
  16 #define OMAP3_EFR               2       /* Extended features register */
  17 #define OMAP3_FCR               2       /* FIFO control register */
  18 #define OMAP3_LCR               3       /* Line control register */
  19 #define OMAP3_MCR               4       /* Modem control register */
  20 #define OMAP3_LSR               5       /* Line status register */
  21 #define OMAP3_MSR               6       /* Modem status register */
  22 #define OMAP3_MDR1              0x08    /* Mode definition register 1 */
  23 #define OMAP3_MDR2              0x09    /* Mode definition register 2 */
  24 #define OMAP3_SCR               0x10    /* Supplementary control register */
  25 #define OMAP3_SSR               0x11    /* Supplementary status register */
  26 #define OMAP3_SYSC              0x15    /* System configuration register */
  27 #define OMAP3_SYSS              0x16    /* System status register */
  28
  29 /* Enhanced Features Register bits */
  30 #define UART_EFR_ECB            0x10    /* Enhanced control bit */
  31
  32 /* Interrupt Enable Register bits */
  33 #define UART_IER_MSI            0x08    /* Modem status interrupt */
  34 #define UART_IER_RLSI           0x04    /* Receiver line status interrupt */
  35 #define UART_IER_THRI           0x02    /* Transmitter holding register int. */
  36 #define UART_IER_RDI            0x01    /* Receiver data interrupt */
  37
  38 /* FIFO control register */
  39 #define OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT        6
  40 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK         (0x3 << 6)
  41 #define UART_FCR_ENABLE_FIFO    0x01    /* Enable the fifo */
  42 #define UART_FCR_CLR_RCVR       0x02    /* Clear the RCVR FIFO */
  43 #define UART_FCR_CLR_XMIT       0x04    /* Clear the XMIT FIFO */
  44
  45 /* Interrupt Identification Register bits */
  46 #define UART_IIR_RDI            0x04    /* Data ready interrupt */
  47 #define UART_IIR_THRI           0x02    /* Transmitter holding register empty */
  48 #define UART_IIR_NO_INT         0x01    /* No interrupt is pending */
  49
  50 /* Line Control Register bits */
  51 #define UART_LCR_DLAB           0x80    /* Divisor latch access bit */
  52 #define UART_LCR_SBC            0x40    /* Set break control */
  53 #define UART_LCR_EPAR           0x10    /* Even parity select */
  54 #define UART_LCR_PARITY         0x08    /* Enable parity */
  55 #define UART_LCR_STOP           0x04    /* Stop bits; 0=1 bit, 1=2 bits */
  56 #define UART_LCR_WLEN5          0x00    /* Wordlength 5 bits */
  57 #define UART_LCR_WLEN6          0x01    /* Wordlength 6 bits */
  58 #define UART_LCR_WLEN7          0x02    /* Wordlength 7 bits */
  59 #define UART_LCR_WLEN8          0x03    /* Wordlength 8 bits */
  60
  61 #define UART_LCR_CONF_MODE_A    UART_LCR_DLAB   /* Configuration Mode A */
  62 #define UART_LCR_CONF_MODE_B    0xBF            /* Configuration Mode B */
  63
  64 /* Line Status Register bits */
  65 #define UART_LSR_THRE           0x20    /* Transmit-hold-register empty */
  66 #define UART_LSR_BI             0x10    /* Break condition */
  67 #define UART_LSR_DR             0x01    /* Data ready */
  68
  69 /* Modem Control Register bits */
  70 #define UART_MCR_TCRTLR         0x40    /* Access TCR/TLR */
  71 #define UART_MCR_OUT2           0x08    /* Out2 complement */
  72 #define UART_MCR_RTS            0x02    /* RTS complement */
  73 #define UART_MCR_DTR            0x01    /* DTR output low */
  74
  75 /* Mode Definition Register 1 bits */
  76 #define OMAP_MDR1_DISABLE       0x07
  77 #define OMAP_MDR1_MODE13X       0x03
  78 #define OMAP_MDR1_MODE16X       0x00
  79
  80 /* Modem Status Register bits */
  81 #define UART_MSR_DCD            0x80    /* Data Carrier Detect */
  82 #define UART_MSR_CTS            0x10    /* Clear to Send */
  83 #define UART_MSR_DDCD           0x08    /* Delta DCD */
  84
  85 /* Supplementary control Register bits */
  86 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK       (1 << 7)
  87
  88 /* System Control Register bits */
  89 #define UART_SYSC_SOFTRESET     0x02
  90
  91 /* System Status Register bits */
  92 #define UART_SYSS_RESETDONE     0x01
  93
  94 /* Line status register fields */
  95 #define OMAP3_LSR_TX_FIFO_E    (1 << 5) /* Transmit FIFO empty */
  96 #define OMAP3_LSR_RX_FIFO_E    (1 << 0) /* Receive FIFO empty */
  97
  98 /* Supplementary status register fields */
  99 #define OMAP3_SSR_TX_FIFO_FULL (1 << 0) /* Transmit FIFO full */
 100
 101 #define OMAP3_UART3_THR (OMAP3_UART3_BASE + OMAP3_THR)
 102 #define OMAP3_UART3_IIR (OMAP3_UART3_BASE + OMAP3_IIR)
 103 #define OMAP3_UART3_LSR (OMAP3_UART3_BASE + OMAP3_LSR)
 104 #define OMAP3_UART3_SSR (OMAP3_UART3_BASE + OMAP3_SSR)
 105
 106 #endif /* _OMAP_SERIAL_H */