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memory: use sys_safememset() for /dev/zero
[minix.git] / drivers / atl2 / atl2.c
blob60c2ecd6dfcc72432a0a73bd8acf010c39378ac0
1 /* Attansic/Atheros L2 FastEthernet driver, by D.C. van Moolenbroek */
2
3 /* No documentation is available for this card. The FreeBSD driver is based
4 * heavily on the official Linux driver; this driver is based heavily on both.
5 */
6
7 #include <minix/drivers.h>
8 #include <minix/netdriver.h>
9
10 #include <sys/mman.h>
11 #include <minix/ds.h>
12 #include <minix/vm.h>
13 #include <machine/pci.h>
14 #include <net/gen/ether.h>
15 #include <net/gen/eth_io.h>
16 #include <assert.h>
17
18 #include "atl2.h"
19
20 #define VERBOSE 0 /* Verbose debugging output */
21 #define ATL2_FKEY 1 /* Register Shift+F11 for dumping statistics */
22
23 #if VERBOSE
24 #define ATL2_DEBUG(x) printf x
25 #else
26 #define ATL2_DEBUG(x)
27 #endif
28
29 typedef struct {
30 u32_t hdr;
31 u32_t vtag;
32 u8_t data[ATL2_RXD_SIZE - sizeof(u32_t) * 2];
33 } rxd_t;
34
35 static struct {
36 int devind; /* PCI device index */
37 int irq; /* IRQ number */
38 int hook_id; /* IRQ hook ID */
39 int mode; /* datalink mode */
40 volatile u8_t *base; /* base address of memory-mapped registers */
41 u32_t size; /* size of memory-mapped area */
42 u32_t hwaddr[2]; /* MAC address, in register representation */
43
44 u8_t *txd_base; /* local address of TxD ring buffer base */
45 u32_t *txs_base; /* local address of TxS ring buffer base */
46 u8_t *rxd_base_u; /* unaligned base address of RxD ring buffer */
47 rxd_t *rxd_base; /* local address of RxD ring buffer base */
48
49 int rxd_align; /* alignment offset of RxD ring buffer */
50
51 vir_bytes txd_phys; /* physical address of TxD ring buffer */
52 vir_bytes txs_phys; /* physical address of TxS ring buffer */
53 vir_bytes rxd_phys; /* physical address of RxD ring buffer */
54
55 int txd_tail; /* tail index into TxD, in bytes */
56 int txd_num; /* head-tail offset into TxD, in bytes */
57 int txs_tail; /* tail index into TxS, in elements */
58 int txs_num; /* head-tail offset into TxS, in elements */
59 int rxd_tail; /* tail index into RxD, in elements */
60
61 int flags; /* state flags (ATL2_FLAG_) */
62 message read_msg; /* suspended read request (READ_PEND) */
63 message write_msg; /* suspended write request (WRITE_PEND) */
64 endpoint_t task_endpt; /* requester endpoint (PACK_RCVD|PACK_SENT) */
65 size_t recv_count; /* packet size (PACK_RCVD) */
66
67 eth_stat_t stat; /* statistics */
68 } state;
69
70 #define ATL2_FLAG_RX_AVAIL 0x01 /* packet available for receipt */
71 #define ATL2_FLAG_READ_PEND 0x02 /* read request pending */
72 #define ATL2_FLAG_WRITE_PEND 0x04 /* write request pending */
73 #define ATL2_FLAG_PACK_RCVD 0x08 /* packet received */
74 #define ATL2_FLAG_PACK_SENT 0x10 /* packet transmitted */
75
76 #define ATL2_READ_U8(off) (* (u8_t *) (state.base + (off)))
77 #define ATL2_READ_U16(off) (* (u16_t *) (state.base + (off)))
78 #define ATL2_READ_U32(off) (* (u32_t *) (state.base + (off)))
79 #define ATL2_WRITE_U8(off, val) * (u8_t *) (state.base + (off)) = (val);
80 #define ATL2_WRITE_U16(off, val) * (u16_t *) (state.base + (off)) = (val);
81 #define ATL2_WRITE_U32(off, val) * (u32_t *) (state.base + (off)) = (val);
82
83 #define ATL2_ALIGN_32(n) (((n) + 3) & ~3)
84
85 static iovec_s_t iovec[NR_IOREQS];
86
87 static int instance;
88
89 /*===========================================================================*
90 * atl2_read_vpd *
91 *===========================================================================*/
92 static int atl2_read_vpd(int index, u32_t *res)
93 {
94 /* Read a value from the VPD register area.
95 */
96 u32_t off, val;
97 int i;
98
99 ATL2_WRITE_U32(ATL2_VPD_DATA_REG, 0);
100
101 off = ATL2_VPD_REGBASE + index * sizeof(u32_t);
102
103 ATL2_WRITE_U32(ATL2_VPD_CAP_REG,
104 (off << ATL2_VPD_CAP_ADDR_SHIFT) & ATL2_VPD_CAP_ADDR_MASK);
105
106 for (i = 0; i < ATL2_VPD_NTRIES; i++) {
107 micro_delay(ATL2_VPD_DELAY);
108
109 val = ATL2_READ_U32(ATL2_VPD_CAP_REG);
110 if (val & ATL2_VPD_CAP_DONE)
111 break;
112 }
113
114 if (i == ATL2_VPD_NTRIES) {
115 printf("ATL2: timeout reading EEPROM register %d\n", index);
116 return FALSE;
117 }
118
119 *res = ATL2_READ_U32(ATL2_VPD_DATA_REG);
120 return TRUE;
121 }
122
123 /*===========================================================================*
124 * atl2_get_vpd_hwaddr *
125 *===========================================================================*/
126 static int atl2_get_vpd_hwaddr(void)
127 {
128 /* Read the MAC address from the EEPROM, using the Vital Product Data
129 * register interface.
130 */
131 u32_t key, val;
132 int i, n, found[2];
133
134 /* No idea, copied from FreeBSD which copied it from Linux. */
135 val = ATL2_READ_U32(ATL2_SPICTL_REG);
136 if (val & ATL2_SPICTL_VPD_EN) {
137 val &= ~ATL2_SPICTL_VPD_EN;
138 ATL2_WRITE_U32(ATL2_SPICTL_REG, val);
139 }
140
141 /* Is VPD supported? */
142 #ifdef PCI_CAP_VPD /* FIXME: just a guess at the future name */
143 if (!pci_find_cap(state.devind, PCI_CAP_VPD, &n))
144 return FALSE;
145 #endif
146
147 /* Read out the set of key/value pairs. Look for the two parts that
148 * make up the MAC address.
149 */
150 found[0] = found[1] = FALSE;
151 for (i = 0; i < ATL2_VPD_NREGS; i += 2) {
152 if (!atl2_read_vpd(i, &key))
153 break;
154
155 if ((key & ATL2_VPD_SIG_MASK) != ATL2_VPD_SIG)
156 break;
157
158 key >>= ATL2_VPD_REG_SHIFT;
159
160 if (key != ATL2_HWADDR0_REG && key != ATL2_HWADDR1_REG)
161 continue;
162
163 if (!atl2_read_vpd(i + 1, &val))
164 break;
165
166 n = (key == ATL2_HWADDR1_REG);
167 state.hwaddr[n] = val;
168 found[n] = TRUE;
169
170 if (found[1 - n]) break;
171 }
172
173 return found[0] && found[1];
174 }
175
176 /*===========================================================================*
177 * atl2_get_hwaddr *
178 *===========================================================================*/
179 static void atl2_get_hwaddr(void)
180 {
181 /* Get the MAC address of the card. First try the EEPROM; if that
182 * fails, just use whatever the card was already set to.
183 */
184
185 if (!atl2_get_vpd_hwaddr()) {
186 printf("ATL2: unable to read from VPD\n");
187
188 state.hwaddr[0] = ATL2_READ_U32(ATL2_HWADDR0_REG);
189 state.hwaddr[1] = ATL2_READ_U32(ATL2_HWADDR1_REG) & 0xffff;
190 }
191
192 ATL2_DEBUG(("ATL2: MAC address %04lx%08lx\n",
193 state.hwaddr[1], state.hwaddr[0]));
194 }
195
196 /*===========================================================================*
197 * atl2_read_mdio *
198 *===========================================================================*/
199 static int atl2_read_mdio(int addr, u16_t *res)
200 {
201 /* Read a MII PHY register using MDIO.
202 */
203 u32_t rval;
204 int i;
205
206 rval = ((addr << ATL2_MDIO_ADDR_SHIFT) & ATL2_MDIO_ADDR_MASK) |
207 ATL2_MDIO_START | ATL2_MDIO_READ | ATL2_MDIO_SUP_PREAMBLE |
208 ATL2_MDIO_CLK_25_4;
209
210 ATL2_WRITE_U32(ATL2_MDIO_REG, rval);
211
212 for (i = 0; i < ATL2_MDIO_NTRIES; i++) {
213 micro_delay(ATL2_MDIO_DELAY);
214
215 rval = ATL2_READ_U32(ATL2_MDIO_REG);
216
217 if (!(rval & (ATL2_MDIO_START | ATL2_MDIO_BUSY)))
218 break;
219 }
220
221 if (i == ATL2_MDIO_NTRIES) return FALSE;
222
223 *res = (u16_t) (rval & ATL2_MDIO_DATA_MASK);
224 return TRUE;
225 }
226
227 /*===========================================================================*
228 * atl2_alloc_dma *
229 *===========================================================================*/
230 static int atl2_alloc_dma(void)
231 {
232 /* Allocate DMA ring buffers.
233 */
234
235 state.txd_base = alloc_contig(ATL2_TXD_BUFSIZE,
236 AC_ALIGN4K, &state.txd_phys);
237 state.txs_base = alloc_contig(ATL2_TXS_COUNT * sizeof(u32_t),
238 AC_ALIGN4K, &state.txs_phys);
239
240 /* The data buffer in each RxD descriptor must be 128-byte aligned.
241 * The two Tx buffers merely require a 4-byte start alignment.
242 */
243 state.rxd_align = 128 - offsetof(rxd_t, data);
244 state.rxd_base_u =
245 alloc_contig(state.rxd_align + ATL2_RXD_COUNT * ATL2_RXD_SIZE,
246 AC_ALIGN4K, &state.rxd_phys);
247
248 /* Unlike mmap, alloc_contig returns NULL on failure. */
249 if (!state.txd_base || !state.txs_base || !state.rxd_base_u)
250 return ENOMEM;
251
252 state.rxd_base = (rxd_t *) (state.rxd_base_u + state.rxd_align);
253 state.rxd_phys += state.rxd_align;
254
255 /* Zero out just in case. */
256 memset(state.txd_base, 0, ATL2_TXD_BUFSIZE);
257 memset(state.txs_base, 0, ATL2_TXS_COUNT * sizeof(u32_t));
258 memset(state.rxd_base, 0, ATL2_RXD_COUNT * ATL2_RXD_SIZE);
259
260 return OK;
261 }
262
263 /*===========================================================================*
264 * atl2_stop *
265 *===========================================================================*/
266 static int atl2_stop(void)
267 {
268 /* Stop the device.
269 */
270 u32_t val;
271 int i;
272
273 /* Clear and disable interrupts. */
274 ATL2_WRITE_U32(ATL2_IMR_REG, 0);
275 ATL2_WRITE_U32(ATL2_ISR_REG, 0xffffffff);
276
277 /* Stop Rx/Tx MACs. */
278 val = ATL2_READ_U32(ATL2_MAC_REG);
279 if (val & (ATL2_MAC_RX_EN | ATL2_MAC_TX_EN)) {
280 val &= ~(ATL2_MAC_RX_EN | ATL2_MAC_TX_EN);
281 ATL2_WRITE_U32(ATL2_MAC_REG, val);
282 }
283
284 ATL2_WRITE_U8(ATL2_DMAWRITE_REG, 0);
285 ATL2_WRITE_U8(ATL2_DMAREAD_REG, 0);
286
287 /* Wait until everything is idle. */
288 for (i = 0; i < ATL2_IDLE_NTRIES; i++) {
289 if (ATL2_READ_U32(ATL2_IDLE_REG) == 0)
290 break;
291
292 micro_delay(ATL2_IDLE_DELAY);
293 }
294
295 /* The caller will generally ignore this return value. */
296 return (i < ATL2_IDLE_NTRIES);
297 }
298
299 /*===========================================================================*
300 * atl2_reset *
301 *===========================================================================*/
302 static int atl2_reset(void)
303 {
304 /* Reset the device to a known good state.
305 */
306 u32_t val;
307 int i;
308
309 /* Issue a soft reset, and wait for the device to respond. */
310 ATL2_WRITE_U32(ATL2_MASTER_REG, ATL2_MASTER_SOFT_RESET);
311
312 for (i = 0; i < ATL2_RESET_NTRIES; i++) {
313 val = ATL2_READ_U32(ATL2_MASTER_REG);
314 if (!(val & ATL2_MASTER_SOFT_RESET))
315 break;
316
317 micro_delay(ATL2_RESET_DELAY);
318 }
319
320 if (i == ATL2_RESET_NTRIES)
321 return FALSE;
322
323 /* Wait until everything is idle. */
324 for (i = 0; i < ATL2_IDLE_NTRIES; i++) {
325 if (ATL2_READ_U32(ATL2_IDLE_REG) == 0)
326 break;
327
328 micro_delay(ATL2_IDLE_DELAY);
329 }
330
331 return (i < ATL2_IDLE_NTRIES);
332 }
333
334 /*===========================================================================*
335 * atl2_set_mode *
336 *===========================================================================*/
337 static void atl2_set_mode(void)
338 {
339 /* Reconfigure the device's promiscuity, multicast, and broadcast mode
340 * settings.
341 */
342 u32_t val;
343
344 val = ATL2_READ_U32(ATL2_MAC_REG);
345 val &= ~(ATL2_MAC_PROMISC_EN | ATL2_MAC_MCAST_EN | ATL2_MAC_BCAST_EN);
346
347 if (state.mode & DL_PROMISC_REQ)
348 val |= ATL2_MAC_PROMISC_EN;
349 if (state.mode & DL_MULTI_REQ)
350 val |= ATL2_MAC_MCAST_EN;
351 if (state.mode & DL_BROAD_REQ)
352 val |= ATL2_MAC_BCAST_EN;
353
354 ATL2_WRITE_U32(ATL2_MAC_REG, val);
355 }
356
357 /*===========================================================================*
358 * atl2_setup *
359 *===========================================================================*/
360 static int atl2_setup(void)
361 {
362 /* Set up the device for normal operation.
363 */
364 u32_t val;
365
366 atl2_stop();
367
368 if (!atl2_reset())
369 return FALSE;
370
371 /* Initialize PCIE module. Magic. */
372 ATL2_WRITE_U32(ATL2_LTSSM_TESTMODE_REG, ATL2_LTSSM_TESTMODE_DEFAULT);
373 ATL2_WRITE_U32(ATL2_DLL_TX_CTRL_REG, ATL2_DLL_TX_CTRL_DEFAULT);
374
375 /* Enable PHY. */
376 ATL2_WRITE_U32(ATL2_PHY_ENABLE_REG, ATL2_PHY_ENABLE);
377 micro_delay(1000);
378
379 /* Clear and disable interrupts. */
380 ATL2_WRITE_U32(ATL2_ISR_REG, 0xffffffff);
381
382 /* Set the MAC address. */
383 ATL2_WRITE_U32(ATL2_HWADDR0_REG, state.hwaddr[0]);
384 ATL2_WRITE_U32(ATL2_HWADDR1_REG, state.hwaddr[1]);
385
386 /* Initialize ring buffer addresses and sizes. */
387 ATL2_WRITE_U32(ATL2_DESC_ADDR_HI_REG, 0); /* no 64 bit */
388 ATL2_WRITE_U32(ATL2_TXD_ADDR_LO_REG, state.txd_phys);
389 ATL2_WRITE_U32(ATL2_TXS_ADDR_LO_REG, state.txs_phys);
390 ATL2_WRITE_U32(ATL2_RXD_ADDR_LO_REG, state.rxd_phys);
391
392 ATL2_WRITE_U16(ATL2_RXD_COUNT_REG, ATL2_RXD_COUNT);
393 ATL2_WRITE_U16(ATL2_TXD_BUFSIZE_REG, ATL2_TXD_BUFSIZE / sizeof(u32_t));
394 ATL2_WRITE_U16(ATL2_TXS_COUNT_REG, ATL2_TXS_COUNT);
395
396 /* A whole lot of other initialization copied from Linux/FreeBSD. */
397 ATL2_WRITE_U32(ATL2_IFG_REG, ATL2_IFG_DEFAULT);
398
399 ATL2_WRITE_U32(ATL2_HDPX_REG, ATL2_HDPX_DEFAULT);
400
401 ATL2_WRITE_U16(ATL2_IMT_REG, ATL2_IMT_DEFAULT);
402 val = ATL2_READ_U32(ATL2_MASTER_REG);
403 ATL2_WRITE_U32(ATL2_MASTER_REG, val | ATL2_MASTER_IMT_EN);
404
405 ATL2_WRITE_U16(ATL2_ICT_REG, ATL2_ICT_DEFAULT);
406
407 ATL2_WRITE_U32(ATL2_CUT_THRESH_REG, ATL2_CUT_THRESH_DEFAULT);
408
409 ATL2_WRITE_U16(ATL2_FLOW_THRESH_HI_REG, (ATL2_RXD_COUNT / 8) * 7);
410 ATL2_WRITE_U16(ATL2_FLOW_THRESH_LO_REG, ATL2_RXD_COUNT / 12);
411
412 /* Set MTU. */
413 ATL2_WRITE_U16(ATL2_MTU_REG, ATL2_MTU_DEFAULT);
414
415 /* Reset descriptors, and enable DMA. */
416 state.txd_tail = state.txs_tail = state.rxd_tail = 0;
417 state.txd_num = state.txs_num = 0;
418 state.flags &= ~ATL2_FLAG_RX_AVAIL;
419 ATL2_WRITE_U16(ATL2_TXD_IDX_REG, 0);
420 ATL2_WRITE_U16(ATL2_RXD_IDX_REG, 0);
421
422 ATL2_WRITE_U8(ATL2_DMAREAD_REG, ATL2_DMAREAD_EN);
423 ATL2_WRITE_U8(ATL2_DMAWRITE_REG, ATL2_DMAWRITE_EN);
424
425 /* Did everything go alright? */
426 val = ATL2_READ_U32(ATL2_ISR_REG);
427 if (val & ATL2_ISR_PHY_LINKDOWN) {
428 printf("ATL2: initialization failed\n");
429 return FALSE;
430 }
431
432 /* Clear interrupt status. */
433 ATL2_WRITE_U32(ATL2_ISR_REG, 0x3fffffff);
434 ATL2_WRITE_U32(ATL2_ISR_REG, 0);
435
436 /* Enable interrupts. */
437 ATL2_WRITE_U32(ATL2_IMR_REG, ATL2_IMR_DEFAULT);
438
439 /* Configure MAC. */
440 ATL2_WRITE_U32(ATL2_MAC_REG, ATL2_MAC_DEFAULT);
441
442 /* Inet does not tell us about the multicast addresses that it is
443 * interested in, so we have to simply accept all multicast packets.
444 */
445 ATL2_WRITE_U32(ATL2_MHT0_REG, 0xffffffff);
446 ATL2_WRITE_U32(ATL2_MHT1_REG, 0xffffffff);
447
448 atl2_set_mode();
449
450 /* Enable Tx/Rx. */
451 val = ATL2_READ_U32(ATL2_MAC_REG);
452 ATL2_WRITE_U32(ATL2_MAC_REG, val | ATL2_MAC_TX_EN | ATL2_MAC_RX_EN);
453
454 return TRUE;
455 }
456
457 /*===========================================================================*
458 * atl2_probe *
459 *===========================================================================*/
460 static int atl2_probe(int skip)
461 {
462 /* Find a matching PCI device.
463 */
464 u16_t vid, did;
465 #if VERBOSE
466 char *dname;
467 #endif
468 int r, devind;
469
470 pci_init();
471
472 r = pci_first_dev(&devind, &vid, &did);
473 if (r <= 0)
474 return -1;
475
476 while (skip--) {
477 r = pci_next_dev(&devind, &vid, &did);
478 if (r <= 0)
479 return -1;
480 }
481
482 #if VERBOSE
483 dname = pci_dev_name(vid, did);
484 ATL2_DEBUG(("ATL2: found %s (%x/%x) at %s\n",
485 dname ? dname : "<unknown>", vid, did,
486 pci_slot_name(devind)));
487 #endif
488
489 pci_reserve(devind);
490
491 return devind;
492 }
493
494 /*===========================================================================*
495 * atl2_init *
496 *===========================================================================*/
497 static void atl2_init(int devind)
498 {
499 /* Initialize the device.
500 */
501 u32_t bar;
502 int r, flag;
503
504 /* Initialize global state. */
505 state.devind = devind;
506 state.mode = DL_NOMODE;
507 state.flags = 0;
508 state.recv_count = 0;
509
510 memset(&state.stat, 0, sizeof(state.stat));
511
512 if ((r = pci_get_bar(devind, PCI_BAR, &bar, &state.size, &flag)) != OK)
513 panic("unable to retrieve bar: %d", r);
514
515 if (state.size < ATL2_MIN_MMAP_SIZE || flag)
516 panic("invalid register bar");
517
518 state.base = vm_map_phys(SELF, (void *) bar, state.size);
519 if (state.base == MAP_FAILED)
520 panic("unable to map in registers");
521
522 if ((r = atl2_alloc_dma()) != OK)
523 panic("unable to allocate DMA buffers: %d", r);
524
525 state.irq = pci_attr_r8(devind, PCI_ILR);
526
527 if ((r = sys_irqsetpolicy(state.irq, 0, &state.hook_id)) != OK)
528 panic("unable to register IRQ: %d", r);
529
530 if (!atl2_reset())
531 panic("unable to reset hardware");
532
533 if ((r = sys_irqenable(&state.hook_id)) != OK)
534 panic("unable to enable IRQ: %d", r);
535
536 atl2_get_hwaddr();
537
538 atl2_setup();
539 }
540
541 /*===========================================================================*
542 * atl2_tx_stat *
543 *===========================================================================*/
544 static void atl2_tx_stat(u32_t stat)
545 {
546 /* Update statistics for packet transmission.
547 */
548
549 if (stat & ATL2_TXS_SUCCESS)
550 state.stat.ets_packetT++;
551 else
552 state.stat.ets_recvErr++;
553
554 if (stat & ATL2_TXS_DEFER)
555 state.stat.ets_transDef++;
556 if (stat & (ATL2_TXS_EXCDEFER | ATL2_TXS_ABORTCOL))
557 state.stat.ets_transAb++;
558 if (stat & ATL2_TXS_SINGLECOL)
559 state.stat.ets_collision++;
560 if (stat & ATL2_TXS_MULTICOL)
561 state.stat.ets_collision++;
562 if (stat & ATL2_TXS_LATECOL)
563 state.stat.ets_OWC++;
564 if (stat & ATL2_TXS_UNDERRUN)
565 state.stat.ets_fifoUnder++;
566 }
567
568 /*===========================================================================*
569 * atl2_rx_stat *
570 *===========================================================================*/
571 static void atl2_rx_stat(u32_t stat)
572 {
573 /* Update statistics for packet receipt.
574 */
575
576 if (stat & ATL2_RXD_SUCCESS)
577 state.stat.ets_packetR++;
578 else
579 state.stat.ets_recvErr++;
580
581 if (stat & ATL2_RXD_CRCERR)
582 state.stat.ets_CRCerr++;
583 if (stat & ATL2_RXD_FRAG)
584 state.stat.ets_collision++;
585 if (stat & ATL2_RXD_TRUNC)
586 state.stat.ets_fifoOver++;
587 if (stat & ATL2_RXD_ALIGN)
588 state.stat.ets_frameAll++;
589 }
590
591 /*===========================================================================*
592 * atl2_tx_advance *
593 *===========================================================================*/
594 static int atl2_tx_advance(void)
595 {
596 /* Advance the TxD/TxS tails by as many sent packets as found.
597 */
598 u32_t stat, size, dsize;
599 int advanced;
600
601 advanced = FALSE;
602
603 while (state.txs_num > 0) {
604 /* Has the tail packet been processed by the driver? */
605 stat = state.txs_base[state.txs_tail];
606
607 if (!(stat & ATL2_TXS_UPDATE))
608 break;
609
610 /* The packet size from the status must match the packet size
611 * we put in. If they don't, there's not much we can do..
612 */
613 size = stat & ATL2_TXS_SIZE_MASK;
614
615 assert((u32_t) state.txd_tail <=
616 ATL2_TXD_BUFSIZE - sizeof(u32_t));
617 dsize = * (u32_t *) (state.txd_base + state.txd_tail);
618 if (size != dsize)
619 printf("ATL2: TxD/TxS size mismatch (%x vs %x)\n",
620 size, dsize);
621
622 /* Advance tails accordingly. */
623 size = sizeof(u32_t) + ATL2_ALIGN_32(dsize);
624 assert((u32_t) state.txd_num >= size);
625 state.txd_tail = (state.txd_tail + size) % ATL2_TXD_BUFSIZE;
626 state.txd_num -= size;
627
628 state.txs_tail = (state.txs_tail + 1) % ATL2_TXS_COUNT;
629 state.txs_num--;
630
631 if (stat & ATL2_TXS_SUCCESS) {
632 ATL2_DEBUG(("ATL2: successfully sent packet\n"));
633 } else {
634 ATL2_DEBUG(("ATL2: failed to send packet\n"));
635 }
636
637 /* Update statistics. */
638 atl2_tx_stat(stat);
639
640 advanced = TRUE;
641 }
642
643 return advanced;
644 }
645
646 /*===========================================================================*
647 * atl2_rx_advance *
648 *===========================================================================*/
649 static void atl2_rx_advance(int next)
650 {
651 /* Advance the RxD tail by as many failed receipts as possible, and
652 * see if there is an actual packet left to receive. If 'next' is set,
653 * the packet at the current tail has been processed.
654 */
655 int update_tail;
656 rxd_t *rxd;
657 u32_t hdr, size;
658
659 update_tail = FALSE;
660
661 if (next) {
662 state.rxd_tail = (state.rxd_tail + 1) % ATL2_RXD_COUNT;
663 update_tail = TRUE;
664
665 ATL2_DEBUG(("ATL2: successfully received packet\n"));
666
667 state.flags &= ~ATL2_FLAG_RX_AVAIL;
668 }
669
670 assert(!(state.flags & ATL2_FLAG_RX_AVAIL));
671
672 for (;;) {
673 /* Check the RxD tail for updates. */
674 rxd = &state.rxd_base[state.rxd_tail];
675
676 hdr = rxd->hdr;
677
678 if (!(hdr & ATL2_RXD_UPDATE))
679 break;
680
681 rxd->hdr = hdr & ~(ATL2_RXD_UPDATE);
682
683 /* Update statistics. */
684 atl2_rx_stat(hdr);
685
686 /* Stop at the first successful receipt. The packet will be
687 * picked up by Inet later.
688 */
689 size = hdr & ATL2_RXD_SIZE_MASK;
690
691 if ((hdr & ATL2_RXD_SUCCESS) && size >= ETH_MIN_PACK_SIZE) {
692 ATL2_DEBUG(("ATL2: packet available, size %ld\n",
693 size));
694
695 state.flags |= ATL2_FLAG_RX_AVAIL;
696 break;
697 }
698
699 ATL2_DEBUG(("ATL2: packet receipt failed\n"));
700
701 /* Advance tail. */
702 state.rxd_tail = (state.rxd_tail + 1) % ATL2_RXD_COUNT;
703 update_tail = TRUE;
704 }
705
706 /* If new RxD descriptors are now up for reuse, tell the device. */
707 if (update_tail) {
708 __insn_barrier();
709
710 ATL2_WRITE_U32(ATL2_RXD_IDX_REG, state.rxd_tail);
711 }
712 }
713
714 /*===========================================================================*
715 * atl2_reply *
716 *===========================================================================*/
717 static void atl2_reply(void)
718 {
719 /* Send a task reply to Inet.
720 */
721 message m;
722 int r, flags;
723
724 flags = DL_NOFLAGS;
725 if (state.flags & ATL2_FLAG_PACK_SENT)
726 flags |= DL_PACK_SEND;
727 if (state.flags & ATL2_FLAG_PACK_RCVD)
728 flags |= DL_PACK_RECV;
729
730 m.m_type = DL_TASK_REPLY;
731 m.DL_FLAGS = flags;
732 m.DL_COUNT = state.recv_count;
733
734 ATL2_DEBUG(("ATL2: sending reply, flags %x count %d\n", flags,
735 m.DL_COUNT));
736
737 if ((r = send(state.task_endpt, &m)) != OK)
738 panic("unable to reply: %d", r);
739
740 state.flags &= ~(ATL2_FLAG_PACK_SENT | ATL2_FLAG_PACK_RCVD);
741 state.recv_count = 0;
742 }
743
744 /*===========================================================================*
745 * atl2_readv *
746 *===========================================================================*/
747 static void atl2_readv(const message *m, int from_int)
748 {
749 /* Read packet data.
750 */
751 rxd_t *rxd;
752 iovec_s_t *iovp;
753 size_t count, off, left, size;
754 u8_t *pos;
755 int i, j, r, batch;
756
757 /* We can deal with only one read request from Inet at a time. */
758 assert(from_int || !(state.flags & ATL2_FLAG_READ_PEND));
759
760 state.task_endpt = m->m_source;
761
762 /* Are there any packets available at all? */
763 if (!(state.flags & ATL2_FLAG_RX_AVAIL))
764 goto suspend;
765
766 /* Get the first available packet's size. Cut off the CRC. */
767 rxd = &state.rxd_base[state.rxd_tail];
768
769 count = rxd->hdr & ATL2_RXD_SIZE_MASK;
770 count -= ETH_CRC_SIZE;
771
772 ATL2_DEBUG(("ATL2: readv: found packet with length %d\n", count));
773
774 /* Copy out the packet. */
775 off = 0;
776 left = count;
777 pos = rxd->data;
778
779 for (i = 0; i < m->DL_COUNT && left > 0; i += batch) {
780 /* Copy in the next batch. */
781 batch = MIN(m->DL_COUNT - i, NR_IOREQS);
782
783 r = sys_safecopyfrom(m->m_source, m->DL_GRANT, off,
784 (vir_bytes) iovec, batch * sizeof(iovec[0]));
785 if (r != OK)
786 panic("vector copy failed: %d", r);
787
788 /* Copy out each element in the batch, until we run out. */
789 for (j = 0, iovp = iovec; j < batch && left > 0; j++, iovp++) {
790 size = MIN(iovp->iov_size, left);
791
792 r = sys_safecopyto(m->m_source, iovp->iov_grant, 0,
793 (vir_bytes) pos, size);
794 if (r != OK)
795 panic("safe copy failed: %d", r);
796
797 pos += size;
798 left -= size;
799 }
800
801 off += batch * sizeof(iovec[0]);
802 }
803
804 /* Not sure what to do here. Inet shouldn't mess this up anyway. */
805 if (left > 0) {
806 printf("ATL2: truncated packet of %d bytes by %d bytes\n",
807 count, left);
808 count -= left;
809 }
810
811 /* We are done with this packet. Move on to the next. */
812 atl2_rx_advance(TRUE /*next*/);
813
814 /* We have now successfully received a packet. */
815 state.flags &= ~ATL2_FLAG_READ_PEND;
816 state.flags |= ATL2_FLAG_PACK_RCVD;
817 state.recv_count = count;
818
819 /* If called from the interrupt handler, the caller will reply. */
820 if (!from_int)
821 atl2_reply();
822
823 return;
824
825 suspend:
826 /* No packets are available at this time. If we were not already
827 * trying to resume receipt, save the read request for later, and tell
828 * Inet that the request has been suspended.
829 */
830 if (from_int)
831 return;
832
833 state.flags |= ATL2_FLAG_READ_PEND;
834 state.read_msg = *m;
835
836 atl2_reply();
837 }
838
839 /*===========================================================================*
840 * atl2_writev *
841 *===========================================================================*/
842 static void atl2_writev(const message *m, int from_int)
843 {
844 /* Write packet data.
845 */
846 iovec_s_t *iovp;
847 size_t off, count, left, pos, skip;
848 vir_bytes size;
849 u8_t *sizep;
850 int i, j, r, batch, maxnum;
851
852 /* We can deal with only one write request from Inet at a time. */
853 assert(from_int || !(state.flags & ATL2_FLAG_WRITE_PEND));
854
855 state.task_endpt = m->m_source;
856
857 /* If we are already certain that the packet won't fit, bail out.
858 * Keep at least some space between TxD head and tail, as it is not
859 * clear whether the device deals well with the case that they collide.
860 */
861 if (state.txs_num >= ATL2_TXS_COUNT)
862 goto suspend;
863 maxnum = ATL2_TXD_BUFSIZE - ETH_MIN_PACK_SIZE - sizeof(u32_t);
864 if (state.txd_num >= maxnum)
865 goto suspend;
866
867 /* Optimistically try to copy in the data; suspend if it turns out
868 * that it does not fit.
869 */
870 off = 0;
871 count = 0;
872 left = state.txd_num - sizeof(u32_t);
873 pos = (state.txd_tail + state.txd_num +
874 sizeof(u32_t)) % ATL2_TXD_BUFSIZE;
875
876 for (i = 0; i < m->DL_COUNT; i += batch) {
877 /* Copy in the next batch. */
878 batch = MIN(m->DL_COUNT - i, NR_IOREQS);
879
880 r = sys_safecopyfrom(m->m_source, m->DL_GRANT, off,
881 (vir_bytes) iovec, batch * sizeof(iovec[0]));
882 if (r != OK)
883 panic("vector copy failed: %d", r);
884
885 /* Copy in each element in the batch. */
886 for (j = 0, iovp = iovec; j < batch; j++, iovp++) {
887 size = iovp->iov_size;
888 if (size > left)
889 goto suspend;
890
891 skip = 0;
892 if (size > ATL2_TXD_BUFSIZE - pos) {
893 skip = ATL2_TXD_BUFSIZE - pos;
894 r = sys_safecopyfrom(m->m_source,
895 iovp->iov_grant, 0,
896 (vir_bytes) (state.txd_base + pos),
897 skip);
898 if (r != OK)
899 panic("safe copy failed: %d", r);
900 pos = 0;
901 }
902
903 r = sys_safecopyfrom(m->m_source, iovp->iov_grant,
904 skip, (vir_bytes) (state.txd_base + pos),
905 size - skip);
906 if (r != OK)
907 panic("safe copy failed: %d", r);
908
909 pos = (pos + size - skip) % ATL2_TXD_BUFSIZE;
910 left -= size;
911 count += size;
912 }
913
914 off += batch * sizeof(iovec[0]);
915 }
916
917 assert(count <= ETH_MAX_PACK_SIZE_TAGGED);
918
919 /* Write the length to the DWORD right before the packet. */
920 sizep = state.txd_base +
921 (state.txd_tail + state.txd_num) % ATL2_TXD_BUFSIZE;
922 * (u32_t *) sizep = count;
923
924 /* Update the TxD head. */
925 state.txd_num += sizeof(u32_t) + ATL2_ALIGN_32(count);
926 pos = ATL2_ALIGN_32(pos) % ATL2_TXD_BUFSIZE;
927 assert((int) pos ==
928 (state.txd_tail + state.txd_num) % ATL2_TXD_BUFSIZE);
929
930 /* Initialize and update the TxS head. */
931 state.txs_base[(state.txs_tail + state.txs_num) % ATL2_TXS_COUNT] = 0;
932 state.txs_num++;
933
934 /* Tell the device about our new position. */
935 __insn_barrier();
936
937 ATL2_WRITE_U32(ATL2_TXD_IDX_REG, pos / sizeof(u32_t));
938
939 /* We have now successfully set up the transmission of a packet. */
940 state.flags &= ~ATL2_FLAG_WRITE_PEND;
941 state.flags |= ATL2_FLAG_PACK_SENT;
942
943 /* If called from the interrupt handler, the caller will reply. */
944 if (!from_int)
945 atl2_reply();
946
947 return;
948
949 suspend:
950 /* We cannot transmit the packet at this time. If we were not already
951 * trying to resume transmission, save the write request for later,
952 * and tell Inet that the request has been suspended.
953 */
954 if (from_int)
955 return;
956
957 state.flags |= ATL2_FLAG_WRITE_PEND;
958 state.write_msg = *m;
959
960 atl2_reply();
961 }
962
963 /*===========================================================================*
964 * atl2_intr *
965 *===========================================================================*/
966 static void atl2_intr(const message *UNUSED(m))
967 {
968 /* Interrupt received.
969 */
970 u32_t val;
971 int r, try_write, try_read;
972
973 /* Clear and disable interrupts. */
974 val = ATL2_READ_U32(ATL2_ISR_REG);
975
976 ATL2_WRITE_U32(ATL2_ISR_REG, val | ATL2_ISR_DISABLE);
977
978 ATL2_DEBUG(("ATL2: interrupt (0x%08lx)\n", val));
979
980 /* If an error occurred, reset the card. */
981 if (val & (ATL2_ISR_DMAR_TIMEOUT | ATL2_ISR_DMAW_TIMEOUT |
982 ATL2_ISR_PHY_LINKDOWN)) {
983 atl2_setup();
984 }
985
986 try_write = try_read = FALSE;
987
988 /* Process sent data, and possibly send pending data. */
989 if (val & ATL2_ISR_TX_EVENT) {
990 if (atl2_tx_advance())
991 try_write = (state.flags & ATL2_FLAG_WRITE_PEND);
992 }
993
994 /* Receive new data, and possible satisfy a pending receive request. */
995 if (val & ATL2_ISR_RX_EVENT) {
996 if (!(state.flags & ATL2_FLAG_RX_AVAIL)) {
997 atl2_rx_advance(FALSE /*next*/);
998
999 try_read = (state.flags & ATL2_FLAG_READ_PEND);
1000 }
1001 }
1002
1003 /* Reenable interrupts. */
1004 ATL2_WRITE_U32(ATL2_ISR_REG, 0);
1005
1006 if ((r = sys_irqenable(&state.hook_id)) != OK)
1007 panic("unable to enable IRQ: %d", r);
1008
1009 /* Attempt to satisfy pending write and read requests. */
1010 if (try_write)
1011 atl2_writev(&state.write_msg, TRUE /*from_int*/);
1012 if (try_read)
1013 atl2_readv(&state.read_msg, TRUE /*from_int*/);
1014 if (state.flags & (ATL2_FLAG_PACK_SENT | ATL2_FLAG_PACK_RCVD))
1015 atl2_reply();
1016 }
1017
1018 /*===========================================================================*
1019 * atl2_conf *
1020 *===========================================================================*/
1021 static void atl2_conf(message *m)
1022 {
1023 /* Configure the mode of the card.
1024 */
1025 ether_addr_t addr;
1026 int r;
1027
1028 state.mode = m->DL_MODE;
1029
1030 atl2_set_mode();
1031
1032 addr.ea_addr[0] = state.hwaddr[1] >> 8;
1033 addr.ea_addr[1] = state.hwaddr[1] & 0xff;
1034 addr.ea_addr[2] = state.hwaddr[0] >> 24;
1035 addr.ea_addr[3] = (state.hwaddr[0] >> 16) & 0xff;
1036 addr.ea_addr[4] = (state.hwaddr[0] >> 8) & 0xff;
1037 addr.ea_addr[5] = state.hwaddr[0] & 0xff;
1038
1039 memcpy(m->DL_HWADDR, &addr, sizeof(addr));
1040
1041 m->m_type = DL_CONF_REPLY;
1042 m->DL_STAT = OK;
1043
1044 if ((r = send(m->m_source, m)) != OK)
1045 printf("ATL2: unable to send reply (%d)\n", r);
1046 }
1047
1048 /*===========================================================================*
1049 * atl2_getstat *
1050 *===========================================================================*/
1051 static void atl2_getstat(message *m)
1052 {
1053 /* Copy out statistics.
1054 */
1055 int r;
1056
1057 sys_safecopyto(m->m_source, m->DL_GRANT, 0,
1058 (vir_bytes) &state.stat, sizeof(state.stat));
1059
1060 m->m_type = DL_STAT_REPLY;
1061
1062 if ((r = send(m->m_source, m)) != OK)
1063 printf("ATL2: unable to send reply (%d)\n", r);
1064 }
1065
1066 /*===========================================================================*
1067 * atl2_dump_link *
1068 *===========================================================================*/
1069 static void atl2_dump_link(void)
1070 {
1071 /* Dump link status.
1072 */
1073 u16_t val;
1074 int link_up;
1075
1076 /* The link status bit is latched. Read the status register twice. */
1077 atl2_read_mdio(ATL2_MII_BMSR, &val);
1078 if (!atl2_read_mdio(ATL2_MII_BMSR, &val)) return;
1079
1080 link_up = val & ATL2_MII_BMSR_LSTATUS;
1081 printf("link status: %4s\t", link_up ? "up" : "down");
1082
1083 if (!link_up) return;
1084
1085 if (!atl2_read_mdio(ATL2_MII_PSSR, &val)) return;
1086
1087 if (!(val & ATL2_MII_PSSR_RESOLVED)) {
1088 printf("(not resolved)\n");
1089
1090 return;
1091 }
1092
1093 switch (val & ATL2_MII_PSSR_SPEED) {
1094 case ATL2_MII_PSSR_10: printf("(10Mbps "); break;
1095 case ATL2_MII_PSSR_100: printf("(100Mbps "); break;
1096 case ATL2_MII_PSSR_1000: printf("(1000Mbps "); break;
1097 default: printf("(unknown, ");
1098 }
1099
1100 printf("%s duplex)", (val & ATL2_MII_PSSR_DUPLEX) ? "full" : "half");
1101 }
1102
1103 /*===========================================================================*
1104 * atl2_dump *
1105 *===========================================================================*/
1106 static void atl2_dump(void)
1107 {
1108 /* Dump statistics.
1109 */
1110
1111 printf("\n");
1112 printf("Attansic L2 statistics:\n");
1113
1114 printf("recvErr: %8ld\t", state.stat.ets_recvErr);
1115 printf("sendErr: %8ld\t", state.stat.ets_sendErr);
1116 printf("OVW: %8ld\n", state.stat.ets_OVW);
1117
1118 printf("CRCerr: %8ld\t", state.stat.ets_CRCerr);
1119 printf("frameAll: %8ld\t", state.stat.ets_frameAll);
1120 printf("missedP: %8ld\n", state.stat.ets_missedP);
1121
1122 printf("packetR: %8ld\t", state.stat.ets_packetR);
1123 printf("packetT: %8ld\t", state.stat.ets_packetT);
1124 printf("transDef: %8ld\n", state.stat.ets_transDef);
1125
1126 printf("collision: %8ld\t", state.stat.ets_collision);
1127 printf("transAb: %8ld\t", state.stat.ets_transAb);
1128 printf("carrSense: %8ld\n", state.stat.ets_carrSense);
1129
1130 printf("fifoUnder: %8ld\t", state.stat.ets_fifoUnder);
1131 printf("fifoOver: %8ld\t", state.stat.ets_fifoOver);
1132 printf("CDheartbeat: %8ld\n", state.stat.ets_CDheartbeat);
1133
1134 printf("OWC: %8ld\t", state.stat.ets_OWC);
1135 printf("TxD tail: %8d\t", state.txd_tail);
1136 printf("TxD count: %8d\n", state.txd_num);
1137
1138 printf("RxD tail: %8d\t", state.rxd_tail);
1139 printf("TxS tail: %8d\t", state.txs_tail);
1140 printf("TxS count: %8d\n", state.txs_num);
1141
1142 printf("flags: 0x%04x\t", state.flags);
1143 atl2_dump_link();
1144 printf("\n");
1145 }
1146
1147 /*===========================================================================*
1148 * sef_cb_init_fresh *
1149 *===========================================================================*/
1150 static int sef_cb_init_fresh(int UNUSED(type), sef_init_info_t *UNUSED(info))
1151 {
1152 /* Initialize the atl2 driver.
1153 */
1154 int r, devind;
1155 long v;
1156 #if ATL2_FKEY
1157 int fkeys, sfkeys;
1158 #endif
1159
1160 /* How many matching devices should we skip? */
1161 v = 0;
1162 (void) env_parse("instance", "d", 0, &v, 0, 255);
1163 instance = (int) v;
1164
1165 /* Try to find a recognized device. */
1166 devind = atl2_probe(instance);
1167
1168 if (devind < 0)
1169 panic("no matching device found");
1170
1171 /* Initialize the device. */
1172 atl2_init(devind);
1173
1174 /* Announce we are up! */
1175 netdriver_announce();
1176
1177 #if ATL2_FKEY
1178 /* Register debug dump function key. */
1179 fkeys = sfkeys = 0;
1180 bit_set(sfkeys, 11);
1181 if ((r = fkey_map(&fkeys, &sfkeys)) != OK)
1182 printf("ATL2: warning, could not map Shift+F11 key (%d)\n", r);
1183 #endif
1184
1185 return(OK);
1186 }
1187
1188 /*===========================================================================*
1189 * sef_cb_signal_handler *
1190 *===========================================================================*/
1191 static void sef_cb_signal_handler(int signo)
1192 {
1193 /* In case of a termination signal, shut down this driver.
1194 * Stop the device, and deallocate resources as proof of concept.
1195 */
1196 int r;
1197
1198 /* Only check for termination signal, ignore anything else. */
1199 if (signo != SIGTERM) return;
1200
1201 atl2_stop();
1202
1203 if ((r = sys_irqrmpolicy(&state.hook_id)) != OK)
1204 panic("unable to deregister IRQ: %d", r);
1205
1206 free_contig(state.txd_base, ATL2_TXD_BUFSIZE);
1207 free_contig(state.txs_base, ATL2_TXS_COUNT * sizeof(u32_t));
1208 free_contig(state.rxd_base_u,
1209 state.rxd_align + ATL2_RXD_COUNT * ATL2_RXD_SIZE);
1210
1211 vm_unmap_phys(SELF, (void *) state.base, state.size);
1212
1213 /* We cannot free the PCI device at this time. */
1214
1215 exit(0);
1216 }
1217
1218 /*===========================================================================*
1219 * sef_local_startup *
1220 *===========================================================================*/
1221 static void sef_local_startup(void)
1222 {
1223 /* Register init callbacks. */
1224 sef_setcb_init_fresh(sef_cb_init_fresh);
1225 sef_setcb_init_lu(sef_cb_init_fresh);
1226 sef_setcb_init_restart(sef_cb_init_fresh);
1227
1228 /* Register live update callbacks. */
1229 sef_setcb_lu_prepare(sef_cb_lu_prepare_always_ready);
1230 sef_setcb_lu_state_isvalid(sef_cb_lu_state_isvalid_workfree);
1231
1232 /* Register signal callbacks. */
1233 sef_setcb_signal_handler(sef_cb_signal_handler);
1234
1235 /* Let SEF perform startup. */
1236 sef_startup();
1237 }
1238
1239 /*===========================================================================*
1240 * main *
1241 *===========================================================================*/
1242 int main(int argc, char **argv)
1243 {
1244 /* Driver task.
1245 */
1246 message m;
1247 int ipc_status;
1248 int r;
1249
1250 /* Initialize SEF. */
1251 env_setargs(argc, argv);
1252 sef_local_startup();
1253
1254 while (TRUE) {
1255 if ((r = netdriver_receive(ANY, &m, &ipc_status)) != OK)
1256 panic("netdriver_receive failed: %d", r);
1257
1258 if (is_ipc_notify(ipc_status)) {
1259 switch (m.m_source) {
1260 case HARDWARE: /* interrupt */
1261 atl2_intr(&m);
1262
1263 break;
1264
1265 case TTY_PROC_NR: /* function key */
1266 atl2_dump();
1267
1268 break;
1269
1270 default:
1271 printf("ATL2: illegal notify from %d\n",
1272 m.m_source);
1273 }
1274
1275 continue;
1276 }
1277
1278 /* Process requests from Inet. */
1279 switch (m.m_type) {
1280 case DL_CONF: atl2_conf(&m); break;
1281 case DL_GETSTAT_S: atl2_getstat(&m); break;
1282 case DL_WRITEV_S: atl2_writev(&m, FALSE); break;
1283 case DL_READV_S: atl2_readv(&m, FALSE); break;
1284 default:
1285 printf("ATL2: illegal message %d from %d\n",
1286 m.m_type, m.m_source);
1287 }
1288 }
1289 }
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