kernel/arch/i386/system.c

   1 /* system dependent functions for use inside the whole kernel. */
   2
   3 #include "../../kernel.h"
   4
   5 #include <unistd.h>
   6 #include <ctype.h>
   7 #include <string.h>
   8 #include <ibm/cmos.h>
   9 #include <ibm/bios.h>
  10 #include <minix/portio.h>
  11 #include <minix/cpufeature.h>
  12 #include <a.out.h>
  13 #include <archconst.h>
  14
  15 #include "proto.h"
  16 #include "../../proc.h"
  17 #include "../../debug.h"
  18
  19 #ifdef CONFIG_APIC
  20 #include "apic.h"
  21 #endif
  22
  23 /* set MP and NE flags to handle FPU exceptions in native mode. */
  24 #define CR0_MP_NE       0x0022
  25 /* set CR4.OSFXSR[bit 9] if FXSR is supported. */
  26 #define CR4_OSFXSR      (1L<<9)
  27 /* set OSXMMEXCPT[bit 10] if we provide #XM handler. */
  28 #define CR4_OSXMMEXCPT  (1L<<10)
  29
  30 FORWARD _PROTOTYPE( void ser_debug, (int c));
  31
  32 PUBLIC void arch_monitor(void)
  33 {
  34         level0(monitor);
  35 }
  36
  37 PUBLIC int cpu_has_tsc;
  38
  39 PUBLIC void arch_shutdown(int how)
  40 {
  41         /* Mask all interrupts, including the clock. */
  42         outb( INT_CTLMASK, ~0);
  43
  44         if(minix_panicing) {
  45                 /* We're panicing? Then retrieve and decode currently
  46                  * loaded segment selectors.
  47                  */
  48                 printseg("cs: ", 1, proc_ptr, read_cs());
  49                 printseg("ds: ", 0, proc_ptr, read_ds());
  50                 if(read_ds() != read_ss()) {
  51                         printseg("ss: ", 0, NULL, read_ss());
  52                 }
  53         }
  54
  55         if(how != RBT_RESET) {
  56                 /* return to boot monitor */
  57
  58                 outb( INT_CTLMASK, 0);
  59                 outb( INT2_CTLMASK, 0);
  60
  61                 /* Return to the boot monitor. Set
  62                  * the program if not already done.
  63                  */
  64                 if (how != RBT_MONITOR)
  65                         arch_set_params("", 1);
  66                 if(minix_panicing) {
  67                         int source, dest;
  68                         static char mybuffer[sizeof(params_buffer)];
  69                         char *lead = "echo \\n*** kernel messages:\\n";
  70                         int leadlen = strlen(lead);
  71                         strcpy(mybuffer, lead);
  72
  73 #define DECSOURCE source = (source - 1 + _KMESS_BUF_SIZE) % _KMESS_BUF_SIZE
  74
  75                         dest = sizeof(mybuffer)-1;
  76                         mybuffer[dest--] = '\0';
  77
  78                         source = kmess.km_next;
  79                         DECSOURCE;
  80
  81                         while(dest >= leadlen) {
  82                                 char c = kmess.km_buf[source];
  83                                 if(c == '\n') {
  84                                         mybuffer[dest--] = 'n';
  85                                         mybuffer[dest] = '\\';
  86                                 } else if(isprint(c) &&
  87                                         c != '\'' && c != '"' &&
  88                                         c != '\\' && c != ';') {
  89                                         mybuffer[dest] = c;
  90                                 } else  mybuffer[dest] = ' ';
  91
  92                                 DECSOURCE;
  93                                 dest--;
  94                         }
  95
  96                         arch_set_params(mybuffer, strlen(mybuffer)+1);
  97                 }
  98                 arch_monitor();
  99         } else {
 100                 /* Reset the system by forcing a processor shutdown. First stop
 101                  * the BIOS memory test by setting a soft reset flag.
 102                  */
 103                 u16_t magic = STOP_MEM_CHECK;
 104                 phys_copy(vir2phys(&magic), SOFT_RESET_FLAG_ADDR,
 105                 SOFT_RESET_FLAG_SIZE);
 106                 level0(reset);
 107         }
 108 }
 109
 110 /* address of a.out headers, set in mpx386.s */
 111 phys_bytes aout;
 112
 113 PUBLIC void arch_get_aout_headers(int i, struct exec *h)
 114 {
 115         /* The bootstrap loader created an array of the a.out headers at
 116          * absolute address 'aout'. Get one element to h.
 117          */
 118         phys_copy(aout + i * A_MINHDR, vir2phys(h), (phys_bytes) A_MINHDR);
 119 }
 120
 121 PRIVATE void tss_init(struct tss_s * tss, void * kernel_stack, unsigned cpu)
 122 {
 123         /*
 124          * make space for process pointer and cpu id and point to the first
 125          * usable word
 126          */
 127         tss->sp0 = ((unsigned) kernel_stack) - 2 * sizeof(void *);
 128         tss->ss0 = DS_SELECTOR;
 129
 130         /*
 131          * set the cpu id at the top of the stack so we know on which cpu is
 132          * this stak in use when we trap to kernel
 133          */
 134         *((reg_t *)(tss->sp0 + 1 * sizeof(reg_t))) = cpu;
 135 }
 136
 137 PUBLIC void arch_init(void)
 138 {
 139         unsigned short cw, sw;
 140
 141         fninit();
 142         sw = fnstsw();
 143         fnstcw(&cw);
 144
 145         if((sw & 0xff) == 0 &&
 146            (cw & 0x103f) == 0x3f) {
 147                 /* We have some sort of FPU, but don't check exact model.
 148                  * Set CR0_NE and CR0_MP to handle fpu exceptions
 149                  * in native mode. */
 150                 write_cr0(read_cr0() | CR0_MP_NE);
 151                 fpu_presence = 1;
 152                 if(_cpufeature(_CPUF_I386_FXSR)) {
 153                         register struct proc *rp;
 154                         phys_bytes aligned_fp_area;
 155
 156                         /* Enable FXSR feature usage. */
 157                         write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT);
 158                         osfxsr_feature = 1;
 159
 160                         for (rp = BEG_PROC_ADDR; rp < END_PROC_ADDR; ++rp) {
 161                                 /* FXSR requires 16-byte alignment of memory
 162                                  * image, but unfortunately some old tools
 163                                  * (probably linker) ignores ".balign 16"
 164                                  * applied to our memory image.
 165                                  * Thus we have to do manual alignment.
 166                                  */
 167                                 aligned_fp_area =
 168                                         (phys_bytes) &rp->p_fpu_state.fpu_image;
 169                                 if(aligned_fp_area % FPUALIGN) {
 170                                     aligned_fp_area += FPUALIGN -
 171                                                    (aligned_fp_area % FPUALIGN);
 172                                 }
 173                                 rp->p_fpu_state.fpu_save_area_p =
 174                                                     (void *) aligned_fp_area;
 175                         }
 176                 } else {
 177                         osfxsr_feature = 0;
 178                 }
 179         } else {
 180                 /* No FPU presents. */
 181                 fpu_presence = 0;
 182                 osfxsr_feature = 0;
 183                 return;
 184         }
 185
 186 #ifdef CONFIG_APIC
 187         /*
 188          * this is setting kernel segments to cover most of the phys memory. The
 189          * value is high enough to reach local APIC nad IOAPICs before paging is
 190          * turned on.
 191          */
 192         prot_set_kern_seg_limit(0xfff00000);
 193         reload_ds();
 194 #endif
 195
 196         idt_init();
 197
 198         tss_init(&tss, &k_boot_stktop, 0);
 199
 200 #if defined(CONFIG_APIC) && !defined(CONFIG_SMP)
 201         if (config_no_apic) {
 202                 BOOT_VERBOSE(kprintf("APIC disabled, using legacy PIC\n"));
 203         }
 204         else if (!apic_single_cpu_init()) {
 205                 BOOT_VERBOSE(kprintf("APIC not present, using legacy PIC\n"));
 206         }
 207 #endif
 208
 209 }
 210
 211 #define COM1_BASE       0x3F8
 212 #define COM1_THR        (COM1_BASE + 0)
 213 #define COM1_RBR (COM1_BASE + 0)
 214 #define COM1_LSR        (COM1_BASE + 5)
 215 #define         LSR_DR          0x01
 216 #define         LSR_THRE        0x20
 217
 218 PUBLIC void ser_putc(char c)
 219 {
 220         int i;
 221         int lsr, thr;
 222
 223         lsr= COM1_LSR;
 224         thr= COM1_THR;
 225         for (i= 0; i<100000; i++)
 226         {
 227                 if (inb( lsr) & LSR_THRE)
 228                         break;
 229         }
 230         outb( thr, c);
 231 }
 232
 233 /*===========================================================================*
 234  *                              do_ser_debug                                 *
 235  *===========================================================================*/
 236 PUBLIC void do_ser_debug()
 237 {
 238         u8_t c, lsr;
 239
 240         lsr= inb(COM1_LSR);
 241         if (!(lsr & LSR_DR))
 242                 return;
 243         c = inb(COM1_RBR);
 244         ser_debug(c);
 245 }
 246
 247 PRIVATE void ser_dump_queues(void)
 248 {
 249         int q;
 250         for(q = 0; q < NR_SCHED_QUEUES; q++) {
 251                 struct proc *p;
 252                 if(rdy_head[q])
 253                         printf("%2d: ", q);
 254                 for(p = rdy_head[q]; p; p = p->p_nextready) {
 255                         printf("%s / %d  ", p->p_name, p->p_endpoint);
 256                 }
 257                 printf("\n");
 258         }
 259
 260 }
 261
 262 PRIVATE void ser_dump_segs(void)
 263 {
 264         struct proc *pp;
 265         for (pp= BEG_PROC_ADDR; pp < END_PROC_ADDR; pp++)
 266         {
 267                 if (isemptyp(pp))
 268                         continue;
 269                 kprintf("%d: %s ep %d\n", proc_nr(pp), pp->p_name, pp->p_endpoint);
 270                 printseg("cs: ", 1, pp, pp->p_reg.cs);
 271                 printseg("ds: ", 0, pp, pp->p_reg.ds);
 272                 if(pp->p_reg.ss != pp->p_reg.ds) {
 273                         printseg("ss: ", 0, pp, pp->p_reg.ss);
 274                 }
 275         }
 276 }
 277
 278 PRIVATE void ser_debug(int c)
 279 {
 280         int u = 0;
 281
 282         serial_debug_active = 1;
 283         /* Disable interrupts so that we get a consistent state. */
 284         if(!intr_disabled()) { lock; u = 1; };
 285
 286         switch(c)
 287         {
 288         case 'Q':
 289                 minix_shutdown(NULL);
 290                 NOT_REACHABLE;
 291         case '1':
 292                 ser_dump_proc();
 293                 break;
 294         case '2':
 295                 ser_dump_queues();
 296                 break;
 297         case '3':
 298                 ser_dump_segs();
 299                 break;
 300 #if DEBUG_TRACE
 301 #define TOGGLECASE(ch, flag)                            \
 302         case ch: {                                      \
 303                 if(verboseflags & flag) {               \
 304                         verboseflags &= ~flag;          \
 305                         printf("%s disabled\n", #flag); \
 306                 } else {                                \
 307                         verboseflags |= flag;           \
 308                         printf("%s enabled\n", #flag);  \
 309                 }                                       \
 310                 break;                                  \
 311                 }
 312         TOGGLECASE('8', VF_SCHEDULING)
 313         TOGGLECASE('9', VF_PICKPROC)
 314 #endif
 315         }
 316         serial_debug_active = 0;
 317         if(u) { unlock; }
 318 }
 319
 320 PRIVATE void printslot(struct proc *pp, int level)
 321 {
 322         struct proc *depproc = NULL;
 323         int dep = NONE;
 324 #define COL { int i; for(i = 0; i < level; i++) printf("> "); }
 325
 326         if(level >= NR_PROCS) {
 327                 kprintf("loop??\n");
 328                 return;
 329         }
 330
 331         COL
 332
 333         kprintf("%d: %s %d prio %d/%d time %d/%d cr3 0x%lx rts %s misc %s",
 334                 proc_nr(pp), pp->p_name, pp->p_endpoint,
 335                 pp->p_priority, pp->p_max_priority, pp->p_user_time,
 336                 pp->p_sys_time, pp->p_seg.p_cr3,
 337                 rtsflagstr(pp->p_rts_flags), miscflagstr(pp->p_misc_flags));
 338
 339         if(pp->p_rts_flags & RTS_SENDING) {
 340                 dep = pp->p_sendto_e;
 341                 kprintf(" to: ");
 342         } else if(pp->p_rts_flags & RTS_RECEIVING) {
 343                 dep = pp->p_getfrom_e;
 344                 kprintf(" from: ");
 345         }
 346
 347         if(dep != NONE) {
 348                 if(dep == ANY) {
 349                         kprintf(" ANY\n");
 350                 } else {
 351                         int procno;
 352                         if(!isokendpt(dep, &procno)) {
 353                                 kprintf(" ??? %d\n", dep);
 354                         } else {
 355                                 depproc = proc_addr(procno);
 356                                 if(isemptyp(depproc)) {
 357                                         kprintf(" empty slot %d???\n", procno);
 358                                         depproc = NULL;
 359                                 } else {
 360                                         kprintf(" %s\n", depproc->p_name);
 361                                 }
 362                         }
 363                 }
 364         } else {
 365                 kprintf("\n");
 366         }
 367
 368         COL
 369         proc_stacktrace(pp);
 370
 371
 372         if(depproc)
 373                 printslot(depproc, level+1);
 374 }
 375
 376
 377 PUBLIC void ser_dump_proc()
 378 {
 379         struct proc *pp;
 380
 381         for (pp= BEG_PROC_ADDR; pp < END_PROC_ADDR; pp++)
 382         {
 383                 if (isemptyp(pp))
 384                         continue;
 385                 printslot(pp, 0);
 386         }
 387 }
 388
 389 #if SPROFILE
 390
 391 PUBLIC int arch_init_profile_clock(u32_t freq)
 392 {
 393   int r;
 394   /* Set CMOS timer frequency. */
 395   outb(RTC_INDEX, RTC_REG_A);
 396   outb(RTC_IO, RTC_A_DV_OK | freq);
 397   /* Enable CMOS timer interrupts. */
 398   outb(RTC_INDEX, RTC_REG_B);
 399   r = inb(RTC_IO);
 400   outb(RTC_INDEX, RTC_REG_B);
 401   outb(RTC_IO, r | RTC_B_PIE);
 402   /* Mandatory read of CMOS register to enable timer interrupts. */
 403   outb(RTC_INDEX, RTC_REG_C);
 404   inb(RTC_IO);
 405
 406   return CMOS_CLOCK_IRQ;
 407 }
 408
 409 PUBLIC void arch_stop_profile_clock(void)
 410 {
 411   int r;
 412   /* Disable CMOS timer interrupts. */
 413   outb(RTC_INDEX, RTC_REG_B);
 414   r = inb(RTC_IO);
 415   outb(RTC_INDEX, RTC_REG_B);
 416   outb(RTC_IO, r & ~RTC_B_PIE);
 417 }
 418
 419 PUBLIC void arch_ack_profile_clock(void)
 420 {
 421   /* Mandatory read of CMOS register to re-enable timer interrupts. */
 422   outb(RTC_INDEX, RTC_REG_C);
 423   inb(RTC_IO);
 424 }
 425
 426 #endif
 427
 428 #define COLOR_BASE      0xB8000L
 429
 430 PRIVATE void cons_setc(int pos, int c)
 431 {
 432         char ch;
 433
 434         ch= c;
 435         phys_copy(vir2phys((vir_bytes)&ch), COLOR_BASE+(20*80+pos)*2, 1);
 436 }
 437
 438 PRIVATE void cons_seth(int pos, int n)
 439 {
 440         n &= 0xf;
 441         if (n < 10)
 442                 cons_setc(pos, '0'+n);
 443         else
 444                 cons_setc(pos, 'A'+(n-10));
 445 }
 446
 447 /* Saved by mpx386.s into these variables. */
 448 u32_t params_size, params_offset, mon_ds;
 449
 450 PUBLIC int arch_get_params(char *params, int maxsize)
 451 {
 452         phys_copy(seg2phys(mon_ds) + params_offset, vir2phys(params),
 453                 MIN(maxsize, params_size));
 454         params[maxsize-1] = '\0';
 455         return OK;
 456 }
 457
 458 PUBLIC int arch_set_params(char *params, int size)
 459 {
 460         if(size > params_size)
 461                 return E2BIG;
 462         phys_copy(vir2phys(params), seg2phys(mon_ds) + params_offset, size);
 463         return OK;
 464 }
 465
 466 PUBLIC void arch_do_syscall(struct proc *proc)
 467 {
 468 /* Perform a previously postponed system call.
 469  */
 470   int call_nr, src_dst_e;
 471   message *m_ptr;
 472   long bit_map;
 473
 474   /* Get the system call parameters from their respective registers. */
 475   call_nr = proc->p_reg.cx;
 476   src_dst_e = proc->p_reg.retreg;
 477   m_ptr = (message *) proc->p_reg.bx;
 478   bit_map = proc->p_reg.dx;
 479
 480   /* sys_call() expects the given process's memory to be accessible. */
 481   vm_set_cr3(proc);
 482
 483   /* Make the system call, for real this time. */
 484   proc->p_reg.retreg = sys_call(call_nr, src_dst_e, m_ptr, bit_map);
 485 }
 486
 487 PUBLIC struct proc * arch_finish_schedcheck(void)
 488 {
 489         char * stk;
 490         stk = (char *)tss.sp0;
 491         /* set pointer to the process to run on the stack */
 492         *((reg_t *)stk) = (reg_t) proc_ptr;
 493         return proc_ptr;
 494 }