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etc/protocols - sync with NetBSD-8
[minix.git] / sys / dev / pci / pci_subr.c
blob462fd5672df9e36dc03d86c6fbe5bc93d71a2864
1 /* $NetBSD: pci_subr.c,v 1.137 2015/10/03 15:22:14 joerg Exp $ */
2
3 /*
4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
5 * Copyright (c) 1995, 1996, 1998, 2000
6 * Christopher G. Demetriou. All rights reserved.
7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Charles M. Hannum.
20 * 4. The name of the author may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 #if defined(__minix) && defined(_PCI_SERVER)
36 /* This is a quick hack, simple copy of the file, until we can use it as is. */
37 #include <sys/types.h>
38
39 #include <stdint.h>
40 #include <stdbool.h>
41 #include <stdio.h>
42
43 #include <pci.h>
44 #include <dev/pci/pcireg.h>
45 #include <dev/pci/pci_verbose.h>
46 #include <dev/pci/pcidevs.h>
47 #include <dev/pci/pcidevs_data.h>
48
49 const char *pci_baseclass_name(pcireg_t reg);
50 const char *pci_subclass_name(pcireg_t reg);
51 #else
52 /*
53 * PCI autoconfiguration support functions.
54 *
55 * Note: This file is also built into a userland library (libpci).
56 * Pay attention to this when you make modifications.
57 */
58
59 #include <sys/cdefs.h>
60 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.137 2015/10/03 15:22:14 joerg Exp $");
61
62 #ifdef _KERNEL_OPT
63 #include "opt_pci.h"
64 #endif
65
66 #include <sys/param.h>
67
68 #ifdef _KERNEL
69 #include <sys/systm.h>
70 #include <sys/intr.h>
71 #include <sys/module.h>
72 #else
73 #include <pci.h>
74 #include <stdbool.h>
75 #include <stdio.h>
76 #include <stdlib.h>
77 #include <string.h>
78 #endif
79
80 #include <dev/pci/pcireg.h>
81 #ifdef _KERNEL
82 #include <dev/pci/pcivar.h>
83 #else
84 #include <dev/pci/pci_verbose.h>
85 #include <dev/pci/pcidevs.h>
86 #include <dev/pci/pcidevs_data.h>
87 #endif
88 #endif /* defined(__minix) && defined(_PCI_SERVER) */
89
90 /*
91 * Descriptions of known PCI classes and subclasses.
92 *
93 * Subclasses are described in the same way as classes, but have a
94 * NULL subclass pointer.
95 */
96 struct pci_class {
97 const char *name;
98 u_int val; /* as wide as pci_{,sub}class_t */
99 const struct pci_class *subclasses;
100 };
101
102 /*
103 * Class 0x00.
104 * Before rev. 2.0.
105 */
106 static const struct pci_class pci_subclass_prehistoric[] = {
107 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, },
108 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, },
109 { NULL, 0, NULL, },
110 };
111
112 /*
113 * Class 0x01.
114 * Mass storage controller
115 */
116
117 /* ATA programming interface */
118 static const struct pci_class pci_interface_ata[] = {
119 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, },
120 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, },
121 { NULL, 0, NULL, },
122 };
123
124 /* SATA programming interface */
125 static const struct pci_class pci_interface_sata[] = {
126 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, },
127 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, },
128 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, },
129 { NULL, 0, NULL, },
130 };
131
132 /* Flash programming interface */
133 static const struct pci_class pci_interface_nvm[] = {
134 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, },
135 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, },
136 { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, },
137 { NULL, 0, NULL, },
138 };
139
140 /* Subclasses */
141 static const struct pci_class pci_subclass_mass_storage[] = {
142 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, },
143 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, },
144 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, },
145 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, },
146 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, },
147 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA,
148 pci_interface_ata, },
149 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA,
150 pci_interface_sata, },
151 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, },
152 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM,
153 pci_interface_nvm, },
154 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, },
155 { NULL, 0, NULL, },
156 };
157
158 /*
159 * Class 0x02.
160 * Network controller.
161 */
162 static const struct pci_class pci_subclass_network[] = {
163 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, },
164 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, },
165 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, },
166 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, },
167 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, },
168 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, },
169 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, },
170 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, },
171 { NULL, 0, NULL, },
172 };
173
174 /*
175 * Class 0x03.
176 * Display controller.
177 */
178
179 /* VGA programming interface */
180 static const struct pci_class pci_interface_vga[] = {
181 { "", PCI_INTERFACE_VGA_VGA, NULL, },
182 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, },
183 { NULL, 0, NULL, },
184 };
185 /* Subclasses */
186 static const struct pci_class pci_subclass_display[] = {
187 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,},
188 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, },
189 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, },
190 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, },
191 { NULL, 0, NULL, },
192 };
193
194 /*
195 * Class 0x04.
196 * Multimedia device.
197 */
198 static const struct pci_class pci_subclass_multimedia[] = {
199 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, },
200 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, },
201 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,},
202 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, },
203 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, },
204 { NULL, 0, NULL, },
205 };
206
207 /*
208 * Class 0x05.
209 * Memory controller.
210 */
211 static const struct pci_class pci_subclass_memory[] = {
212 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, },
213 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, },
214 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, },
215 { NULL, 0, NULL, },
216 };
217
218 /*
219 * Class 0x06.
220 * Bridge device.
221 */
222
223 /* PCI bridge programming interface */
224 static const struct pci_class pci_interface_pcibridge[] = {
225 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, },
226 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, },
227 { NULL, 0, NULL, },
228 };
229
230 /* Semi-transparent PCI-to-PCI bridge programming interface */
231 static const struct pci_class pci_interface_stpci[] = {
232 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, },
233 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, },
234 { NULL, 0, NULL, },
235 };
236
237 /* Advanced Switching programming interface */
238 static const struct pci_class pci_interface_advsw[] = {
239 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, },
240 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, },
241 { NULL, 0, NULL, },
242 };
243
244 /* Subclasses */
245 static const struct pci_class pci_subclass_bridge[] = {
246 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, },
247 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, },
248 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, },
249 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, },
250 { "PCI", PCI_SUBCLASS_BRIDGE_PCI,
251 pci_interface_pcibridge, },
252 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, },
253 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, },
254 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, },
255 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, },
256 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI,
257 pci_interface_stpci, },
258 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, },
259 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW,
260 pci_interface_advsw, },
261 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, },
262 { NULL, 0, NULL, },
263 };
264
265 /*
266 * Class 0x07.
267 * Simple communications controller.
268 */
269
270 /* Serial controller programming interface */
271 static const struct pci_class pci_interface_serial[] = {
272 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, },
273 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, },
274 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, },
275 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, },
276 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, },
277 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, },
278 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, },
279 { NULL, 0, NULL, },
280 };
281
282 /* Parallel controller programming interface */
283 static const struct pci_class pci_interface_parallel[] = {
284 { "", PCI_INTERFACE_PARALLEL, NULL,},
285 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,},
286 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,},
287 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,},
288 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,},
289 { NULL, 0, NULL,},
290 };
291
292 /* Modem programming interface */
293 static const struct pci_class pci_interface_modem[] = {
294 { "", PCI_INTERFACE_MODEM, NULL,},
295 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,},
296 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,},
297 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,},
298 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,},
299 { NULL, 0, NULL,},
300 };
301
302 /* Subclasses */
303 static const struct pci_class pci_subclass_communications[] = {
304 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL,
305 pci_interface_serial, },
306 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL,
307 pci_interface_parallel, },
308 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,},
309 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM,
310 pci_interface_modem, },
311 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,},
312 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,},
313 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,},
314 { NULL, 0, NULL,},
315 };
316
317 /*
318 * Class 0x08.
319 * Base system peripheral.
320 */
321
322 /* PIC programming interface */
323 static const struct pci_class pci_interface_pic[] = {
324 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, },
325 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, },
326 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, },
327 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, },
328 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, },
329 { NULL, 0, NULL, },
330 };
331
332 /* DMA programming interface */
333 static const struct pci_class pci_interface_dma[] = {
334 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, },
335 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, },
336 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, },
337 { NULL, 0, NULL, },
338 };
339
340 /* Timer programming interface */
341 static const struct pci_class pci_interface_tmr[] = {
342 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, },
343 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, },
344 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, },
345 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, },
346 { NULL, 0, NULL, },
347 };
348
349 /* RTC programming interface */
350 static const struct pci_class pci_interface_rtc[] = {
351 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, },
352 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, },
353 { NULL, 0, NULL, },
354 };
355
356 /* Subclasses */
357 static const struct pci_class pci_subclass_system[] = {
358 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,},
359 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,},
360 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,},
361 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,},
362 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, },
363 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, },
364 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, },
365 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, },
366 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, },
367 { NULL, 0, NULL, },
368 };
369
370 /*
371 * Class 0x09.
372 * Input device.
373 */
374
375 /* Gameport programming interface */
376 static const struct pci_class pci_interface_game[] = {
377 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, },
378 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, },
379 { NULL, 0, NULL, },
380 };
381
382 /* Subclasses */
383 static const struct pci_class pci_subclass_input[] = {
384 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, },
385 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, },
386 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, },
387 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, },
388 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT,
389 pci_interface_game, },
390 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, },
391 { NULL, 0, NULL, },
392 };
393
394 /*
395 * Class 0x0a.
396 * Docking station.
397 */
398 static const struct pci_class pci_subclass_dock[] = {
399 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, },
400 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, },
401 { NULL, 0, NULL, },
402 };
403
404 /*
405 * Class 0x0b.
406 * Processor.
407 */
408 static const struct pci_class pci_subclass_processor[] = {
409 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, },
410 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, },
411 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, },
412 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, },
413 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, },
414 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, },
415 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, },
416 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, },
417 { NULL, 0, NULL, },
418 };
419
420 /*
421 * Class 0x0c.
422 * Serial bus controller.
423 */
424
425 /* IEEE1394 programming interface */
426 static const struct pci_class pci_interface_ieee1394[] = {
427 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,},
428 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,},
429 { NULL, 0, NULL,},
430 };
431
432 /* USB programming interface */
433 static const struct pci_class pci_interface_usb[] = {
434 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, },
435 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, },
436 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, },
437 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, },
438 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, },
439 { "device", PCI_INTERFACE_USB_DEVICE, NULL, },
440 { NULL, 0, NULL, },
441 };
442
443 /* IPMI programming interface */
444 static const struct pci_class pci_interface_ipmi[] = {
445 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,},
446 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,},
447 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,},
448 { NULL, 0, NULL,},
449 };
450
451 /* Subclasses */
452 static const struct pci_class pci_subclass_serialbus[] = {
453 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE,
454 pci_interface_ieee1394, },
455 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, },
456 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, },
457 { "USB", PCI_SUBCLASS_SERIALBUS_USB,
458 pci_interface_usb, },
459 /* XXX Fiber Channel/_FIBRECHANNEL */
460 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, },
461 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, },
462 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,},
463 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI,
464 pci_interface_ipmi, },
465 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, },
466 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, },
467 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, },
468 { NULL, 0, NULL, },
469 };
470
471 /*
472 * Class 0x0d.
473 * Wireless Controller.
474 */
475 static const struct pci_class pci_subclass_wireless[] = {
476 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, },
477 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, },
478 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, },
479 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, },
480 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, },
481 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, },
482 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, },
483 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, },
484 { NULL, 0, NULL, },
485 };
486
487 /*
488 * Class 0x0e.
489 * Intelligent IO controller.
490 */
491
492 /* Intelligent IO programming interface */
493 static const struct pci_class pci_interface_i2o[] = {
494 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,},
495 { NULL, 0, NULL,},
496 };
497
498 /* Subclasses */
499 static const struct pci_class pci_subclass_i2o[] = {
500 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,},
501 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, },
502 { NULL, 0, NULL, },
503 };
504
505 /*
506 * Class 0x0f.
507 * Satellite communication controller.
508 */
509 static const struct pci_class pci_subclass_satcom[] = {
510 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, },
511 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, },
512 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, },
513 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, },
514 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, },
515 { NULL, 0, NULL, },
516 };
517
518 /*
519 * Class 0x10.
520 * Encryption/Decryption controller.
521 */
522 static const struct pci_class pci_subclass_crypto[] = {
523 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, },
524 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,},
525 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, },
526 { NULL, 0, NULL, },
527 };
528
529 /*
530 * Class 0x11.
531 * Data aquuisition and signal processing controller.
532 */
533 static const struct pci_class pci_subclass_dasp[] = {
534 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, },
535 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, },
536 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, },
537 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, },
538 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, },
539 { NULL, 0, NULL, },
540 };
541
542 /* List of classes */
543 static const struct pci_class pci_class[] = {
544 { "prehistoric", PCI_CLASS_PREHISTORIC,
545 pci_subclass_prehistoric, },
546 { "mass storage", PCI_CLASS_MASS_STORAGE,
547 pci_subclass_mass_storage, },
548 { "network", PCI_CLASS_NETWORK,
549 pci_subclass_network, },
550 { "display", PCI_CLASS_DISPLAY,
551 pci_subclass_display, },
552 { "multimedia", PCI_CLASS_MULTIMEDIA,
553 pci_subclass_multimedia, },
554 { "memory", PCI_CLASS_MEMORY,
555 pci_subclass_memory, },
556 { "bridge", PCI_CLASS_BRIDGE,
557 pci_subclass_bridge, },
558 { "communications", PCI_CLASS_COMMUNICATIONS,
559 pci_subclass_communications, },
560 { "system", PCI_CLASS_SYSTEM,
561 pci_subclass_system, },
562 { "input", PCI_CLASS_INPUT,
563 pci_subclass_input, },
564 { "dock", PCI_CLASS_DOCK,
565 pci_subclass_dock, },
566 { "processor", PCI_CLASS_PROCESSOR,
567 pci_subclass_processor, },
568 { "serial bus", PCI_CLASS_SERIALBUS,
569 pci_subclass_serialbus, },
570 { "wireless", PCI_CLASS_WIRELESS,
571 pci_subclass_wireless, },
572 { "I2O", PCI_CLASS_I2O,
573 pci_subclass_i2o, },
574 { "satellite comm", PCI_CLASS_SATCOM,
575 pci_subclass_satcom, },
576 { "crypto", PCI_CLASS_CRYPTO,
577 pci_subclass_crypto, },
578 { "DASP", PCI_CLASS_DASP,
579 pci_subclass_dasp, },
580 { "undefined", PCI_CLASS_UNDEFINED,
581 NULL, },
582 { NULL, 0,
583 NULL, },
584 };
585
586 #if defined(__minix) && defined(_PCI_SERVER)
587 const char *
588 pci_baseclass_name(pcireg_t reg)
589 {
590 const struct pci_class *classp = pci_class;
591
592 while (classp->name != NULL) {
593 if (PCI_CLASS(reg) == classp->val)
594 break;
595 classp++;
596 }
597
598 return classp->name;
599 }
600
601 const char *
602 pci_subclass_name(pcireg_t reg)
603 {
604 const struct pci_class *classp = pci_class;
605 const struct pci_class *subclassp;
606
607 while (classp->name != NULL) {
608 if (PCI_CLASS(reg) == classp->val)
609 break;
610 classp++;
611 }
612
613 subclassp = (classp->name != NULL) ? classp->subclasses : NULL;
614 while (subclassp && subclassp->name != NULL) {
615 if (PCI_SUBCLASS(reg) == subclassp->val)
616 break;
617 subclassp++;
618 }
619
620 if (subclassp) {
621 return subclassp->name;
622 } else {
623 return NULL;
624 }
625 }
626 #endif /* defined(__minix) && defined(_PCI_SERVER) */
627
628 DEV_VERBOSE_DEFINE(pci);
629
630 #if defined(__minix) && !defined(_PCI_SERVER)
631
632 void
633 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp,
634 size_t l)
635 {
636 pci_class_t pciclass;
637 pci_subclass_t subclass;
638 pci_interface_t interface;
639 pci_revision_t revision;
640 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN];
641 const struct pci_class *classp, *subclassp, *interfacep;
642 char *ep;
643
644 ep = cp + l;
645
646 pciclass = PCI_CLASS(class_reg);
647 subclass = PCI_SUBCLASS(class_reg);
648 interface = PCI_INTERFACE(class_reg);
649 revision = PCI_REVISION(class_reg);
650
651 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg));
652 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg),
653 PCI_PRODUCT(id_reg));
654
655 classp = pci_class;
656 while (classp->name != NULL) {
657 if (pciclass == classp->val)
658 break;
659 classp++;
660 }
661
662 subclassp = (classp->name != NULL) ? classp->subclasses : NULL;
663 while (subclassp && subclassp->name != NULL) {
664 if (subclass == subclassp->val)
665 break;
666 subclassp++;
667 }
668
669 interfacep = (subclassp && subclassp->name != NULL) ?
670 subclassp->subclasses : NULL;
671 while (interfacep && interfacep->name != NULL) {
672 if (interface == interfacep->val)
673 break;
674 interfacep++;
675 }
676
677 cp += snprintf(cp, ep - cp, "%s %s", vendor, product);
678 if (showclass) {
679 cp += snprintf(cp, ep - cp, " (");
680 if (classp->name == NULL)
681 cp += snprintf(cp, ep - cp,
682 "class 0x%02x, subclass 0x%02x", pciclass, subclass);
683 else {
684 if (subclassp == NULL || subclassp->name == NULL)
685 cp += snprintf(cp, ep - cp,
686 "%s, subclass 0x%02x",
687 classp->name, subclass);
688 else
689 cp += snprintf(cp, ep - cp, "%s %s",
690 subclassp->name, classp->name);
691 }
692 if ((interfacep == NULL) || (interfacep->name == NULL)) {
693 if (interface != 0)
694 cp += snprintf(cp, ep - cp,
695 ", interface 0x%02x", interface);
696 } else if (strncmp(interfacep->name, "", 1) != 0)
697 cp += snprintf(cp, ep - cp, ", %s",
698 interfacep->name);
699 if (revision != 0)
700 cp += snprintf(cp, ep - cp, ", revision 0x%02x",
701 revision);
702 cp += snprintf(cp, ep - cp, ")");
703 }
704 }
705
706 #ifdef _KERNEL
707 void
708 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive,
709 const char *known, int addrev)
710 {
711 char devinfo[256];
712
713 if (known) {
714 aprint_normal(": %s", known);
715 if (addrev)
716 aprint_normal(" (rev. 0x%02x)",
717 PCI_REVISION(pa->pa_class));
718 aprint_normal("\n");
719 } else {
720 pci_devinfo(pa->pa_id, pa->pa_class, 0,
721 devinfo, sizeof(devinfo));
722 aprint_normal(": %s (rev. 0x%02x)\n", devinfo,
723 PCI_REVISION(pa->pa_class));
724 }
725 if (naive)
726 aprint_naive(": %s\n", naive);
727 else
728 aprint_naive("\n");
729 }
730 #endif
731
732 /*
733 * Print out most of the PCI configuration registers. Typically used
734 * in a device attach routine like this:
735 *
736 * #ifdef MYDEV_DEBUG
737 * printf("%s: ", device_xname(sc->sc_dev));
738 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL);
739 * #endif
740 */
741
742 #define i2o(i) ((i) * 4)
743 #define o2i(o) ((o) / 4)
744 #define onoff2(str, rval, bit, onstr, offstr) \
745 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr);
746 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off")
747
748 static void
749 pci_conf_print_common(
750 #ifdef _KERNEL
751 pci_chipset_tag_t pc, pcitag_t tag,
752 #endif
753 const pcireg_t *regs)
754 {
755 const char *name;
756 const struct pci_class *classp, *subclassp;
757 char vendor[PCI_VENDORSTR_LEN];
758 char product[PCI_PRODUCTSTR_LEN];
759 pcireg_t rval;
760 unsigned int num;
761
762 rval = regs[o2i(PCI_ID_REG)];
763 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval));
764 if (name)
765 printf(" Vendor Name: %s (0x%04x)\n", name,
766 PCI_VENDOR(rval));
767 else
768 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval));
769 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval),
770 PCI_PRODUCT(rval));
771 if (name)
772 printf(" Device Name: %s (0x%04x)\n", name,
773 PCI_PRODUCT(rval));
774 else
775 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval));
776
777 rval = regs[o2i(PCI_COMMAND_STATUS_REG)];
778
779 printf(" Command register: 0x%04x\n", rval & 0xffff);
780 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE);
781 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE);
782 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE);
783 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE);
784 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE);
785 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE);
786 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE);
787 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE);
788 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE);
789 onoff("Fast back-to-back transactions", rval,
790 PCI_COMMAND_BACKTOBACK_ENABLE);
791 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE);
792
793 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff);
794 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active",
795 "inactive");
796 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT);
797 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT);
798 onoff("User Definable Features (UDF) support", rval,
799 PCI_STATUS_UDF_SUPPORT);
800 onoff("Fast back-to-back capable", rval,
801 PCI_STATUS_BACKTOBACK_SUPPORT);
802 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR);
803
804 printf(" DEVSEL timing: ");
805 switch (rval & PCI_STATUS_DEVSEL_MASK) {
806 case PCI_STATUS_DEVSEL_FAST:
807 printf("fast");
808 break;
809 case PCI_STATUS_DEVSEL_MEDIUM:
810 printf("medium");
811 break;
812 case PCI_STATUS_DEVSEL_SLOW:
813 printf("slow");
814 break;
815 default:
816 printf("unknown/reserved"); /* XXX */
817 break;
818 }
819 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25);
820
821 onoff("Slave signaled Target Abort", rval,
822 PCI_STATUS_TARGET_TARGET_ABORT);
823 onoff("Master received Target Abort", rval,
824 PCI_STATUS_MASTER_TARGET_ABORT);
825 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT);
826 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR);
827 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT);
828
829 rval = regs[o2i(PCI_CLASS_REG)];
830 for (classp = pci_class; classp->name != NULL; classp++) {
831 if (PCI_CLASS(rval) == classp->val)
832 break;
833 }
834 subclassp = (classp->name != NULL) ? classp->subclasses : NULL;
835 while (subclassp && subclassp->name != NULL) {
836 if (PCI_SUBCLASS(rval) == subclassp->val)
837 break;
838 subclassp++;
839 }
840 if (classp->name != NULL) {
841 printf(" Class Name: %s (0x%02x)\n", classp->name,
842 PCI_CLASS(rval));
843 if (subclassp != NULL && subclassp->name != NULL)
844 printf(" Subclass Name: %s (0x%02x)\n",
845 subclassp->name, PCI_SUBCLASS(rval));
846 else
847 printf(" Subclass ID: 0x%02x\n",
848 PCI_SUBCLASS(rval));
849 } else {
850 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval));
851 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval));
852 }
853 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval));
854 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval));
855
856 rval = regs[o2i(PCI_BHLC_REG)];
857 printf(" BIST: 0x%02x\n", PCI_BIST(rval));
858 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval),
859 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "",
860 PCI_HDRTYPE(rval));
861 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval));
862 num = PCI_CACHELINE(rval);
863 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num);
864 }
865
866 static int
867 pci_conf_print_bar(
868 #ifdef _KERNEL
869 pci_chipset_tag_t pc, pcitag_t tag,
870 #endif
871 const pcireg_t *regs, int reg, const char *name
872 #ifdef _KERNEL
873 , int sizebar
874 #endif
875 )
876 {
877 int width;
878 pcireg_t rval, rval64h;
879 #ifdef _KERNEL
880 int s;
881 pcireg_t mask, mask64h;
882 #endif
883
884 width = 4;
885
886 /*
887 * Section 6.2.5.1, `Address Maps', tells us that:
888 *
889 * 1) The builtin software should have already mapped the
890 * device in a reasonable way.
891 *
892 * 2) A device which wants 2^n bytes of memory will hardwire
893 * the bottom n bits of the address to 0. As recommended,
894 * we write all 1s and see what we get back.
895 */
896
897 rval = regs[o2i(reg)];
898 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM &&
899 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) {
900 rval64h = regs[o2i(reg + 4)];
901 width = 8;
902 } else
903 rval64h = 0;
904
905 #ifdef _KERNEL
906 /* XXX don't size unknown memory type? */
907 if (rval != 0 && sizebar) {
908 /*
909 * The following sequence seems to make some devices
910 * (e.g. host bus bridges, which don't normally
911 * have their space mapped) very unhappy, to
912 * the point of crashing the system.
913 *
914 * Therefore, if the mapping register is zero to
915 * start out with, don't bother trying.
916 */
917 s = splhigh();
918 pci_conf_write(pc, tag, reg, 0xffffffff);
919 mask = pci_conf_read(pc, tag, reg);
920 pci_conf_write(pc, tag, reg, rval);
921 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM &&
922 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) {
923 pci_conf_write(pc, tag, reg + 4, 0xffffffff);
924 mask64h = pci_conf_read(pc, tag, reg + 4);
925 pci_conf_write(pc, tag, reg + 4, rval64h);
926 } else
927 mask64h = 0;
928 splx(s);
929 } else
930 mask = mask64h = 0;
931 #endif /* _KERNEL */
932
933 printf(" Base address register at 0x%02x", reg);
934 if (name)
935 printf(" (%s)", name);
936 printf("\n ");
937 if (rval == 0) {
938 printf("not implemented(?)\n");
939 return width;
940 }
941 printf("type: ");
942 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) {
943 const char *type, *prefetch;
944
945 switch (PCI_MAPREG_MEM_TYPE(rval)) {
946 case PCI_MAPREG_MEM_TYPE_32BIT:
947 type = "32-bit";
948 break;
949 case PCI_MAPREG_MEM_TYPE_32BIT_1M:
950 type = "32-bit-1M";
951 break;
952 case PCI_MAPREG_MEM_TYPE_64BIT:
953 type = "64-bit";
954 break;
955 default:
956 type = "unknown (XXX)";
957 break;
958 }
959 if (PCI_MAPREG_MEM_PREFETCHABLE(rval))
960 prefetch = "";
961 else
962 prefetch = "non";
963 printf("%s %sprefetchable memory\n", type, prefetch);
964 switch (PCI_MAPREG_MEM_TYPE(rval)) {
965 case PCI_MAPREG_MEM_TYPE_64BIT:
966 printf(" base: 0x%016llx, ",
967 PCI_MAPREG_MEM64_ADDR(
968 ((((long long) rval64h) << 32) | rval)));
969 #ifdef _KERNEL
970 if (sizebar)
971 printf("size: 0x%016llx",
972 PCI_MAPREG_MEM64_SIZE(
973 ((((long long) mask64h) << 32) | mask)));
974 else
975 #endif /* _KERNEL */
976 printf("not sized");
977 printf("\n");
978 break;
979 case PCI_MAPREG_MEM_TYPE_32BIT:
980 case PCI_MAPREG_MEM_TYPE_32BIT_1M:
981 default:
982 printf(" base: 0x%08x, ",
983 PCI_MAPREG_MEM_ADDR(rval));
984 #ifdef _KERNEL
985 if (sizebar)
986 printf("size: 0x%08x",
987 PCI_MAPREG_MEM_SIZE(mask));
988 else
989 #endif /* _KERNEL */
990 printf("not sized");
991 printf("\n");
992 break;
993 }
994 } else {
995 #ifdef _KERNEL
996 if (sizebar)
997 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16);
998 #endif /* _KERNEL */
999 printf("i/o\n");
1000 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval));
1001 #ifdef _KERNEL
1002 if (sizebar)
1003 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask));
1004 else
1005 #endif /* _KERNEL */
1006 printf("not sized");
1007 printf("\n");
1008 }
1009
1010 return width;
1011 }
1012
1013 static void
1014 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast)
1015 {
1016 int off, needaddr, neednl;
1017
1018 needaddr = 1;
1019 neednl = 0;
1020 for (off = first; off < pastlast; off += 4) {
1021 if ((off % 16) == 0 || needaddr) {
1022 printf(" 0x%02x:", off);
1023 needaddr = 0;
1024 }
1025 printf(" 0x%08x", regs[o2i(off)]);
1026 neednl = 1;
1027 if ((off % 16) == 12) {
1028 printf("\n");
1029 neednl = 0;
1030 }
1031 }
1032 if (neednl)
1033 printf("\n");
1034 }
1035
1036 static void
1037 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff)
1038 {
1039 pcireg_t rval;
1040
1041 printf("\n AGP Capabilities Register\n");
1042
1043 rval = regs[o2i(capoff)];
1044 printf(" Revision: %d.%d\n",
1045 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval));
1046
1047 /* XXX need more */
1048 }
1049
1050 static const char *
1051 pci_conf_print_pcipm_cap_aux(uint16_t caps)
1052 {
1053
1054 switch ((caps >> 6) & 7) {
1055 case 0: return "self-powered";
1056 case 1: return "55 mA";
1057 case 2: return "100 mA";
1058 case 3: return "160 mA";
1059 case 4: return "220 mA";
1060 case 5: return "270 mA";
1061 case 6: return "320 mA";
1062 case 7:
1063 default: return "375 mA";
1064 }
1065 }
1066
1067 static const char *
1068 pci_conf_print_pcipm_cap_pmrev(uint8_t val)
1069 {
1070 static const char unk[] = "unknown";
1071 static const char *pmrev[8] = {
1072 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk
1073 };
1074 if (val > 7)
1075 return unk;
1076 return pmrev[val];
1077 }
1078
1079 static void
1080 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff)
1081 {
1082 uint16_t caps, pmcsr;
1083 pcireg_t reg;
1084
1085 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT;
1086 reg = regs[o2i(capoff + PCI_PMCSR)];
1087 pmcsr = reg & 0xffff;
1088
1089 printf("\n PCI Power Management Capabilities Register\n");
1090
1091 printf(" Capabilities register: 0x%04x\n", caps);
1092 printf(" Version: %s\n",
1093 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK));
1094 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK);
1095 onoff("Device specific initialization", caps, PCI_PMCR_DSI);
1096 printf(" 3.3V auxiliary current: %s\n",
1097 pci_conf_print_pcipm_cap_aux(caps));
1098 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP);
1099 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP);
1100 onoff("PME# support D0", caps, PCI_PMCR_PME_D0);
1101 onoff("PME# support D1", caps, PCI_PMCR_PME_D1);
1102 onoff("PME# support D2", caps, PCI_PMCR_PME_D2);
1103 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT);
1104 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD);
1105
1106 printf(" Control/status register: 0x%04x\n", pmcsr);
1107 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK);
1108 onoff("PCI Express reserved", (pmcsr >> 2), 1);
1109 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST);
1110 printf(" PME# assertion: %sabled\n",
1111 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis");
1112 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS);
1113 printf(" Bridge Support Extensions register: 0x%02x\n",
1114 (reg >> 16) & 0xff);
1115 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT);
1116 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN);
1117 printf(" Data register: 0x%02x\n", (reg >> 24) & 0xff);
1118
1119 }
1120
1121 /* XXX pci_conf_print_vpd_cap */
1122 /* XXX pci_conf_print_slotid_cap */
1123
1124 static void
1125 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff)
1126 {
1127 uint32_t ctl, mmc, mme;
1128
1129 regs += o2i(capoff);
1130 ctl = *regs++;
1131 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK);
1132 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK);
1133
1134 printf("\n PCI Message Signaled Interrupt\n");
1135
1136 printf(" Message Control register: 0x%04x\n", ctl >> 16);
1137 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE);
1138 printf(" Multiple Message Capable: %s (%d vector%s)\n",
1139 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : "");
1140 printf(" Multiple Message Enabled: %s (%d vector%s)\n",
1141 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : "");
1142 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR);
1143 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK);
1144 printf(" Message Address %sregister: 0x%08x\n",
1145 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++);
1146 if (ctl & PCI_MSI_CTL_64BIT_ADDR) {
1147 printf(" Message Address %sregister: 0x%08x\n",
1148 "(upper) ", *regs++);
1149 }
1150 printf(" Message Data register: 0x%08x\n", *regs++);
1151 if (ctl & PCI_MSI_CTL_PERVEC_MASK) {
1152 printf(" Vector Mask register: 0x%08x\n", *regs++);
1153 printf(" Vector Pending register: 0x%08x\n", *regs++);
1154 }
1155 }
1156
1157 /* XXX pci_conf_print_cpci_hostwap_cap */
1158
1159 /*
1160 * For both command register and status register.
1161 * The argument "idx" is index number (0 to 7).
1162 */
1163 static int
1164 pcix_split_trans(unsigned int idx)
1165 {
1166 static int table[8] = {
1167 1, 2, 3, 4, 8, 12, 16, 32
1168 };
1169
1170 if (idx >= __arraycount(table))
1171 return -1;
1172 return table[idx];
1173 }
1174
1175 static void
1176 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff)
1177 {
1178 pcireg_t reg;
1179 int isbridge;
1180 int i;
1181
1182 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)])
1183 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0;
1184 printf("\n PCI-X %s Capabilities Register\n",
1185 isbridge ? "Bridge" : "Non-bridge");
1186
1187 reg = regs[o2i(capoff)];
1188 if (isbridge != 0) {
1189 printf(" Secondary status register: 0x%04x\n",
1190 (reg & 0xffff0000) >> 16);
1191 onoff("64bit device", reg, PCIX_STATUS_64BIT);
1192 onoff("133MHz capable", reg, PCIX_STATUS_133);
1193 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC);
1194 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX);
1195 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN);
1196 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL);
1197 printf(" Secondary clock frequency: 0x%x\n",
1198 (reg & PCIX_BRIDGE_2NDST_CLKF)
1199 >> PCIX_BRIDGE_2NDST_CLKF_SHIFT);
1200 printf(" Version: 0x%x\n",
1201 (reg & PCIX_BRIDGE_2NDST_VER_MASK)
1202 >> PCIX_BRIDGE_2NDST_VER_SHIFT);
1203 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266);
1204 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533);
1205 } else {
1206 printf(" Command register: 0x%04x\n",
1207 (reg & 0xffff0000) >> 16);
1208 onoff("Data Parity Error Recovery", reg,
1209 PCIX_CMD_PERR_RECOVER);
1210 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER);
1211 printf(" Maximum Burst Read Count: %u\n",
1212 PCIX_CMD_BYTECNT(reg));
1213 printf(" Maximum Split Transactions: %d\n",
1214 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK)
1215 >> PCIX_CMD_SPLTRANS_SHIFT));
1216 }
1217 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */
1218 printf(" %sStatus register: 0x%08x\n",
1219 isbridge ? "Bridge " : "", reg);
1220 printf(" Function: %d\n", PCIX_STATUS_FN(reg));
1221 printf(" Device: %d\n", PCIX_STATUS_DEV(reg));
1222 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg));
1223 onoff("64bit device", reg, PCIX_STATUS_64BIT);
1224 onoff("133MHz capable", reg, PCIX_STATUS_133);
1225 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC);
1226 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX);
1227 if (isbridge != 0) {
1228 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN);
1229 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL);
1230 } else {
1231 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX,
1232 "bridge device", "simple device");
1233 printf(" Designed max memory read byte count: %d\n",
1234 512 << ((reg & PCIX_STATUS_MAXB_MASK)
1235 >> PCIX_STATUS_MAXB_SHIFT));
1236 printf(" Designed max outstanding split transaction: %d\n",
1237 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK)
1238 >> PCIX_STATUS_MAXST_SHIFT));
1239 printf(" MAX cumulative Read Size: %u\n",
1240 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT));
1241 onoff("Received split completion error", reg,
1242 PCIX_STATUS_SCERR);
1243 }
1244 onoff("266MHz capable", reg, PCIX_STATUS_266);
1245 onoff("533MHz capable", reg, PCIX_STATUS_533);
1246
1247 if (isbridge == 0)
1248 return;
1249
1250 /* Only for bridge */
1251 for (i = 0; i < 2; i++) {
1252 reg = regs[o2i(capoff+PCIX_BRIDGE_UP_STCR + (4 * i))];
1253 printf(" %s split transaction control register: 0x%08x\n",
1254 (i == 0) ? "Upstream" : "Downstream", reg);
1255 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP);
1256 printf(" Commitment Limit: %d\n",
1257 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT);
1258 }
1259 }
1260
1261 /* XXX pci_conf_print_ldt_cap */
1262
1263 static void
1264 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff)
1265 {
1266 uint16_t caps;
1267
1268 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT;
1269
1270 printf("\n PCI Vendor Specific Capabilities Register\n");
1271 printf(" Capabilities length: 0x%02x\n", caps & 0xff);
1272 }
1273
1274 static void
1275 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff)
1276 {
1277 pcireg_t val;
1278
1279 val = regs[o2i(capoff + PCI_DEBUG_BASER)];
1280
1281 printf("\n Debugport Capability Register\n");
1282 printf(" Debug base Register: 0x%04x\n",
1283 val >> PCI_DEBUG_BASER_SHIFT);
1284 printf(" port offset: 0x%04x\n",
1285 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT);
1286 printf(" BAR number: %u\n",
1287 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT);
1288 }
1289
1290 /* XXX pci_conf_print_cpci_rsrcctl_cap */
1291 /* XXX pci_conf_print_hotplug_cap */
1292
1293 static void
1294 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff)
1295 {
1296 pcireg_t reg;
1297
1298 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)];
1299
1300 printf("\n Subsystem ID Capability Register\n");
1301 printf(" Subsystem ID : 0x%08x\n", reg);
1302 }
1303
1304 /* XXX pci_conf_print_agp8_cap */
1305 /* XXX pci_conf_print_secure_cap */
1306
1307 static void
1308 pci_print_pcie_L0s_latency(uint32_t val)
1309 {
1310
1311 switch (val) {
1312 case 0x0:
1313 printf("Less than 64ns\n");
1314 break;
1315 case 0x1:
1316 case 0x2:
1317 case 0x3:
1318 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1));
1319 break;
1320 case 0x4:
1321 printf("512ns to less than 1us\n");
1322 break;
1323 case 0x5:
1324 printf("1us to less than 2us\n");
1325 break;
1326 case 0x6:
1327 printf("2us - 4us\n");
1328 break;
1329 case 0x7:
1330 printf("More than 4us\n");
1331 break;
1332 }
1333 }
1334
1335 static void
1336 pci_print_pcie_L1_latency(uint32_t val)
1337 {
1338
1339 switch (val) {
1340 case 0x0:
1341 printf("Less than 1us\n");
1342 break;
1343 case 0x6:
1344 printf("32us - 64us\n");
1345 break;
1346 case 0x7:
1347 printf("More than 64us\n");
1348 break;
1349 default:
1350 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val);
1351 break;
1352 }
1353 }
1354
1355 static void
1356 pci_print_pcie_compl_timeout(uint32_t val)
1357 {
1358
1359 switch (val) {
1360 case 0x0:
1361 printf("50us to 50ms\n");
1362 break;
1363 case 0x5:
1364 printf("16ms to 55ms\n");
1365 break;
1366 case 0x6:
1367 printf("65ms to 210ms\n");
1368 break;
1369 case 0x9:
1370 printf("260ms to 900ms\n");
1371 break;
1372 case 0xa:
1373 printf("1s to 3.5s\n");
1374 break;
1375 default:
1376 printf("unknown %u value\n", val);
1377 break;
1378 }
1379 }
1380
1381 static void
1382 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff)
1383 {
1384 pcireg_t reg; /* for each register */
1385 pcireg_t val; /* for each bitfield */
1386 bool check_link = false;
1387 bool check_slot = false;
1388 bool check_rootport = false;
1389 unsigned int pciever;
1390 static const char * const linkspeeds[] = {"2.5", "5.0", "8.0"};
1391 int i;
1392
1393 printf("\n PCI Express Capabilities Register\n");
1394 /* Capability Register */
1395 reg = regs[o2i(capoff)];
1396 printf(" Capability register: %04x\n", reg >> 16);
1397 pciever = (unsigned int)((reg & 0x000f0000) >> 16);
1398 printf(" Capability version: %u\n", pciever);
1399 printf(" Device type: ");
1400 switch ((reg & 0x00f00000) >> 20) {
1401 case 0x0:
1402 printf("PCI Express Endpoint device\n");
1403 check_link = true;
1404 break;
1405 case 0x1:
1406 printf("Legacy PCI Express Endpoint device\n");
1407 check_link = true;
1408 break;
1409 case 0x4:
1410 printf("Root Port of PCI Express Root Complex\n");
1411 check_link = true;
1412 check_slot = true;
1413 check_rootport = true;
1414 break;
1415 case 0x5:
1416 printf("Upstream Port of PCI Express Switch\n");
1417 break;
1418 case 0x6:
1419 printf("Downstream Port of PCI Express Switch\n");
1420 check_slot = true;
1421 check_rootport = true;
1422 break;
1423 case 0x7:
1424 printf("PCI Express to PCI/PCI-X Bridge\n");
1425 break;
1426 case 0x8:
1427 printf("PCI/PCI-X to PCI Express Bridge\n");
1428 break;
1429 case 0x9:
1430 printf("Root Complex Integrated Endpoint\n");
1431 break;
1432 case 0xa:
1433 check_rootport = true;
1434 printf("Root Complex Event Collector\n");
1435 break;
1436 default:
1437 printf("unknown\n");
1438 break;
1439 }
1440 onoff("Slot implemented", reg, PCIE_XCAP_SI);
1441 printf(" Interrupt Message Number: %x\n",
1442 (unsigned int)((reg & PCIE_XCAP_IRQ) >> 27));
1443
1444 /* Device Capability Register */
1445 reg = regs[o2i(capoff + PCIE_DCAP)];
1446 printf(" Device Capabilities Register: 0x%08x\n", reg);
1447 printf(" Max Payload Size Supported: %u bytes max\n",
1448 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD));
1449 printf(" Phantom Functions Supported: ");
1450 switch ((reg & PCIE_DCAP_PHANTOM_FUNCS) >> 3) {
1451 case 0x0:
1452 printf("not available\n");
1453 break;
1454 case 0x1:
1455 printf("MSB\n");
1456 break;
1457 case 0x2:
1458 printf("two MSB\n");
1459 break;
1460 case 0x3:
1461 printf("All three bits\n");
1462 break;
1463 }
1464 printf(" Extended Tag Field Supported: %dbit\n",
1465 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8);
1466 printf(" Endpoint L0 Acceptable Latency: ");
1467 pci_print_pcie_L0s_latency((reg & PCIE_DCAP_L0S_LATENCY) >> 6);
1468 printf(" Endpoint L1 Acceptable Latency: ");
1469 pci_print_pcie_L1_latency((reg & PCIE_DCAP_L1_LATENCY) >> 9);
1470 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON);
1471 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND);
1472 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND);
1473 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT);
1474 printf(" Captured Slot Power Limit Value: %d\n",
1475 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_VAL) >> 18);
1476 printf(" Captured Slot Power Limit Scale: %d\n",
1477 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_SCALE) >> 26);
1478 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR);
1479
1480 /* Device Control Register */
1481 reg = regs[o2i(capoff + PCIE_DCSR)];
1482 printf(" Device Control Register: 0x%04x\n", reg & 0xffff);
1483 onoff("Correctable Error Reporting Enable", reg,
1484 PCIE_DCSR_ENA_COR_ERR);
1485 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER);
1486 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER);
1487 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR);
1488 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD);
1489 printf(" Max Payload Size: %d byte\n",
1490 128 << (((unsigned int)(reg & PCIE_DCSR_MAX_PAYLOAD) >> 5)));
1491 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD);
1492 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS);
1493 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM);
1494 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP);
1495 printf(" Max Read Request Size: %d byte\n",
1496 128 << ((unsigned int)(reg & PCIE_DCSR_MAX_READ_REQ) >> 12));
1497
1498 /* Device Status Register */
1499 reg = regs[o2i(capoff + PCIE_DCSR)];
1500 printf(" Device Status Register: 0x%04x\n", reg >> 16);
1501 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED);
1502 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED);
1503 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED);
1504 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD);
1505 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR);
1506 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND);
1507
1508 if (check_link) {
1509 /* Link Capability Register */
1510 reg = regs[o2i(capoff + PCIE_LCAP)];
1511 printf(" Link Capabilities Register: 0x%08x\n", reg);
1512 printf(" Maximum Link Speed: ");
1513 val = reg & PCIE_LCAP_MAX_SPEED;
1514 if (val < 1 || val > 3) {
1515 printf("unknown %u value\n", val);
1516 } else {
1517 printf("%sGT/s\n", linkspeeds[val - 1]);
1518 }
1519 printf(" Maximum Link Width: x%u lanes\n",
1520 (unsigned int)(reg & PCIE_LCAP_MAX_WIDTH) >> 4);
1521 printf(" Active State PM Support: ");
1522 val = (reg & PCIE_LCAP_ASPM) >> 10;
1523 switch (val) {
1524 case 0x1:
1525 printf("L0s Entry supported\n");
1526 break;
1527 case 0x3:
1528 printf("L0s and L1 supported\n");
1529 break;
1530 default:
1531 printf("Reserved value\n");
1532 break;
1533 }
1534 printf(" L0 Exit Latency: ");
1535 pci_print_pcie_L0s_latency((reg & PCIE_LCAP_L0S_EXIT) >> 12);
1536 printf(" L1 Exit Latency: ");
1537 pci_print_pcie_L1_latency((reg & PCIE_LCAP_L1_EXIT) >> 15);
1538 printf(" Port Number: %u\n", reg >> 24);
1539 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM);
1540 onoff("Surprise Down Error Report", reg,
1541 PCIE_LCAP_SURPRISE_DOWN);
1542 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE);
1543 onoff("Link BW Notification Capable", reg,
1544 PCIE_LCAP_LINK_BW_NOTIFY);
1545 onoff("ASPM Optionally Compliance", reg,
1546 PCIE_LCAP_ASPM_COMPLIANCE);
1547
1548 /* Link Control Register */
1549 reg = regs[o2i(capoff + PCIE_LCSR)];
1550 printf(" Link Control Register: 0x%04x\n", reg & 0xffff);
1551 printf(" Active State PM Control: ");
1552 val = reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S);
1553 switch (val) {
1554 case 0:
1555 printf("disabled\n");
1556 break;
1557 case 1:
1558 printf("L0s Entry Enabled\n");
1559 break;
1560 case 2:
1561 printf("L1 Entry Enabled\n");
1562 break;
1563 case 3:
1564 printf("L0s and L1 Entry Enabled\n");
1565 break;
1566 }
1567 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB,
1568 "128bytes", "64bytes");
1569 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS);
1570 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN);
1571 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG);
1572 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC);
1573 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM);
1574 onoff("Hardware Autonomous Width Disable", reg,
1575 PCIE_LCSR_HAWD);
1576 onoff("Link Bandwidth Management Interrupt Enable", reg,
1577 PCIE_LCSR_LBMIE);
1578 onoff("Link Autonomous Bandwidth Interrupt Enable", reg,
1579 PCIE_LCSR_LABIE);
1580
1581 /* Link Status Register */
1582 reg = regs[o2i(capoff + PCIE_LCSR)];
1583 printf(" Link Status Register: 0x%04x\n", reg >> 16);
1584 printf(" Negotiated Link Speed: ");
1585 if (((reg >> 16) & 0x000f) < 1 ||
1586 ((reg >> 16) & 0x000f) > 3) {
1587 printf("unknown %u value\n",
1588 (unsigned int)(reg & PCIE_LCSR_LINKSPEED) >> 16);
1589 } else {
1590 printf("%sGT/s\n",
1591 linkspeeds[((reg & PCIE_LCSR_LINKSPEED) >> 16)-1]);
1592 }
1593 printf(" Negotiated Link Width: x%u lanes\n",
1594 (reg >> 20) & 0x003f);
1595 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR);
1596 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN);
1597 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG);
1598 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE);
1599 onoff("Link Bandwidth Management Status", reg,
1600 PCIE_LCSR_LINK_BW_MGMT);
1601 onoff("Link Autonomous Bandwidth Status", reg,
1602 PCIE_LCSR_LINK_AUTO_BW);
1603 }
1604
1605 if (check_slot == true) {
1606 /* Slot Capability Register */
1607 reg = regs[o2i(capoff + PCIE_SLCAP)];
1608 printf(" Slot Capability Register: %08x\n", reg);
1609 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP);
1610 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP);
1611 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP);
1612 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP);
1613 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP);
1614 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS);
1615 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC);
1616 printf(" Slot Power Limit Value: %d\n",
1617 (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7);
1618 printf(" Slot Power Limit Scale: %d\n",
1619 (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15);
1620 onoff("Electromechanical Interlock Present", reg,
1621 PCIE_SLCAP_EIP);
1622 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS);
1623 printf(" Physical Slot Number: %d\n",
1624 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19);
1625
1626 /* Slot Control Register */
1627 reg = regs[o2i(capoff + PCIE_SLCSR)];
1628 printf(" Slot Control Register: %04x\n", reg & 0xffff);
1629 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE);
1630 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE);
1631 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE);
1632 onoff("Presense Detect Changed Enabled", reg, PCIE_SLCSR_PDE);
1633 onoff("Command Completed Interrupt Enabled", reg,
1634 PCIE_SLCSR_CCE);
1635 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE);
1636 printf(" Attention Indicator Control: ");
1637 switch ((reg & PCIE_SLCSR_AIC) >> 6) {
1638 case 0x0:
1639 printf("reserved\n");
1640 break;
1641 case 0x1:
1642 printf("on\n");
1643 break;
1644 case 0x2:
1645 printf("blink\n");
1646 break;
1647 case 0x3:
1648 printf("off\n");
1649 break;
1650 }
1651 printf(" Power Indicator Control: ");
1652 switch ((reg & PCIE_SLCSR_PIC) >> 8) {
1653 case 0x0:
1654 printf("reserved\n");
1655 break;
1656 case 0x1:
1657 printf("on\n");
1658 break;
1659 case 0x2:
1660 printf("blink\n");
1661 break;
1662 case 0x3:
1663 printf("off\n");
1664 break;
1665 }
1666 onoff("Power Controller Control", reg, PCIE_SLCSR_PCC);
1667 onoff("Electromechanical Interlock Control",
1668 reg, PCIE_SLCSR_EIC);
1669 onoff("Data Link Layer State Changed Enable", reg,
1670 PCIE_SLCSR_DLLSCE);
1671
1672 /* Slot Status Register */
1673 printf(" Slot Status Register: %04x\n", reg >> 16);
1674 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP);
1675 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD);
1676 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC);
1677 onoff("Presense Detect Changed", reg, PCIE_SLCSR_PDC);
1678 onoff("Command Completed", reg, PCIE_SLCSR_CC);
1679 onoff("MRL Open", reg, PCIE_SLCSR_MS);
1680 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS);
1681 onoff("Electromechanical Interlock engaged", reg,
1682 PCIE_SLCSR_EIS);
1683 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS);
1684 }
1685
1686 if (check_rootport == true) {
1687 /* Root Control Register */
1688 reg = regs[o2i(capoff + PCIE_RCR)];
1689 printf(" Root Control Register: %04x\n", reg & 0xffff);
1690 onoff("SERR on Correctable Error Enable", reg,
1691 PCIE_RCR_SERR_CER);
1692 onoff("SERR on Non-Fatal Error Enable", reg,
1693 PCIE_RCR_SERR_NFER);
1694 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER);
1695 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE);
1696 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE);
1697
1698 /* Root Capability Register */
1699 printf(" Root Capability Register: %04x\n",
1700 reg >> 16);
1701 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV);
1702
1703 /* Root Status Register */
1704 reg = regs[o2i(capoff + PCIE_RSR)];
1705 printf(" Root Status Register: %08x\n", reg);
1706 printf(" PME Requester ID: %04x\n",
1707 (unsigned int)(reg & PCIE_RSR_PME_REQESTER));
1708 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT);
1709 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND);
1710 }
1711
1712 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */
1713 if (pciever < 2)
1714 return;
1715
1716 /* Device Capabilities 2 */
1717 reg = regs[o2i(capoff + PCIE_DCAP2)];
1718 printf(" Device Capabilities 2: 0x%08x\n", reg);
1719 printf(" Completion Timeout Ranges Supported: %u \n",
1720 (unsigned int)(reg & PCIE_DCAP2_COMPT_RANGE));
1721 onoff("Completion Timeout Disable Supported", reg,
1722 PCIE_DCAP2_COMPT_DIS);
1723 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD);
1724 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT);
1725 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM);
1726 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM);
1727 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS);
1728 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS);
1729 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC);
1730 printf(" TPH Completer Supported: %u\n",
1731 (unsigned int)(reg & PCIE_DCAP2_TPH_COMP) >> 12);
1732 printf(" OBFF Supported: ");
1733 switch ((reg & PCIE_DCAP2_OBFF) >> 18) {
1734 case 0x0:
1735 printf("Not supported\n");
1736 break;
1737 case 0x1:
1738 printf("Message only\n");
1739 break;
1740 case 0x2:
1741 printf("WAKE# only\n");
1742 break;
1743 case 0x3:
1744 printf("Both\n");
1745 break;
1746 }
1747 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD);
1748 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF);
1749 printf(" Max End-End TLP Prefixes: %u\n",
1750 (unsigned int)(reg & PCIE_DCAP2_MAX_EETLP) >> 22);
1751
1752 /* Device Control 2 */
1753 reg = regs[o2i(capoff + PCIE_DCSR2)];
1754 printf(" Device Control 2: 0x%04x\n", reg & 0xffff);
1755 printf(" Completion Timeout Value: ");
1756 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL);
1757 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS);
1758 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD);
1759 onoff("AtomicOp Rquester Enabled", reg, PCIE_DCSR2_ATOM_REQ);
1760 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK);
1761 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ);
1762 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP);
1763 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC);
1764 printf(" OBFF: ");
1765 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) {
1766 case 0x0:
1767 printf("Disabled\n");
1768 break;
1769 case 0x1:
1770 printf("Enabled with Message Signaling Variation A\n");
1771 break;
1772 case 0x2:
1773 printf("Enabled with Message Signaling Variation B\n");
1774 break;
1775 case 0x3:
1776 printf("Enabled using WAKE# signaling\n");
1777 break;
1778 }
1779 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP);
1780
1781 if (check_link) {
1782 /* Link Capability 2 */
1783 reg = regs[o2i(capoff + PCIE_LCAP2)];
1784 printf(" Link Capabilities 2: 0x%08x\n", reg);
1785 val = (reg & PCIE_LCAP2_SUP_LNKSV) >> 1;
1786 printf(" Supported Link Speed Vector:");
1787 for (i = 0; i <= 2; i++) {
1788 if (((val >> i) & 0x01) != 0)
1789 printf(" %sGT/s", linkspeeds[i]);
1790 }
1791 printf("\n");
1792 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK);
1793
1794 /* Link Control 2 */
1795 reg = regs[o2i(capoff + PCIE_LCSR2)];
1796 printf(" Link Control 2: 0x%04x\n", reg & 0xffff);
1797 printf(" Target Link Speed: ");
1798 val = reg & PCIE_LCSR2_TGT_LSPEED;
1799 if (val < 1 || val > 3)
1800 printf("unknown %u value\n", val);
1801 else
1802 printf("%sGT/s\n", linkspeeds[val - 1]);
1803 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL);
1804 onoff("HW Autonomous Speed Disabled", reg,
1805 PCIE_LCSR2_HW_AS_DIS);
1806 onoff("Selectable De-emphasis", reg, PCIE_LCSR2_SEL_DEEMP);
1807 printf(" Transmit Margin: %u\n",
1808 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7);
1809 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP);
1810 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS);
1811 printf(" Compliance Present/De-emphasis: %u\n",
1812 (unsigned int)(reg & PCIE_LCSR2_COMP_DEEMP) >> 12);
1813
1814 /* Link Status 2 */
1815 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff);
1816 onoff("Current De-emphasis Level", reg, PCIE_LCSR2_DEEMP_LVL);
1817 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL);
1818 onoff("Equalization Phase 1 Successful", reg,
1819 PCIE_LCSR2_EQP1_SUC);
1820 onoff("Equalization Phase 2 Successful", reg,
1821 PCIE_LCSR2_EQP2_SUC);
1822 onoff("Equalization Phase 3 Successful", reg,
1823 PCIE_LCSR2_EQP3_SUC);
1824 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ);
1825 }
1826
1827 /* Slot Capability 2 */
1828 /* Slot Control 2 */
1829 /* Slot Status 2 */
1830 }
1831
1832 static void
1833 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff)
1834 {
1835 pcireg_t reg;
1836
1837 printf("\n MSI-X Capability Register\n");
1838
1839 reg = regs[o2i(capoff + PCI_MSIX_CTL)];
1840 printf(" Message Control register: 0x%04x\n",
1841 (reg >> 16) & 0xff);
1842 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg));
1843 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK);
1844 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE);
1845 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)];
1846 printf(" Table offset register: 0x%08x\n", reg);
1847 printf(" Table offset: %08x\n", reg & PCI_MSIX_TBLOFFSET_MASK);
1848 printf(" BIR: 0x%x\n", reg & PCI_MSIX_TBLBIR_MASK);
1849 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)];
1850 printf(" Pending bit array register: 0x%08x\n", reg);
1851 printf(" Pending bit array offset: %08x\n",
1852 reg & PCI_MSIX_PBAOFFSET_MASK);
1853 printf(" BIR: 0x%x\n", reg & PCI_MSIX_PBABIR_MASK);
1854 }
1855
1856 /* XXX pci_conf_print_sata_cap */
1857 static void
1858 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff)
1859 {
1860 pcireg_t reg;
1861
1862 printf("\n Advanced Features Capability Register\n");
1863
1864 reg = regs[o2i(capoff + PCI_AFCAPR)];
1865 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff);
1866 onoff("Transaction Pending", reg, PCI_AF_TP_CAP);
1867 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP);
1868 reg = regs[o2i(capoff + PCI_AFCSR)];
1869 printf(" AF Control register: 0x%02x\n", reg & 0xff);
1870 /*
1871 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register
1872 * and it's always 0 on read
1873 */
1874 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff);
1875 onoff("Transaction Pending", reg, PCI_AFSR_TP);
1876 }
1877
1878 static struct {
1879 pcireg_t cap;
1880 const char *name;
1881 void (*printfunc)(const pcireg_t *, int);
1882 } pci_captab[] = {
1883 { PCI_CAP_RESERVED0, "reserved", NULL },
1884 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap },
1885 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap },
1886 { PCI_CAP_VPD, "VPD", NULL },
1887 { PCI_CAP_SLOTID, "SlotID", NULL },
1888 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap },
1889 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL },
1890 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap },
1891 { PCI_CAP_LDT, "HyperTransport", NULL },
1892 { PCI_CAP_VENDSPEC, "Vendor-specific",
1893 pci_conf_print_vendspec_cap },
1894 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap },
1895 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL },
1896 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL },
1897 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID",
1898 pci_conf_print_subsystem_cap },
1899 { PCI_CAP_AGP8, "AGP 8x", NULL },
1900 { PCI_CAP_SECURE, "Secure Device", NULL },
1901 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap },
1902 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap },
1903 { PCI_CAP_SATA, "SATA", NULL },
1904 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap }
1905 };
1906
1907 static int
1908 pci_conf_find_cap(const pcireg_t *regs, int capoff, unsigned int capid,
1909 int *offsetp)
1910 {
1911 pcireg_t rval;
1912 int off;
1913
1914 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]);
1915 off != 0;
1916 off = PCI_CAPLIST_NEXT(rval)) {
1917 rval = regs[o2i(off)];
1918 if (capid == PCI_CAPLIST_CAP(rval)) {
1919 if (offsetp != NULL)
1920 *offsetp = off;
1921 return 1;
1922 }
1923 }
1924 return 0;
1925 }
1926
1927 static void
1928 pci_conf_print_caplist(
1929 #ifdef _KERNEL
1930 pci_chipset_tag_t pc, pcitag_t tag,
1931 #endif
1932 const pcireg_t *regs, int capoff)
1933 {
1934 int off;
1935 pcireg_t foundcap;
1936 pcireg_t rval;
1937 bool foundtable[__arraycount(pci_captab)];
1938 unsigned int i;
1939
1940 /* Clear table */
1941 for (i = 0; i < __arraycount(pci_captab); i++)
1942 foundtable[i] = false;
1943
1944 /* Print capability register's offset and the type first */
1945 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]);
1946 off != 0;
1947 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) {
1948 rval = regs[o2i(off)];
1949 printf(" Capability register at 0x%02x\n", off);
1950
1951 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval));
1952 foundcap = PCI_CAPLIST_CAP(rval);
1953 if (foundcap < __arraycount(pci_captab)) {
1954 printf("%s)\n", pci_captab[foundcap].name);
1955 /* Mark as found */
1956 foundtable[foundcap] = true;
1957 } else
1958 printf("unknown)\n");
1959 }
1960
1961 /*
1962 * And then, print the detail of each capability registers
1963 * in capability value's order.
1964 */
1965 for (i = 0; i < __arraycount(pci_captab); i++) {
1966 if (foundtable[i] == false)
1967 continue;
1968
1969 /*
1970 * The type was found. Search capability list again and
1971 * print all capabilities that the capabiliy type is
1972 * the same. This is required because some capabilities
1973 * appear multiple times (e.g. HyperTransport capability).
1974 */
1975 if (pci_conf_find_cap(regs, capoff, i, &off)) {
1976 rval = regs[o2i(off)];
1977 if (pci_captab[i].printfunc != NULL)
1978 pci_captab[i].printfunc(regs, off);
1979 }
1980 }
1981 }
1982
1983 /* Extended Capability */
1984
1985 static void
1986 pci_conf_print_aer_cap_uc(pcireg_t reg)
1987 {
1988
1989 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED);
1990 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR);
1991 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR);
1992 onoff("Poisoned TLP", reg, PCI_AER_UC_POISONED_TLP);
1993 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR);
1994 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT);
1995 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT);
1996 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION);
1997 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW);
1998 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP);
1999 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR);
2000 onoff("Unsupported Request Error", reg,
2001 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR);
2002 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION);
2003 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR);
2004 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP);
2005 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED);
2006 onoff("TLP Prefix Blocked Error", reg,
2007 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR);
2008 }
2009
2010 static void
2011 pci_conf_print_aer_cap_cor(pcireg_t reg)
2012 {
2013
2014 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR);
2015 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP);
2016 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP);
2017 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER);
2018 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT);
2019 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR);
2020 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR);
2021 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW);
2022 }
2023
2024 static void
2025 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log)
2026 {
2027
2028 printf(" First Error Pointer: 0x%04x\n",
2029 (pcireg_t)__SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR));
2030 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE);
2031 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE);
2032 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE);
2033 onoff("ECRC Check Enab", reg, PCI_AER_ECRC_CHECK_ENABLE);
2034 onoff("Multiple Header Recording Capable", reg,
2035 PCI_AER_MULT_HDR_CAPABLE);
2036 onoff("Multiple Header Recording Enable", reg, PCI_AER_MULT_HDR_ENABLE);
2037
2038 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */
2039 if (!tlp_prefix_log)
2040 return;
2041 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT);
2042 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false;
2043 }
2044
2045 static void
2046 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg)
2047 {
2048
2049 onoff("Correctable Error Reporting Enable", reg,
2050 PCI_AER_ROOTERR_COR_ENABLE);
2051 onoff("Non-Fatal Error Reporting Enable", reg,
2052 PCI_AER_ROOTERR_NF_ENABLE);
2053 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE);
2054 }
2055
2056 static void
2057 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg)
2058 {
2059
2060 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR);
2061 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR);
2062 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR);
2063 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg,
2064 PCI_AER_ROOTERR_MULTI_UC_ERR);
2065 onoff("First Uncorrectable Fatal", reg, PCI_AER_ROOTERR_FIRST_UC_FATAL);
2066 onoff("Non-Fatal Error Messages Received", reg, PCI_AER_ROOTERR_NF_ERR);
2067 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR);
2068 printf(" Advanced Error Interrupt Message Number: 0x%u\n",
2069 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE));
2070 }
2071
2072 static void
2073 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg)
2074 {
2075
2076 printf(" Correctable Source ID: 0x%04x\n",
2077 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR));
2078 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n",
2079 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC));
2080 }
2081
2082 static void
2083 pci_conf_print_aer_cap(const pcireg_t *regs, int capoff, int extcapoff)
2084 {
2085 pcireg_t reg;
2086 int pcie_capoff;
2087 int pcie_devtype = -1;
2088 bool tlp_prefix_log = false;
2089
2090 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
2091 reg = regs[o2i(pcie_capoff)];
2092 pcie_devtype = reg & PCIE_XCAP_TYPE_MASK;
2093 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */
2094 if (__SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) {
2095 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)];
2096 /* End-End TLP Prefix Supported */
2097 if (reg & PCIE_DCAP2_EETLP_PREF) {
2098 tlp_prefix_log = true;
2099 }
2100 }
2101 }
2102
2103 printf("\n Advanced Error Reporting Register\n");
2104
2105 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)];
2106 printf(" Uncorrectable Error Status register: 0x%08x\n", reg);
2107 pci_conf_print_aer_cap_uc(reg);
2108 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)];
2109 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg);
2110 pci_conf_print_aer_cap_uc(reg);
2111 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)];
2112 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg);
2113 pci_conf_print_aer_cap_uc(reg);
2114
2115 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)];
2116 printf(" Correctable Error Status register: 0x%08x\n", reg);
2117 pci_conf_print_aer_cap_cor(reg);
2118 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)];
2119 printf(" Correctable Error Mask register: 0x%08x\n", reg);
2120 pci_conf_print_aer_cap_cor(reg);
2121
2122 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)];
2123 printf(" Advanced Error Capabilities and Control register: 0x%08x\n",
2124 reg);
2125 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log);
2126 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)];
2127 printf(" Header Log register:\n");
2128 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG,
2129 extcapoff + PCI_AER_ROOTERR_CMD);
2130
2131 switch (pcie_devtype) {
2132 case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */
2133 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */
2134 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)];
2135 printf(" Root Error Command register: 0x%08x\n", reg);
2136 pci_conf_print_aer_cap_rooterr_cmd(reg);
2137 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)];
2138 printf(" Root Error Status register: 0x%08x\n", reg);
2139 pci_conf_print_aer_cap_rooterr_status(reg);
2140
2141 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)];
2142 printf(" Error Source Identification: 0x%04x\n", reg);
2143 pci_conf_print_aer_cap_errsrc_id(reg);
2144 break;
2145 }
2146
2147 if (tlp_prefix_log) {
2148 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)];
2149 printf(" TLP Prefix Log register: 0x%08x\n", reg);
2150 }
2151 }
2152
2153 static void
2154 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name,
2155 pcireg_t parbsel, int parbsize)
2156 {
2157 pcireg_t reg;
2158 int num = 16 << parbsel;
2159 int num_per_reg = sizeof(pcireg_t) / parbsize;
2160 int i, j;
2161
2162 /* First, dump the table */
2163 for (i = 0; i < num; i += num_per_reg) {
2164 reg = regs[o2i(off + i / num_per_reg)];
2165 printf(" %s Arbitration Table: 0x%08x\n", name, reg);
2166 }
2167 /* And then, decode each entry */
2168 for (i = 0; i < num; i += num_per_reg) {
2169 reg = regs[o2i(off + i / num_per_reg)];
2170 for (j = 0; j < num_per_reg; j++)
2171 printf(" Phase[%d]: %d\n", j, reg);
2172 }
2173 }
2174
2175 static void
2176 pci_conf_print_vc_cap(const pcireg_t *regs, int capoff, int extcapoff)
2177 {
2178 pcireg_t reg, n;
2179 int parbtab, parbsize;
2180 pcireg_t parbsel;
2181 int varbtab, varbsize;
2182 pcireg_t varbsel;
2183 int i, count;
2184
2185 printf("\n Virtual Channel Register\n");
2186 reg = regs[o2i(extcapoff + PCI_VC_CAP1)];
2187 printf(" Port VC Capability register 1: 0x%08x\n", reg);
2188 count = __SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT);
2189 printf(" Extended VC Count: %d\n", count);
2190 n = __SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT);
2191 printf(" Low Priority Extended VC Count: %u\n", n);
2192 n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK);
2193 printf(" Reference Clock: %s\n",
2194 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100" : "unknown");
2195 parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE);
2196 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize);
2197
2198 reg = regs[o2i(extcapoff + PCI_VC_CAP2)];
2199 printf(" Port VC Capability register 2: 0x%08x\n", reg);
2200 onoff("Hardware fixed arbitration scheme",
2201 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME);
2202 onoff("WRR arbitration with 32 phases",
2203 reg, PCI_VC_CAP2_ARB_CAP_WRR_32);
2204 onoff("WRR arbitration with 64 phases",
2205 reg, PCI_VC_CAP2_ARB_CAP_WRR_64);
2206 onoff("WRR arbitration with 128 phases",
2207 reg, PCI_VC_CAP2_ARB_CAP_WRR_128);
2208 varbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET);
2209 printf(" VC Arbitration Table Offset: 0x%x\n", varbtab);
2210
2211 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff;
2212 printf(" Port VC Control register: 0x%04x\n", reg);
2213 varbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT);
2214 printf(" VC Arbitration Select: 0x%x\n", varbsel);
2215
2216 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16;
2217 printf(" Port VC Status register: 0x%04x\n", reg);
2218 onoff("VC Arbitration Table Status",
2219 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE);
2220
2221 for (i = 0; i < count + 1; i++) {
2222 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))];
2223 printf(" VC number %d\n", i);
2224 printf(" VC Resource Capability Register: 0x%08x\n", reg);
2225 onoff(" Non-configurable Hardware fixed arbitration scheme",
2226 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME);
2227 onoff(" WRR arbitration with 32 phases",
2228 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32);
2229 onoff(" WRR arbitration with 64 phases",
2230 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64);
2231 onoff(" WRR arbitration with 128 phases",
2232 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128);
2233 onoff(" Time-based WRR arbitration with 128 phases",
2234 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128);
2235 onoff(" WRR arbitration with 256 phases",
2236 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256);
2237 onoff(" Advanced Packet Switching",
2238 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH);
2239 onoff(" Reject Snoop Transaction",
2240 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS);
2241 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1;
2242 printf(" Maximum Time Slots: %d\n", n);
2243 parbtab = reg >> PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S;
2244 printf(" Port Arbitration Table offset: 0x%02x\n",
2245 parbtab);
2246
2247 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))];
2248 printf(" VC Resource Control Register: 0x%08x\n", reg);
2249 printf(" TC/VC Map: %02x\n",
2250 (pcireg_t)__SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP));
2251 /*
2252 * The load Port Arbitration Table bit is used to update
2253 * the Port Arbitration logic and it's always 0 on read, so
2254 * we don't print it.
2255 */
2256 parbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT);
2257 printf(" Port Arbitration Select: %x\n", parbsel);
2258 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID);
2259 printf(" VC ID %d\n", n);
2260 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE);
2261
2262 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16;
2263 printf(" VC Resource Status Register: 0x%08x\n", reg);
2264 onoff(" Port Arbitration Table Status",
2265 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE);
2266 onoff(" VC Negotiation Pending",
2267 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING);
2268
2269 if ((parbtab != 0) && (parbsel != 0))
2270 pci_conf_print_vc_cap_arbtab(regs, extcapoff + parbtab,
2271 "Port", parbsel, parbsize);
2272 }
2273
2274 varbsize = 8;
2275 if ((varbtab != 0) && (varbsel != 0))
2276 pci_conf_print_vc_cap_arbtab(regs, extcapoff + varbtab,
2277 " VC", varbsel, varbsize);
2278 }
2279
2280 static const char *
2281 pci_conf_print_pwrbdgt_base_power(uint8_t reg)
2282 {
2283
2284 switch (reg) {
2285 case 0xf0:
2286 return "250W";
2287 case 0xf1:
2288 return "275W";
2289 case 0xf2:
2290 return "300W";
2291 default:
2292 return "Unknown";
2293 }
2294 }
2295
2296 static const char *
2297 pci_conf_print_pwrbdgt_data_scale(uint8_t reg)
2298 {
2299
2300 switch (reg) {
2301 case 0x00:
2302 return "1.0x";
2303 case 0x01:
2304 return "0.1x";
2305 case 0x02:
2306 return "0.01x";
2307 case 0x03:
2308 return "0.001x";
2309 default:
2310 return "wrong value!";
2311 }
2312 }
2313
2314 static const char *
2315 pci_conf_print_pwrbdgt_type(uint8_t reg)
2316 {
2317
2318 switch (reg) {
2319 case 0x00:
2320 return "PME Aux";
2321 case 0x01:
2322 return "Auxilary";
2323 case 0x02:
2324 return "Idle";
2325 case 0x03:
2326 return "Sustained";
2327 case 0x07:
2328 return "Maximun";
2329 default:
2330 return "Unknown";
2331 }
2332 }
2333
2334 static const char *
2335 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg)
2336 {
2337
2338 switch (reg) {
2339 case 0x00:
2340 return "Power(12V)";
2341 case 0x01:
2342 return "Power(3.3V)";
2343 case 0x02:
2344 return "Power(1.5V or 1.8V)";
2345 case 0x07:
2346 return "Thermal";
2347 default:
2348 return "Unknown";
2349 }
2350 }
2351
2352 static void
2353 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int capoff, int extcapoff)
2354 {
2355 pcireg_t reg;
2356
2357 printf("\n Power Budget Register\n");
2358
2359 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)];
2360 printf(" Data Select register: 0x%08x\n", reg);
2361
2362 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)];
2363 printf(" Data register: 0x%08x\n", reg);
2364 printf(" Base Power: %s\n",
2365 pci_conf_print_pwrbdgt_base_power((uint8_t)reg));
2366 printf(" Data Scale: %s\n",
2367 pci_conf_print_pwrbdgt_data_scale(
2368 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE))));
2369 printf(" PM Sub State: 0x%hhx\n",
2370 (uint8_t)__SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT));
2371 printf(" PM State: D%u\n",
2372 (unsigned int)__SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT));
2373 printf(" Type: %s\n",
2374 pci_conf_print_pwrbdgt_type(
2375 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_TYPE))));
2376 printf(" Power Rail: %s\n",
2377 pci_conf_print_pwrbdgt_pwrrail(
2378 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL))));
2379
2380 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)];
2381 printf(" Power Budget Capability register: 0x%08x\n", reg);
2382 onoff("System Allocated",
2383 reg, PCI_PWRBDGT_CAP_SYSALLOC);
2384 }
2385
2386 static const char *
2387 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type)
2388 {
2389
2390 switch (type) {
2391 case 0x00:
2392 return "Configuration Space Element";
2393 case 0x01:
2394 return "System Egress Port or internal sink (memory)";
2395 case 0x02:
2396 return "Internal Root Complex Link";
2397 default:
2398 return "Unknown";
2399 }
2400 }
2401
2402 static void
2403 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int capoff, int extcapoff)
2404 {
2405 pcireg_t reg;
2406 unsigned char nent, linktype;
2407 int i;
2408
2409 printf("\n Root Complex Link Declaration\n");
2410
2411 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)];
2412 printf(" Element Self Description Register: 0x%08x\n", reg);
2413 printf(" Element Type: %s\n",
2414 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg));
2415 nent = __SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT);
2416 printf(" Number of Link Entries: %hhu\n", nent);
2417 printf(" Component ID: %hhu\n",
2418 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID));
2419 printf(" Port Number: %hhu\n",
2420 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM));
2421 for (i = 0; i < nent; i++) {
2422 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))];
2423 printf(" Link Description Register: 0x%08x\n", reg);
2424 onoff("Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID);
2425 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE;
2426 onoff2("Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE,
2427 "Configuration Space", "Memory-Mapped Space");
2428 onoff("Associated RCRB Header", reg,
2429 PCI_RCLINK_DCL_LINKDESC_ARCRBH);
2430 printf(" Target Component ID: %hhu\n",
2431 (unsigned char)__SHIFTOUT(reg,
2432 PCI_RCLINK_DCL_LINKDESC_TCOMPID));
2433 printf(" Target Port Number: %hhu\n",
2434 (unsigned char)__SHIFTOUT(reg,
2435 PCI_RCLINK_DCL_LINKDESC_TPNUM));
2436
2437 if (linktype == 0) {
2438 /* Memory-Mapped Space */
2439 reg = regs[o2i(extcapoff
2440 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))];
2441 printf(" Link Address Low Register: 0x%08x\n", reg);
2442 reg = regs[o2i(extcapoff
2443 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))];
2444 printf(" Link Address High Register: 0x%08x\n",reg);
2445 } else {
2446 unsigned int nb;
2447 pcireg_t lo, hi;
2448
2449 /* Configuration Space */
2450 lo = regs[o2i(extcapoff
2451 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))];
2452 printf(" Configuration Space Low Register: 0x%08x"
2453 "\n", lo);
2454 hi = regs[o2i(extcapoff
2455 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))];
2456 printf(" Configuration Space High Register: 0x%08x"
2457 "\n", hi);
2458 nb = __SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N);
2459 printf(" N: %u\n", nb);
2460 printf(" Func: %hhu\n",
2461 (unsigned char)__SHIFTOUT(lo,
2462 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC));
2463 printf(" Dev: %hhu\n",
2464 (unsigned char)__SHIFTOUT(lo,
2465 PCI_RCLINK_DCL_LINKADDR_LT1_DEV));
2466 printf(" Bus: %hhu\n",
2467 (unsigned char)__SHIFTOUT(lo,
2468 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb)));
2469 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i);
2470 printf(" Configuration Space Base Address: 0x%016"
2471 PRIx64 "\n", ((uint64_t)hi << 32) + lo);
2472 }
2473 }
2474 }
2475
2476 /* XXX pci_conf_print_rclink_ctl_cap */
2477
2478 static void
2479 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int capoff, int extcapoff)
2480 {
2481 pcireg_t reg;
2482
2483 printf("\n Root Complex Event Collector Association\n");
2484
2485 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)];
2486 printf(" Association Bitmap for Root Complex Integrated Devices:"
2487 " 0x%08x\n", reg);
2488 }
2489
2490 /* XXX pci_conf_print_mfvc_cap */
2491 /* XXX pci_conf_print_vc2_cap */
2492 /* XXX pci_conf_print_rcrb_cap */
2493 /* XXX pci_conf_print_vendor_cap */
2494 /* XXX pci_conf_print_cac_cap */
2495
2496 static void
2497 pci_conf_print_acs_cap(const pcireg_t *regs, int capoff, int extcapoff)
2498 {
2499 pcireg_t reg, cap, ctl;
2500 unsigned int size, i;
2501
2502 printf("\n Access Control Services\n");
2503
2504 reg = regs[o2i(extcapoff + PCI_ACS_CAP)];
2505 cap = reg & 0xffff;
2506 ctl = reg >> 16;
2507 printf(" ACS Capability register: 0x%08x\n", cap);
2508 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V);
2509 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B);
2510 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R);
2511 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C);
2512 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U);
2513 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E);
2514 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T);
2515 size = __SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE);
2516 if (size == 0)
2517 size = 256;
2518 printf(" Egress Control Vector Size: %u\n", size);
2519 printf(" ACS Control register: 0x%08x\n", ctl);
2520 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V);
2521 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B);
2522 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R);
2523 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C);
2524 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U);
2525 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E);
2526 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T);
2527
2528 /*
2529 * If the P2P Egress Control Capability bit is 0, ignore the Egress
2530 * Control vector.
2531 */
2532 if ((cap & PCI_ACS_CAP_E) == 0)
2533 return;
2534 for (i = 0; i < size; i += 32)
2535 printf(" Egress Control Vector [%u..%u]: %x\n", i + 31,
2536 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]);
2537 }
2538
2539 static void
2540 pci_conf_print_ari_cap(const pcireg_t *regs, int capoff, int extcapoff)
2541 {
2542 pcireg_t reg, cap, ctl;
2543
2544 printf("\n Alternative Routing-ID Interpretation Register\n");
2545
2546 reg = regs[o2i(extcapoff + PCI_ARI_CAP)];
2547 cap = reg & 0xffff;
2548 ctl = reg >> 16;
2549 printf(" Capability register: 0x%08x\n", cap);
2550 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M);
2551 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A);
2552 printf(" Next Function Number: %u\n",
2553 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CAP_NXTFN));
2554 printf(" Control register: 0x%08x\n", ctl);
2555 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M);
2556 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A);
2557 printf(" Function Group: %u\n",
2558 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP));
2559 }
2560
2561 static void
2562 pci_conf_print_ats_cap(const pcireg_t *regs, int capoff, int extcapoff)
2563 {
2564 pcireg_t reg, cap, ctl;
2565 unsigned int num;
2566
2567 printf("\n Address Translation Services\n");
2568
2569 reg = regs[o2i(extcapoff + PCI_ARI_CAP)];
2570 cap = reg & 0xffff;
2571 ctl = reg >> 16;
2572 printf(" Capability register: 0x%04x\n", cap);
2573 num = __SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH);
2574 if (num == 0)
2575 num = 32;
2576 printf(" Invalidate Queue Depth: %u\n", num);
2577 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ);
2578
2579 printf(" Control register: 0x%04x\n", ctl);
2580 printf(" Smallest Translation Unit: %u\n",
2581 (unsigned int)__SHIFTOUT(reg, PCI_ATS_CTL_STU));
2582 onoff("Enable", reg, PCI_ATS_CTL_EN);
2583 }
2584
2585 static void
2586 pci_conf_print_sernum_cap(const pcireg_t *regs, int capoff, int extcapoff)
2587 {
2588 pcireg_t lo, hi;
2589
2590 printf("\n Device Serial Number Register\n");
2591
2592 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)];
2593 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)];
2594 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
2595 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff,
2596 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff);
2597 }
2598
2599 static void
2600 pci_conf_print_sriov_cap(const pcireg_t *regs, int capoff, int extcapoff)
2601 {
2602 char buf[sizeof("99999 MB")];
2603 pcireg_t reg;
2604 pcireg_t total_vfs;
2605 int i;
2606 bool first;
2607
2608 printf("\n Single Root IO Virtualization Register\n");
2609
2610 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)];
2611 printf(" Capabilities register: 0x%08x\n", reg);
2612 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION);
2613 onoff("ARI Capable Hierarchy Preserved", reg,
2614 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED);
2615 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) {
2616 printf(" VF Migration Interrupt Message Number: 0x%u\n",
2617 (pcireg_t)__SHIFTOUT(reg,
2618 PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N));
2619 }
2620
2621 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff;
2622 printf(" Control register: 0x%04x\n", reg);
2623 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE);
2624 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT);
2625 onoff("VF Migration Interrupt Enable", reg,
2626 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE);
2627 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE);
2628 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER);
2629
2630 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16;
2631 printf(" Status register: 0x%04x\n", reg);
2632 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION);
2633
2634 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff;
2635 printf(" InitialVFs register: 0x%04x\n", reg);
2636 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16;
2637 printf(" TotalVFs register: 0x%04x\n", reg);
2638 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff;
2639 printf(" NumVFs register: 0x%04x\n", reg);
2640
2641 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16;
2642 printf(" Function Dependency Link register: 0x%04x\n", reg);
2643
2644 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff;
2645 printf(" First VF Offset register: 0x%04x\n", reg);
2646 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16;
2647 printf(" VF Stride register: 0x%04x\n", reg);
2648
2649 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)];
2650 printf(" Supported Page Sizes register: 0x%08x\n", reg);
2651 printf(" Supported Page Size:");
2652 for (i = 0, first = true; i < 32; i++) {
2653 if (reg & __BIT(i)) {
2654 #ifdef _KERNEL
2655 format_bytes(buf, sizeof(buf), 1LL << (i + 12));
2656 #else
2657 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B",
2658 HN_AUTOSCALE, 0);
2659 #endif
2660 printf("%s %s", first ? "" : ",", buf);
2661 first = false;
2662 }
2663 }
2664 printf("\n");
2665
2666 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)];
2667 printf(" System Page Sizes register: 0x%08x\n", reg);
2668 printf(" Page Size: ");
2669 if (reg != 0) {
2670 #ifdef _KERNEL
2671 format_bytes(buf, sizeof(buf), 1LL << (ffs(reg) + 12));
2672 #else
2673 humanize_number(buf, sizeof(buf), 1LL << (ffs(reg) + 12), "B",
2674 HN_AUTOSCALE, 0);
2675 #endif
2676 printf("%s", buf);
2677 } else {
2678 printf("unknown");
2679 }
2680 printf("\n");
2681
2682 for (i = 0; i < 6; i++) {
2683 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))];
2684 printf(" VF BAR%d register: 0x%08x\n", i, reg);
2685 }
2686
2687 if (total_vfs > 0) {
2688 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)];
2689 printf(" VF Migration State Array Offset register: 0x%08x\n",
2690 reg);
2691 printf(" VF Migration State Offset: 0x%08x\n",
2692 (pcireg_t)__SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET));
2693 i = __SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR);
2694 printf(" VF Migration State BIR: ");
2695 if (i >= 0 && i <= 5) {
2696 printf("BAR%d", i);
2697 } else {
2698 printf("unknown BAR (%d)", i);
2699 }
2700 printf("\n");
2701 }
2702 }
2703
2704 /* XXX pci_conf_print_mriov_cap */
2705 /* XXX pci_conf_print_multicast_cap */
2706
2707 static void
2708 pci_conf_print_page_req_cap(const pcireg_t *regs, int capoff, int extcapoff)
2709 {
2710 pcireg_t reg, ctl, sta;
2711
2712 printf("\n Page Request\n");
2713
2714 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)];
2715 ctl = reg & 0xffff;
2716 sta = reg >> 16;
2717 printf(" Control Register: 0x%04x\n", ctl);
2718 onoff("Enalbe", reg, PCI_PAGE_REQ_CTL_E);
2719 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R);
2720
2721 printf(" Status Register: 0x%04x\n", sta);
2722 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF);
2723 onoff("Unexpected Page Request Group Index", reg,
2724 PCI_PAGE_REQ_STA_UPRGI);
2725 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S);
2726
2727 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)];
2728 printf(" Outstanding Page Request Capacity: %u\n", reg);
2729 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)];
2730 printf(" Outstanding Page Request Allocation: %u\n", reg);
2731 }
2732
2733 /* XXX pci_conf_print_amd_cap */
2734 /* XXX pci_conf_print_resize_bar_cap */
2735 /* XXX pci_conf_print_dpa_cap */
2736
2737 static const char *
2738 pci_conf_print_tph_req_cap_sttabloc(unsigned char val)
2739 {
2740
2741 switch (val) {
2742 case 0x0:
2743 return "Not Present";
2744 case 0x1:
2745 return "in the TPH Requester Capability Structure";
2746 case 0x2:
2747 return "in the MSI-X Table";
2748 default:
2749 return "Unknown";
2750 }
2751 }
2752
2753 static void
2754 pci_conf_print_tph_req_cap(const pcireg_t *regs, int capoff, int extcapoff)
2755 {
2756 pcireg_t reg;
2757 int size, i, j;
2758
2759 printf("\n TPH Requester Extended Capability\n");
2760
2761 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)];
2762 printf(" TPH Requester Capabililty register: 0x%08x\n", reg);
2763 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST);
2764 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC);
2765 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC);
2766 onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ);
2767 printf(" ST Table Location: %s\n",
2768 pci_conf_print_tph_req_cap_sttabloc(
2769 (unsigned char)__SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC)));
2770 size = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1;
2771 printf(" ST Table Size: %d\n", size);
2772 for (i = 0; i < size ; i += 2) {
2773 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)];
2774 for (j = 0; j < 2 ; j++) {
2775 uint32_t entry = reg;
2776
2777 if (j != 0)
2778 entry >>= 16;
2779 entry &= 0xffff;
2780 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n",
2781 i + j, entry);
2782 }
2783 }
2784 }
2785
2786 static void
2787 pci_conf_print_ltr_cap(const pcireg_t *regs, int capoff, int extcapoff)
2788 {
2789 pcireg_t reg;
2790
2791 printf("\n Latency Tolerance Reporting\n");
2792 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)] & 0xffff;
2793 printf(" Max Snoop Latency Register: 0x%04x\n", reg);
2794 printf(" Max Snoop LatencyValue: %u\n",
2795 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL));
2796 printf(" Max Snoop LatencyScale: %uns\n",
2797 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE)));
2798 reg = regs[o2i(extcapoff + PCI_LTR_MAXNOSNOOPLAT)] >> 16;
2799 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg);
2800 printf(" Max No-Snoop LatencyValue: %u\n",
2801 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL));
2802 printf(" Max No-Snoop LatencyScale: %uns\n",
2803 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE)));
2804 }
2805
2806 static void
2807 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int capoff, int extcapoff)
2808 {
2809 int pcie_capoff;
2810 pcireg_t reg;
2811 int i, maxlinkwidth;
2812
2813 printf("\n Secondary PCI Express Register\n");
2814
2815 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)];
2816 printf(" Link Control 3 register: 0x%08x\n", reg);
2817 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ);
2818 onoff("Link Equalization Request Interrupt Enable",
2819 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE);
2820
2821 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)];
2822 printf(" Lane Error Status register: 0x%08x\n", reg);
2823
2824 /* Get Max Link Width */
2825 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)){
2826 reg = regs[o2i(pcie_capoff + PCIE_LCAP)];
2827 maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH);
2828 } else {
2829 printf("error: falied to get PCIe capablity\n");
2830 return;
2831 }
2832 for (i = 0; i < maxlinkwidth; i++) {
2833 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))];
2834 if (i % 2 != 0)
2835 reg >>= 16;
2836 else
2837 reg &= 0xffff;
2838 printf(" Equalization Control Register (Link %d): %04x\n",
2839 i, reg);
2840 printf(" Downstream Port Transmit Preset: 0x%x\n",
2841 (pcireg_t)__SHIFTOUT(reg,
2842 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET));
2843 printf(" Downstream Port Receive Hint: 0x%x\n",
2844 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT));
2845 printf(" Upstream Port Transmit Preset: 0x%x\n",
2846 (pcireg_t)__SHIFTOUT(reg,
2847 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET));
2848 printf(" Upstream Port Receive Hint: 0x%x\n",
2849 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT));
2850 }
2851 }
2852
2853 /* XXX pci_conf_print_pmux_cap */
2854
2855 static void
2856 pci_conf_print_pasid_cap(const pcireg_t *regs, int capoff, int extcapoff)
2857 {
2858 pcireg_t reg, cap, ctl;
2859 unsigned int num;
2860
2861 printf("\n Process Address Space ID\n");
2862
2863 reg = regs[o2i(extcapoff + PCI_PASID_CAP)];
2864 cap = reg & 0xffff;
2865 ctl = reg >> 16;
2866 printf(" PASID Capability Register: 0x%04x\n", cap);
2867 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM);
2868 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE);
2869 num = (1 << __SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1;
2870 printf(" Max PASID Width: %u\n", num);
2871
2872 printf(" PASID Control Register: 0x%04x\n", ctl);
2873 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN);
2874 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN);
2875 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN);
2876 }
2877
2878 static void
2879 pci_conf_print_lnr_cap(const pcireg_t *regs, int capoff, int extcapoff)
2880 {
2881 pcireg_t reg, cap, ctl;
2882 unsigned int num;
2883
2884 printf("\n LN Requester\n");
2885
2886 reg = regs[o2i(extcapoff + PCI_LNR_CAP)];
2887 cap = reg & 0xffff;
2888 ctl = reg >> 16;
2889 printf(" LNR Capability register: 0x%04x\n", cap);
2890 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64);
2891 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128);
2892 num = 1 << __SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX);
2893 printf(" LNR Registration MAX: %u\n", num);
2894
2895 printf(" LNR Control register: 0x%04x\n", ctl);
2896 onoff("LNR Enable", reg, PCI_LNR_CTL_EN);
2897 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS);
2898 num = 1 << __SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM);
2899 printf(" LNR Registration Limit: %u\n", num);
2900 }
2901
2902 /* XXX pci_conf_print_dpc_cap */
2903
2904 static int
2905 pci_conf_l1pm_cap_tposcale(unsigned char scale)
2906 {
2907
2908 /* Return scale in us */
2909 switch (scale) {
2910 case 0x0:
2911 return 2;
2912 case 0x1:
2913 return 10;
2914 case 0x2:
2915 return 100;
2916 default:
2917 return -1;
2918 }
2919 }
2920
2921 static void
2922 pci_conf_print_l1pm_cap(const pcireg_t *regs, int capoff, int extcapoff)
2923 {
2924 pcireg_t reg;
2925 int scale, val;
2926
2927 printf("\n L1 PM Substates\n");
2928
2929 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)];
2930 printf(" L1 PM Substates Capability register: 0x%08x\n", reg);
2931 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12);
2932 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11);
2933 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12);
2934 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11);
2935 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM);
2936 printf(" Port Common Mode Restore Time: %uus\n",
2937 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT));
2938 scale = pci_conf_l1pm_cap_tposcale(
2939 __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE));
2940 val = __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL);
2941 printf(" Port T_POWER_ON: ");
2942 if (scale == -1)
2943 printf("unknown\n");
2944 else
2945 printf("%dus\n", val * scale);
2946
2947 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)];
2948 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg);
2949 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN);
2950 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN);
2951 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN);
2952 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN);
2953 printf(" Common Mode Restore Time: %uus\n",
2954 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT));
2955 scale = PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE));
2956 val = __SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL);
2957 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale);
2958
2959 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)];
2960 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg);
2961 scale = pci_conf_l1pm_cap_tposcale(
2962 __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE));
2963 val = __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL);
2964 printf(" T_POWER_ON: ");
2965 if (scale == -1)
2966 printf("unknown\n");
2967 else
2968 printf("%dus\n", val * scale);
2969 }
2970
2971 /* XXX pci_conf_print_ptm_cap */
2972 /* XXX pci_conf_print_mpcie_cap */
2973 /* XXX pci_conf_print_frsq_cap */
2974 /* XXX pci_conf_print_rtr_cap */
2975 /* XXX pci_conf_print_desigvndsp_cap */
2976
2977 #undef MS
2978 #undef SM
2979 #undef RW
2980
2981 static struct {
2982 pcireg_t cap;
2983 const char *name;
2984 void (*printfunc)(const pcireg_t *, int, int);
2985 } pci_extcaptab[] = {
2986 { 0, "reserved",
2987 NULL },
2988 { PCI_EXTCAP_AER, "Advanced Error Reporting",
2989 pci_conf_print_aer_cap },
2990 { PCI_EXTCAP_VC, "Virtual Channel",
2991 pci_conf_print_vc_cap },
2992 { PCI_EXTCAP_SERNUM, "Device Serial Number",
2993 pci_conf_print_sernum_cap },
2994 { PCI_EXTCAP_PWRBDGT, "Power Budgeting",
2995 pci_conf_print_pwrbdgt_cap },
2996 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration",
2997 pci_conf_print_rclink_dcl_cap },
2998 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control",
2999 NULL },
3000 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association",
3001 pci_conf_print_rcec_assoc_cap },
3002 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel",
3003 NULL },
3004 { PCI_EXTCAP_VC2, "Virtual Channel",
3005 NULL },
3006 { PCI_EXTCAP_RCRB, "RCRB Header",
3007 NULL },
3008 { PCI_EXTCAP_VENDOR, "Vendor Unique",
3009 NULL },
3010 { PCI_EXTCAP_CAC, "Configuration Access Correction",
3011 NULL },
3012 { PCI_EXTCAP_ACS, "Access Control Services",
3013 pci_conf_print_acs_cap },
3014 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation",
3015 pci_conf_print_ari_cap },
3016 { PCI_EXTCAP_ATS, "Address Translation Services",
3017 pci_conf_print_ats_cap },
3018 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization",
3019 pci_conf_print_sriov_cap },
3020 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization",
3021 NULL },
3022 { PCI_EXTCAP_MULTICAST, "Multicast",
3023 NULL },
3024 { PCI_EXTCAP_PAGE_REQ, "Page Request",
3025 pci_conf_print_page_req_cap },
3026 { PCI_EXTCAP_AMD, "Reserved for AMD",
3027 NULL },
3028 { PCI_EXTCAP_RESIZE_BAR,"Resizable BAR",
3029 NULL },
3030 { PCI_EXTCAP_DPA, "Dynamic Power Allocation",
3031 NULL },
3032 { PCI_EXTCAP_TPH_REQ, "TPH Requester",
3033 pci_conf_print_tph_req_cap },
3034 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting",
3035 pci_conf_print_ltr_cap },
3036 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express",
3037 pci_conf_print_sec_pcie_cap },
3038 { PCI_EXTCAP_PMUX, "Protocol Multiplexing",
3039 NULL },
3040 { PCI_EXTCAP_PASID, "Process Address Space ID",
3041 pci_conf_print_pasid_cap },
3042 { PCI_EXTCAP_LN_REQ, "LN Requester",
3043 pci_conf_print_lnr_cap },
3044 { PCI_EXTCAP_DPC, "Downstream Port Containment",
3045 NULL },
3046 { PCI_EXTCAP_L1PM, "L1 PM Substates",
3047 pci_conf_print_l1pm_cap },
3048 { PCI_EXTCAP_PTM, "Precision Time Management",
3049 NULL },
3050 { PCI_EXTCAP_MPCIE, "M-PCIe",
3051 NULL },
3052 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing",
3053 NULL },
3054 { PCI_EXTCAP_RTR, "Readiness Time Reporting",
3055 NULL },
3056 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific",
3057 NULL },
3058 };
3059
3060 static int
3061 pci_conf_find_extcap(const pcireg_t *regs, int capoff, unsigned int capid,
3062 int *offsetp)
3063 {
3064 int off;
3065 pcireg_t rval;
3066
3067 for (off = PCI_EXTCAPLIST_BASE;
3068 off != 0;
3069 off = PCI_EXTCAPLIST_NEXT(rval)) {
3070 rval = regs[o2i(off)];
3071 if (capid == PCI_EXTCAPLIST_CAP(rval)) {
3072 if (offsetp != NULL)
3073 *offsetp = off;
3074 return 1;
3075 }
3076 }
3077 return 0;
3078 }
3079
3080 static void
3081 pci_conf_print_extcaplist(
3082 #ifdef _KERNEL
3083 pci_chipset_tag_t pc, pcitag_t tag,
3084 #endif
3085 const pcireg_t *regs, int capoff)
3086 {
3087 int off;
3088 pcireg_t foundcap;
3089 pcireg_t rval;
3090 bool foundtable[__arraycount(pci_extcaptab)];
3091 unsigned int i;
3092
3093 /* Check Extended capability structure */
3094 off = PCI_EXTCAPLIST_BASE;
3095 rval = regs[o2i(off)];
3096 if (rval == 0xffffffff || rval == 0)
3097 return;
3098
3099 /* Clear table */
3100 for (i = 0; i < __arraycount(pci_extcaptab); i++)
3101 foundtable[i] = false;
3102
3103 /* Print extended capability register's offset and the type first */
3104 for (;;) {
3105 printf(" Extended Capability Register at 0x%02x\n", off);
3106
3107 foundcap = PCI_EXTCAPLIST_CAP(rval);
3108 printf(" type: 0x%04x (", foundcap);
3109 if (foundcap < __arraycount(pci_extcaptab)) {
3110 printf("%s)\n", pci_extcaptab[foundcap].name);
3111 /* Mark as found */
3112 foundtable[foundcap] = true;
3113 } else
3114 printf("unknown)\n");
3115 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval));
3116
3117 off = PCI_EXTCAPLIST_NEXT(rval);
3118 if (off == 0)
3119 break;
3120 rval = regs[o2i(off)];
3121 }
3122
3123 /*
3124 * And then, print the detail of each capability registers
3125 * in capability value's order.
3126 */
3127 for (i = 0; i < __arraycount(pci_extcaptab); i++) {
3128 if (foundtable[i] == false)
3129 continue;
3130
3131 /*
3132 * The type was found. Search capability list again and
3133 * print all capabilities that the capabiliy type is
3134 * the same.
3135 */
3136 if (pci_conf_find_extcap(regs, capoff, i, &off) == 0)
3137 continue;
3138 rval = regs[o2i(off)];
3139 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0)
3140 || (pci_extcaptab[i].printfunc == NULL))
3141 continue;
3142
3143 pci_extcaptab[i].printfunc(regs, capoff, off);
3144
3145 }
3146 }
3147
3148 /* Print the Secondary Status Register. */
3149 static void
3150 pci_conf_print_ssr(pcireg_t rval)
3151 {
3152 pcireg_t devsel;
3153
3154 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */
3155 onoff("66 MHz capable", rval, __BIT(5));
3156 onoff("User Definable Features (UDF) support", rval, __BIT(6));
3157 onoff("Fast back-to-back capable", rval, __BIT(7));
3158 onoff("Data parity error detected", rval, __BIT(8));
3159
3160 printf(" DEVSEL timing: ");
3161 devsel = __SHIFTOUT(rval, __BITS(10, 9));
3162 switch (devsel) {
3163 case 0:
3164 printf("fast");
3165 break;
3166 case 1:
3167 printf("medium");
3168 break;
3169 case 2:
3170 printf("slow");
3171 break;
3172 default:
3173 printf("unknown/reserved"); /* XXX */
3174 break;
3175 }
3176 printf(" (0x%x)\n", devsel);
3177
3178 onoff("Signalled target abort", rval, __BIT(11));
3179 onoff("Received target abort", rval, __BIT(12));
3180 onoff("Received master abort", rval, __BIT(13));
3181 onoff("Received system error", rval, __BIT(14));
3182 onoff("Detected parity error", rval, __BIT(15));
3183 }
3184
3185 static void
3186 pci_conf_print_type0(
3187 #ifdef _KERNEL
3188 pci_chipset_tag_t pc, pcitag_t tag,
3189 #endif
3190 const pcireg_t *regs
3191 #ifdef _KERNEL
3192 , int sizebars
3193 #endif
3194 )
3195 {
3196 int off, width;
3197 pcireg_t rval;
3198
3199 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) {
3200 #ifdef _KERNEL
3201 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars);
3202 #else
3203 width = pci_conf_print_bar(regs, off, NULL);
3204 #endif
3205 }
3206
3207 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]);
3208
3209 rval = regs[o2i(PCI_SUBSYS_ID_REG)];
3210 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval));
3211 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval));
3212
3213 /* XXX */
3214 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]);
3215
3216 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)
3217 printf(" Capability list pointer: 0x%02x\n",
3218 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)]));
3219 else
3220 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]);
3221
3222 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]);
3223
3224 rval = regs[o2i(PCI_INTERRUPT_REG)];
3225 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff);
3226 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff);
3227 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval));
3228 switch (PCI_INTERRUPT_PIN(rval)) {
3229 case PCI_INTERRUPT_PIN_NONE:
3230 printf("(none)");
3231 break;
3232 case PCI_INTERRUPT_PIN_A:
3233 printf("(pin A)");
3234 break;
3235 case PCI_INTERRUPT_PIN_B:
3236 printf("(pin B)");
3237 break;
3238 case PCI_INTERRUPT_PIN_C:
3239 printf("(pin C)");
3240 break;
3241 case PCI_INTERRUPT_PIN_D:
3242 printf("(pin D)");
3243 break;
3244 default:
3245 printf("(? ? ?)");
3246 break;
3247 }
3248 printf("\n");
3249 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval));
3250 }
3251
3252 static void
3253 pci_conf_print_type1(
3254 #ifdef _KERNEL
3255 pci_chipset_tag_t pc, pcitag_t tag,
3256 #endif
3257 const pcireg_t *regs
3258 #ifdef _KERNEL
3259 , int sizebars
3260 #endif
3261 )
3262 {
3263 int off, width;
3264 pcireg_t rval;
3265 uint32_t base, limit;
3266 uint32_t base_h, limit_h;
3267 uint64_t pbase, plimit;
3268 int use_upper;
3269
3270 /*
3271 * This layout was cribbed from the TI PCI2030 PCI-to-PCI
3272 * Bridge chip documentation, and may not be correct with
3273 * respect to various standards. (XXX)
3274 */
3275
3276 for (off = 0x10; off < 0x18; off += width) {
3277 #ifdef _KERNEL
3278 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars);
3279 #else
3280 width = pci_conf_print_bar(regs, off, NULL);
3281 #endif
3282 }
3283
3284 rval = regs[o2i(PCI_BRIDGE_BUS_REG)];
3285 printf(" Primary bus number: 0x%02x\n",
3286 PCI_BRIDGE_BUS_PRIMARY(rval));
3287 printf(" Secondary bus number: 0x%02x\n",
3288 PCI_BRIDGE_BUS_SECONDARY(rval));
3289 printf(" Subordinate bus number: 0x%02x\n",
3290 PCI_BRIDGE_BUS_SUBORDINATE(rval));
3291 printf(" Secondary bus latency timer: 0x%02x\n",
3292 PCI_BRIDGE_BUS_SEC_LATTIMER(rval));
3293
3294 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)];
3295 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16)));
3296
3297 /* I/O region */
3298 printf(" I/O region:\n");
3299 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff);
3300 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff);
3301 if (PCI_BRIDGE_IO_32BITS(rval))
3302 use_upper = 1;
3303 else
3304 use_upper = 0;
3305 onoff("32bit I/O", rval, use_upper);
3306 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8;
3307 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT)
3308 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8;
3309 limit |= 0x00000fff;
3310
3311 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)];
3312 base_h = (rval >> 0) & 0xffff;
3313 limit_h = (rval >> 16) & 0xffff;
3314 printf(" base upper 16 bits register: 0x%04x\n", base_h);
3315 printf(" limit upper 16 bits register: 0x%04x\n", limit_h);
3316
3317 if (use_upper == 1) {
3318 base |= base_h << 16;
3319 limit |= limit_h << 16;
3320 }
3321 if (base < limit) {
3322 if (use_upper == 1)
3323 printf(" range: 0x%08x-0x%08x\n", base, limit);
3324 else
3325 printf(" range: 0x%04x-0x%04x\n", base, limit);
3326 } else
3327 printf(" range: not set\n");
3328
3329 /* Non-prefetchable memory region */
3330 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)];
3331 printf(" Memory region:\n");
3332 printf(" base register: 0x%04x\n",
3333 (rval >> 0) & 0xffff);
3334 printf(" limit register: 0x%04x\n",
3335 (rval >> 16) & 0xffff);
3336 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT)
3337 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20;
3338 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT)
3339 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff;
3340 if (base < limit)
3341 printf(" range: 0x%08x-0x%08x\n", base, limit);
3342 else
3343 printf(" range: not set\n");
3344
3345 /* Prefetchable memory region */
3346 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)];
3347 printf(" Prefetchable memory region:\n");
3348 printf(" base register: 0x%04x\n",
3349 (rval >> 0) & 0xffff);
3350 printf(" limit register: 0x%04x\n",
3351 (rval >> 16) & 0xffff);
3352 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)];
3353 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)];
3354 printf(" base upper 32 bits register: 0x%08x\n",
3355 base_h);
3356 printf(" limit upper 32 bits register: 0x%08x\n",
3357 limit_h);
3358 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval))
3359 use_upper = 1;
3360 else
3361 use_upper = 0;
3362 onoff("64bit memory address", rval, use_upper);
3363 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT)
3364 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20;
3365 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT)
3366 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff;
3367 if (use_upper == 1) {
3368 pbase |= (uint64_t)base_h << 32;
3369 plimit |= (uint64_t)limit_h << 32;
3370 }
3371 if (pbase < plimit) {
3372 if (use_upper == 1)
3373 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64
3374 "\n", pbase, plimit);
3375 else
3376 printf(" range: 0x%08x-0x%08x\n",
3377 (uint32_t)pbase, (uint32_t)plimit);
3378 } else
3379 printf(" range: not set\n");
3380
3381 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)
3382 printf(" Capability list pointer: 0x%02x\n",
3383 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)]));
3384 else
3385 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]);
3386
3387 /* XXX */
3388 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]);
3389
3390 rval = regs[o2i(PCI_INTERRUPT_REG)];
3391 printf(" Interrupt line: 0x%02x\n",
3392 (rval >> 0) & 0xff);
3393 printf(" Interrupt pin: 0x%02x ",
3394 (rval >> 8) & 0xff);
3395 switch ((rval >> 8) & 0xff) {
3396 case PCI_INTERRUPT_PIN_NONE:
3397 printf("(none)");
3398 break;
3399 case PCI_INTERRUPT_PIN_A:
3400 printf("(pin A)");
3401 break;
3402 case PCI_INTERRUPT_PIN_B:
3403 printf("(pin B)");
3404 break;
3405 case PCI_INTERRUPT_PIN_C:
3406 printf("(pin C)");
3407 break;
3408 case PCI_INTERRUPT_PIN_D:
3409 printf("(pin D)");
3410 break;
3411 default:
3412 printf("(? ? ?)");
3413 break;
3414 }
3415 printf("\n");
3416 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT)
3417 & PCI_BRIDGE_CONTROL_MASK;
3418 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */
3419 onoff("Parity error response", rval, 0x0001);
3420 onoff("Secondary SERR forwarding", rval, 0x0002);
3421 onoff("ISA enable", rval, 0x0004);
3422 onoff("VGA enable", rval, 0x0008);
3423 onoff("Master abort reporting", rval, 0x0020);
3424 onoff("Secondary bus reset", rval, 0x0040);
3425 onoff("Fast back-to-back capable", rval, 0x0080);
3426 }
3427
3428 static void
3429 pci_conf_print_type2(
3430 #ifdef _KERNEL
3431 pci_chipset_tag_t pc, pcitag_t tag,
3432 #endif
3433 const pcireg_t *regs
3434 #ifdef _KERNEL
3435 , int sizebars
3436 #endif
3437 )
3438 {
3439 pcireg_t rval;
3440
3441 /*
3442 * XXX these need to be printed in more detail, need to be
3443 * XXX checked against specs/docs, etc.
3444 *
3445 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus
3446 * controller chip documentation, and may not be correct with
3447 * respect to various standards. (XXX)
3448 */
3449
3450 #ifdef _KERNEL
3451 pci_conf_print_bar(pc, tag, regs, 0x10,
3452 "CardBus socket/ExCA registers", sizebars);
3453 #else
3454 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers");
3455 #endif
3456
3457 /* Capability list pointer and secondary status register */
3458 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)];
3459 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)
3460 printf(" Capability list pointer: 0x%02x\n",
3461 PCI_CAPLIST_PTR(rval));
3462 else
3463 printf(" Reserved @ 0x14: 0x%04x\n",
3464 (pcireg_t)__SHIFTOUT(rval, __BITS(15, 0)));
3465 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16)));
3466
3467 rval = regs[o2i(PCI_BRIDGE_BUS_REG)];
3468 printf(" PCI bus number: 0x%02x\n",
3469 (rval >> 0) & 0xff);
3470 printf(" CardBus bus number: 0x%02x\n",
3471 (rval >> 8) & 0xff);
3472 printf(" Subordinate bus number: 0x%02x\n",
3473 (rval >> 16) & 0xff);
3474 printf(" CardBus latency timer: 0x%02x\n",
3475 (rval >> 24) & 0xff);
3476
3477 /* XXX Print more prettily */
3478 printf(" CardBus memory region 0:\n");
3479 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]);
3480 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]);
3481 printf(" CardBus memory region 1:\n");
3482 printf(" base register: 0x%08x\n", regs[o2i(0x24)]);
3483 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]);
3484 printf(" CardBus I/O region 0:\n");
3485 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]);
3486 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]);
3487 printf(" CardBus I/O region 1:\n");
3488 printf(" base register: 0x%08x\n", regs[o2i(0x34)]);
3489 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]);
3490
3491 rval = regs[o2i(PCI_INTERRUPT_REG)];
3492 printf(" Interrupt line: 0x%02x\n",
3493 (rval >> 0) & 0xff);
3494 printf(" Interrupt pin: 0x%02x ",
3495 (rval >> 8) & 0xff);
3496 switch ((rval >> 8) & 0xff) {
3497 case PCI_INTERRUPT_PIN_NONE:
3498 printf("(none)");
3499 break;
3500 case PCI_INTERRUPT_PIN_A:
3501 printf("(pin A)");
3502 break;
3503 case PCI_INTERRUPT_PIN_B:
3504 printf("(pin B)");
3505 break;
3506 case PCI_INTERRUPT_PIN_C:
3507 printf("(pin C)");
3508 break;
3509 case PCI_INTERRUPT_PIN_D:
3510 printf("(pin D)");
3511 break;
3512 default:
3513 printf("(? ? ?)");
3514 break;
3515 }
3516 printf("\n");
3517 rval = (regs[o2i(0x3c)] >> 16) & 0xffff;
3518 printf(" Bridge control register: 0x%04x\n", rval);
3519 onoff("Parity error response", rval, __BIT(0));
3520 onoff("SERR# enable", rval, __BIT(1));
3521 onoff("ISA enable", rval, __BIT(2));
3522 onoff("VGA enable", rval, __BIT(3));
3523 onoff("Master abort mode", rval, __BIT(5));
3524 onoff("Secondary (CardBus) bus reset", rval, __BIT(6));
3525 onoff("Functional interrupts routed by ExCA registers", rval,
3526 __BIT(7));
3527 onoff("Memory window 0 prefetchable", rval, __BIT(8));
3528 onoff("Memory window 1 prefetchable", rval, __BIT(9));
3529 onoff("Write posting enable", rval, __BIT(10));
3530
3531 rval = regs[o2i(0x40)];
3532 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval));
3533 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval));
3534
3535 #ifdef _KERNEL
3536 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers",
3537 sizebars);
3538 #else
3539 pci_conf_print_bar(regs, 0x44, "legacy-mode registers");
3540 #endif
3541 }
3542
3543 void
3544 pci_conf_print(
3545 #ifdef _KERNEL
3546 pci_chipset_tag_t pc, pcitag_t tag,
3547 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *)
3548 #else
3549 int pcifd, u_int bus, u_int dev, u_int func
3550 #endif
3551 )
3552 {
3553 pcireg_t regs[o2i(PCI_EXTCONF_SIZE)];
3554 int off, capoff, endoff, hdrtype;
3555 const char *type_name;
3556 #ifdef _KERNEL
3557 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *,
3558 int);
3559 int sizebars;
3560 #else
3561 void (*type_printfn)(const pcireg_t *);
3562 #endif
3563
3564 printf("PCI configuration registers:\n");
3565
3566 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) {
3567 #ifdef _KERNEL
3568 regs[o2i(off)] = pci_conf_read(pc, tag, off);
3569 #else
3570 if (pcibus_conf_read(pcifd, bus, dev, func, off,
3571 &regs[o2i(off)]) == -1)
3572 regs[o2i(off)] = 0;
3573 #endif
3574 }
3575
3576 #ifdef _KERNEL
3577 sizebars = 1;
3578 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE &&
3579 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST)
3580 sizebars = 0;
3581 #endif
3582
3583 /* common header */
3584 printf(" Common header:\n");
3585 pci_conf_print_regs(regs, 0, 16);
3586
3587 printf("\n");
3588 #ifdef _KERNEL
3589 pci_conf_print_common(pc, tag, regs);
3590 #else
3591 pci_conf_print_common(regs);
3592 #endif
3593 printf("\n");
3594
3595 /* type-dependent header */
3596 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]);
3597 switch (hdrtype) { /* XXX make a table, eventually */
3598 case 0:
3599 /* Standard device header */
3600 type_name = "\"normal\" device";
3601 type_printfn = &pci_conf_print_type0;
3602 capoff = PCI_CAPLISTPTR_REG;
3603 endoff = 64;
3604 break;
3605 case 1:
3606 /* PCI-PCI bridge header */
3607 type_name = "PCI-PCI bridge";
3608 type_printfn = &pci_conf_print_type1;
3609 capoff = PCI_CAPLISTPTR_REG;
3610 endoff = 64;
3611 break;
3612 case 2:
3613 /* PCI-CardBus bridge header */
3614 type_name = "PCI-CardBus bridge";
3615 type_printfn = &pci_conf_print_type2;
3616 capoff = PCI_CARDBUS_CAPLISTPTR_REG;
3617 endoff = 72;
3618 break;
3619 default:
3620 type_name = NULL;
3621 type_printfn = 0;
3622 capoff = -1;
3623 endoff = 64;
3624 break;
3625 }
3626 printf(" Type %d ", hdrtype);
3627 if (type_name != NULL)
3628 printf("(%s) ", type_name);
3629 printf("header:\n");
3630 pci_conf_print_regs(regs, 16, endoff);
3631 printf("\n");
3632 if (type_printfn) {
3633 #ifdef _KERNEL
3634 (*type_printfn)(pc, tag, regs, sizebars);
3635 #else
3636 (*type_printfn)(regs);
3637 #endif
3638 } else
3639 printf(" Don't know how to pretty-print type %d header.\n",
3640 hdrtype);
3641 printf("\n");
3642
3643 /* capability list, if present */
3644 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)
3645 && (capoff > 0)) {
3646 #ifdef _KERNEL
3647 pci_conf_print_caplist(pc, tag, regs, capoff);
3648 #else
3649 pci_conf_print_caplist(regs, capoff);
3650 #endif
3651 printf("\n");
3652 }
3653
3654 /* device-dependent header */
3655 printf(" Device-dependent header:\n");
3656 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE);
3657 printf("\n");
3658 #ifdef _KERNEL
3659 if (printfn)
3660 (*printfn)(pc, tag, regs);
3661 else
3662 printf(" Don't know how to pretty-print device-dependent header.\n");
3663 printf("\n");
3664 #endif /* _KERNEL */
3665
3666 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff ||
3667 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0)
3668 return;
3669
3670 #ifdef _KERNEL
3671 pci_conf_print_extcaplist(pc, tag, regs, capoff);
3672 #else
3673 pci_conf_print_extcaplist(regs, capoff);
3674 #endif
3675 printf("\n");
3676
3677 /* Extended Configuration Space, if present */
3678 printf(" Extended Configuration Space:\n");
3679 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE);
3680 }
3681 #endif /* defined(__minix) && !defined(_PCI_SERVER) */
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