drivers/ahci/ahci.h

   1 #ifndef _AHCI_H
   2 #define _AHCI_H
   3
   4 #include <minix/drivers.h>
   5
   6 #define NR_PORTS 32             /* maximum number of ports */
   7 #define NR_CMDS 32              /* maximum number of queued commands */
   8
   9 /* Time values that can be set with options. */
  10 #define SPINUP_TIMEOUT          5000    /* initial spin-up time (ms) */
  11 #define SIG_TIMEOUT             250     /* time between signature checks (ms) */
  12 #define NR_SIG_CHECKS           60      /* maximum number of times to check */
  13 #define COMMAND_TIMEOUT         10000   /* time to wait for non-I/O cmd (ms) */
  14 #define TRANSFER_TIMEOUT        30000   /* time to wait for I/O cmd (ms) */
  15 #define FLUSH_TIMEOUT           60000   /* time to wait for flush cmd (ms) */
  16
  17 /* Time values that are defined by the standards. */
  18 #define SPINUP_DELAY            1       /* time to assert spin-up flag (ms) */
  19 #define RESET_DELAY             1000    /* maximum HBA reset time (ms) */
  20 #define PORTREG_DELAY           500     /* maximum port register update (ms) */
  21
  22 /* Generic FIS layout. */
  23 #define ATA_FIS_TYPE                    0       /* FIS Type */
  24 #define         ATA_FIS_TYPE_H2D        0x27    /* Register - Host to Device */
  25
  26 /* Register - Host to Device FIS layout. */
  27 #define ATA_H2D_SIZE                    20      /* byte size of H2D FIS */
  28 #define ATA_H2D_FLAGS                   1       /* C and PM Port */
  29 #define         ATA_H2D_FLAGS_C         0x80    /* update command register */
  30 #define ATA_H2D_CMD                     2       /* Command */
  31 #define         ATA_CMD_READ_DMA_EXT    0x25    /* READ DMA EXT */
  32 #define         ATA_CMD_WRITE_DMA_EXT   0x35    /* WRITE DMA EXT */
  33 #define         ATA_CMD_READ_FPDMA_QUEUED       0x60    /* READ FPDMA QUEUED */
  34 #define         ATA_CMD_WRITE_FPDMA_QUEUED      0x61    /* WRITE FPDMA QUEUED */
  35 #define         ATA_CMD_WRITE_DMA_FUA_EXT       0x3D    /* WRITE DMA FUA EXT */
  36 #define         ATA_CMD_PACKET          0xA0    /* PACKET */
  37 #define         ATA_CMD_IDENTIFY_PACKET 0xA1    /* IDENTIFY PACKET DEVICE */
  38 #define         ATA_CMD_FLUSH_CACHE     0xE7    /* FLUSH CACHE */
  39 #define         ATA_CMD_IDENTIFY        0xEC    /* IDENTIFY DEVICE */
  40 #define         ATA_CMD_SET_FEATURES    0xEF    /* SET FEATURES */
  41 #define ATA_H2D_FEAT                    3       /* Features */
  42 #define         ATA_FEAT_PACKET_DMA     0x01    /* use DMA */
  43 #define         ATA_FEAT_PACKET_DMADIR  0x03    /* DMA is inbound */
  44 #define ATA_H2D_LBA_LOW                 4       /* LBA Low */
  45 #define ATA_H2D_LBA_MID                 5       /* LBA Mid */
  46 #define ATA_H2D_LBA_HIGH                6       /* LBA High */
  47 #define ATA_H2D_DEV                     7       /* Device */
  48 #define         ATA_DEV_LBA             0x40    /* use LBA addressing */
  49 #define         ATA_DEV_FUA             0x80    /* Force Unit Access (FPDMA) */
  50 #define ATA_H2D_LBA_LOW_EXP             8       /* LBA Low (exp) */
  51 #define ATA_H2D_LBA_MID_EXP             9       /* LBA Mid (exp) */
  52 #define ATA_H2D_LBA_HIGH_EXP            10      /* LBA High (exp) */
  53 #define ATA_H2D_FEAT_EXP                11      /* Features (exp) */
  54 #define ATA_H2D_SEC                     12      /* Sector Count */
  55 #define         ATA_SEC_TAG_SHIFT       3       /* NCQ command tag */
  56 #define ATA_H2D_SEC_EXP                 13      /* Sector Count (exp) */
  57 #define ATA_H2D_CTL                     15      /* Control */
  58
  59 #define ATA_IS_FPDMA_CMD(c)                     \
  60         ((c) == ATA_CMD_READ_FPDMA_QUEUED ||    \
  61          (c) == ATA_CMD_WRITE_FPDMA_QUEUED)
  62
  63 /* ATA constants. */
  64 #define ATA_SECTOR_SIZE         512             /* default sector size */
  65 #define ATA_MAX_SECTORS         0x10000         /* max sectors per transfer */
  66
  67 #define ATA_ID_SIZE     (256 * sizeof(u16_t))   /* IDENTIFY result size */
  68
  69 #define ATA_ID_GCAP             0               /* General capabililties */
  70 #define ATA_ID_GCAP_ATAPI_MASK  0xC000          /* ATAPI device mask */
  71 #define ATA_ID_GCAP_ATAPI       0x8000          /* ATAPI device */
  72 #define ATA_ID_GCAP_ATA_MASK    0x8000          /* ATA device mask */
  73 #define ATA_ID_GCAP_ATA         0x0000          /* ATA device */
  74 #define ATA_ID_GCAP_TYPE_MASK   0x1F00          /* ATAPI device type */
  75 #define ATA_ID_GCAP_TYPE_SHIFT  8               /* (one of ATAPI_TYPE_*) */
  76 #define ATA_ID_GCAP_REMOVABLE   0x0080          /* Removable media device */
  77 #define ATA_ID_GCAP_INCOMPLETE  0x0004          /* Incomplete response */
  78 #define ATA_ID_CAP              49              /* Capabilities */
  79 #define ATA_ID_CAP_DMA          0x0100          /* DMA supported (no DMADIR) */
  80 #define ATA_ID_CAP_LBA          0x0200          /* LBA supported */
  81 #define ATA_ID_DMADIR           62              /* DMADIR */
  82 #define ATA_ID_DMADIR_DMADIR    0x8000          /* DMADIR required */
  83 #define ATA_ID_DMADIR_DMA       0x0400          /* DMA supported (DMADIR) */
  84 #define ATA_ID_QDEPTH           75              /* NCQ queue depth */
  85 #define ATA_ID_QDEPTH_MASK      0x000F          /* NCQ queue depth mask */
  86 #define ATA_ID_SATA_CAP         76              /* SATA capabilities */
  87 #define ATA_ID_SATA_CAP_NCQ     0x0100          /* NCQ support */
  88 #define ATA_ID_SUP0             82              /* Features supported (1/3) */
  89 #define ATA_ID_SUP0_WCACHE      0x0020          /* Write cache supported */
  90 #define ATA_ID_SUP1             83              /* Features supported (2/3) */
  91 #define ATA_ID_SUP1_VALID_MASK  0xC000          /* Word validity mask */
  92 #define ATA_ID_SUP1_VALID       0x4000          /* Word contents are valid */
  93 #define ATA_ID_SUP1_FLUSH       0x1000          /* FLUSH CACHE supported */
  94 #define ATA_ID_SUP1_LBA48       0x0400          /* 48-bit LBA supported */
  95 #define ATA_ID_ENA0             85              /* Features enabled (1/3) */
  96 #define ATA_ID_ENA0_WCACHE      0x0020          /* Write cache enabled */
  97 #define ATA_ID_ENA2             87              /* Features enabled (3/3) */
  98 #define ATA_ID_ENA2_VALID_MASK  0xC000          /* Word validity mask */
  99 #define ATA_ID_ENA2_VALID       0x4000          /* Word contents are valid */
 100 #define ATA_ID_ENA2_FUA         0x0040          /* Forced Unit Access sup. */
 101 #define ATA_ID_LBA0             100             /* Max. LBA48 address (LSW) */
 102 #define ATA_ID_LBA1             101             /* Max. LBA48 address */
 103 #define ATA_ID_LBA2             102             /* Max. LBA48 address */
 104 #define ATA_ID_LBA3             103             /* Max. LBA48 address (MSW) */
 105 #define ATA_ID_PLSS             106             /* Phys./logical sector size */
 106 #define ATA_ID_PLSS_VALID_MASK  0xC000          /* Word validity mask */
 107 #define ATA_ID_PLSS_VALID       0x4000          /* Word contents are valid */
 108 #define ATA_ID_PLSS_LLS         0x1000          /* Long logical sectors */
 109 #define ATA_ID_LSS0             118             /* Logical sector size (LSW) */
 110 #define ATA_ID_LSS1             119             /* Logical sector size (MSW) */
 111
 112 #define ATA_SF_EN_WCACHE        0x02            /* Enable write cache */
 113 #define ATA_SF_DI_WCACHE        0x82            /* Disable write cache */
 114
 115 /* ATAPI constants. */
 116 #define ATAPI_PACKET_SIZE       16              /* ATAPI packet size */
 117
 118 #define ATAPI_TYPE_CDROM        5               /* CD-ROM device */
 119
 120 #define ATAPI_CMD_TEST_UNIT     0x00            /* Test Unit Ready */
 121 #define ATAPI_CMD_REQUEST_SENSE 0x03            /* Request Sense */
 122 #define         ATAPI_REQUEST_SENSE_LEN 18              /* result length */
 123 #define         ATAPI_SENSE_UNIT_ATT    6               /* Unit Attention */
 124 #define ATAPI_CMD_START_STOP    0x1B            /* Start/Stop Unit */
 125 #define         ATAPI_START_STOP_EJECT  0x02            /* eject the medium */
 126 #define         ATAPI_START_STOP_LOAD   0x03            /* load the medium */
 127 #define ATAPI_CMD_READ_CAPACITY 0x25            /* Read Capacity */
 128 #define         ATAPI_READ_CAPACITY_LEN 8               /* result length */
 129 #define ATAPI_CMD_READ          0xA8            /* Read (12) */
 130 #define ATAPI_CMD_WRITE         0xAA            /* Write (12) */
 131
 132 /* Command List constants. */
 133 #define AHCI_CL_ENTRY_SIZE      32              /* Command List header size */
 134 #define AHCI_CL_ENTRY_DWORDS    (AHCI_CL_ENTRY_SIZE / sizeof(u32_t))
 135
 136 #define AHCI_CL_PRDTL_SHIFT     16              /* PRD Table Length */
 137 #define AHCI_CL_PREFETCHABLE    (1L << 7)       /* Prefetchable */
 138 #define AHCI_CL_WRITE           (1L << 6)       /* Write */
 139 #define AHCI_CL_ATAPI           (1L << 5)       /* ATAPI */
 140 #define AHCI_CL_CFL_SHIFT       0               /* Command FIS Length */
 141
 142 /* Command Table offsets. */
 143 #define AHCI_CT_PACKET_OFF              0x40    /* CT offset to ATAPI packet */
 144 #define AHCI_CT_PRDT_OFF                0x80    /* CT offset to PRD table */
 145
 146 /* Host Bus Adapter (HBA) constants. */
 147 #define AHCI_HBA_CAP    0               /* Host Capabilities */
 148 #define         AHCI_HBA_CAP_SNCQ       (1L << 30)      /* Native Cmd Queuing */
 149 #define         AHCI_HBA_CAP_SCLO       (1L << 24)      /* Cmd List Override */
 150 #define         AHCI_HBA_CAP_NCS_SHIFT  8               /* Nr of Cmd Slots */
 151 #define         AHCI_HBA_CAP_NCS_MASK   0x1FL
 152 #define         AHCI_HBA_CAP_NP_SHIFT   0               /* Nr of Ports */
 153 #define         AHCI_HBA_CAP_NP_MASK    0x1FL
 154 #define AHCI_HBA_GHC    1               /* Global Host Control */
 155 #define         AHCI_HBA_GHC_AE         (1L << 31)      /* AHCI Enable */
 156 #define         AHCI_HBA_GHC_IE         (1L <<  1)      /* Interrupt Enable */
 157 #define         AHCI_HBA_GHC_HR         (1L <<  0)      /* HBA Reset */
 158 #define AHCI_HBA_IS     2               /* Interrupt Status */
 159 #define AHCI_HBA_PI     3               /* Ports Implemented */
 160 #define AHCI_HBA_VS     4               /* Version */
 161 #define AHCI_HBA_CAP2   9               /* Host Capabilities Extended */
 162
 163 /* Port constants. */
 164 #define AHCI_PORT_CLB   0               /* Command List Base */
 165 #define AHCI_PORT_CLBU  1               /* Command List Base, Upper 32 bits */
 166 #define AHCI_PORT_FB    2               /* FIS Base */
 167 #define AHCI_PORT_FBU   3               /* FIS Base, Upper 32 bits */
 168 #define AHCI_PORT_IS    4               /* Interrupt Status */
 169 #define         AHCI_PORT_IS_TFES       (1L << 30)      /* Task File Error */
 170 #define         AHCI_PORT_IS_HBFS       (1L << 29)      /* Host Bus Fatal */
 171 #define         AHCI_PORT_IS_HBDS       (1L << 28)      /* Host Bus Data */
 172 #define         AHCI_PORT_IS_IFS        (1L << 27)      /* Interface Fatal */
 173 #define         AHCI_PORT_IS_PRCS       (1L << 22)      /* PhyRdy Change */
 174 #define         AHCI_PORT_IS_PCS        (1L <<  6)      /* Port Conn Change */
 175 #define         AHCI_PORT_IS_SDBS       (1L <<  3)      /* Set Device Bits FIS */
 176 #define         AHCI_PORT_IS_PSS        (1L <<  1)      /* PIO Setup FIS */
 177 #define         AHCI_PORT_IS_DHRS       (1L <<  0)      /* D2H Register FIS */
 178 #define AHCI_PORT_IS_RESTART \
 179         (AHCI_PORT_IS_TFES | AHCI_PORT_IS_HBFS | AHCI_PORT_IS_HBDS | \
 180          AHCI_PORT_IS_IFS)
 181 #define AHCI_PORT_IS_MASK \
 182         (AHCI_PORT_IS_RESTART | AHCI_PORT_IS_PRCS | AHCI_PORT_IS_PCS | \
 183          AHCI_PORT_IS_DHRS | AHCI_PORT_IS_PSS | AHCI_PORT_IS_SDBS)
 184 #define AHCI_PORT_IE    5               /* Interrupt Enable */
 185 #define         AHCI_PORT_IE_MASK       AHCI_PORT_IS_MASK
 186 #define         AHCI_PORT_IE_PRCE       AHCI_PORT_IS_PRCS
 187 #define         AHCI_PORT_IE_PCE        AHCI_PORT_IS_PCS
 188 #define         AHCI_PORT_IE_NONE       0L
 189 #define AHCI_PORT_CMD   6               /* Command and Status */
 190 #define         AHCI_PORT_CMD_CR        (1L << 15)      /* Cmd List Running */
 191 #define         AHCI_PORT_CMD_FR        (1L << 14)      /* FIS Recv Running */
 192 #define         AHCI_PORT_CMD_FRE       (1L <<  4)      /* FIS Recv Enabled */
 193 #define         AHCI_PORT_CMD_SUD       (1L <<  1)      /* Spin-Up Device */
 194 #define         AHCI_PORT_CMD_ST        (1L <<  0)      /* Start */
 195 #define AHCI_PORT_TFD   8               /* Task File Data */
 196 #define         AHCI_PORT_TFD_STS_BSY   (1L << 7)       /* Busy */
 197 #define         AHCI_PORT_TFD_STS_DF    (1L << 5)       /* Device Fault */
 198 #define         AHCI_PORT_TFD_STS_DRQ   (1L << 3)       /* Data Xfer Req'd */
 199 #define         AHCI_PORT_TFD_STS_ERR   (1L << 0)       /* Error */
 200 #define         AHCI_PORT_TFD_STS_INIT  0x7F            /* Initial state */
 201 #define AHCI_PORT_SIG   9               /* Signature */
 202 #define         ATA_SIG_ATA             0x00000101L     /* ATA interface */
 203 #define         ATA_SIG_ATAPI           0xEB140101L     /* ATAPI interface */
 204 #define AHCI_PORT_SSTS  10              /* Serial ATA Status */
 205 #define         AHCI_PORT_SSTS_DET_MASK 0x00000007L     /* Detection Mask */
 206 #define         AHCI_PORT_SSTS_DET_PHY  0x00000003L     /* PHY Comm Establ */
 207 #define AHCI_PORT_SCTL  11              /* Serial ATA Control */
 208 #define         AHCI_PORT_SCTL_DET_INIT 0x00000001L     /* Perform Init Seq */
 209 #define         AHCI_PORT_SCTL_DET_NONE 0x00000000L     /* No Action Req'd */
 210 #define AHCI_PORT_SERR  12              /* Serial ATA Error */
 211 #define         AHCI_PORT_SERR_DIAG_N   (1L << 16)      /* PhyRdy Change */
 212 #define AHCI_PORT_SACT  13              /* Serial ATA Active */
 213 #define AHCI_PORT_CI    14              /* Command Issue */
 214
 215 /* Number of Physical Region Descriptors (PRDs). Must be at least NR_IOREQS+2,
 216  * and at most 1024. There is currently no reason to use more than the minimum.
 217  */
 218 #define NR_PRDS         (NR_IOREQS + 2)
 219
 220 /* Various size constants. */
 221 #define AHCI_MEM_BASE_SIZE      0x100   /* memory-mapped base region size */
 222 #define AHCI_MEM_PORT_SIZE      0x80    /* memory-mapped port region size */
 223
 224 #define AHCI_FIS_SIZE   256             /* size of FIS receive buffer */
 225 #define AHCI_CL_SIZE    1024            /* size of command list buffer */
 226 #define AHCI_TMP_SIZE   ATA_ID_SIZE     /* size of temporary storage buffer */
 227 #define AHCI_TMP_ALIGN  2               /* required alignment for temp buf */
 228 #define AHCI_CT_SIZE    (128 + NR_PRDS * sizeof(u32_t) * 4)
 229                                         /* size of command table buffer */
 230 #define AHCI_CT_ALIGN   128             /* required alignment for CT buffer */
 231
 232 #define MAX_PRD_BYTES   (1L << 22)      /* maximum number of bytes per PRD */
 233 #define MAX_TRANSFER    MAX_PRD_BYTES   /* maximum size of a single transfer */
 234
 235 /* Command Frame Information Structure (FIS). For internal use only;
 236  * the contents of this structure are later converted to an actual FIS.
 237  */
 238 typedef struct {
 239         u8_t cf_cmd;            /* Command */
 240         u8_t cf_feat;           /* Features */
 241         u32_t cf_lba;           /* LBA (24-bit) */
 242         u8_t cf_dev;            /* Device */
 243         u32_t cf_lba_exp;       /* LBA (exp) (24-bit) */
 244         u8_t cf_feat_exp;       /* Features (exp) */
 245         u8_t cf_sec;            /* Sector Count */
 246         u8_t cf_sec_exp;        /* Sector Count (exp) */
 247         u8_t cf_ctl;            /* Control */
 248 } cmd_fis_t;
 249
 250 /* Physical Region Descriptor (PRD). For internal and sys_vumap() use only;
 251  * the contents of this structure are later converted to an actual PRD.
 252  */
 253 typedef struct vumap_phys prd_t;
 254
 255 /* These are from at_wini, as this driver is a drop-in replacement for at_wini.
 256  * Practically speaking this is already the upper limit with 256 minor device
 257  * numbers per driver, even though it means we can only ever expose 8 devices
 258  * out of potentially 32.
 259  */
 260 #define MAX_DRIVES              8
 261 #define NR_MINORS               (MAX_DRIVES * DEV_PER_DRIVE)
 262 #define SUB_PER_DRIVE           (NR_PARTITIONS * NR_PARTITIONS)
 263 #define NR_SUBDEVS              (MAX_DRIVES * SUB_PER_DRIVE)
 264
 265 /* Port states. */
 266 enum {
 267         STATE_NO_PORT,          /* this port is not present */
 268         STATE_SPIN_UP,          /* waiting for device or timeout after reset */
 269         STATE_NO_DEV,           /* no device has been detected on this port */
 270         STATE_WAIT_SIG,         /* waiting for device signature to appear */
 271         STATE_WAIT_ID,          /* waiting for device identification */
 272         STATE_BAD_DEV,          /* an unusable device has been detected */
 273         STATE_GOOD_DEV          /* a usable device has been detected */
 274 };
 275
 276 /* Command results. */
 277 enum {
 278         RESULT_FAILURE,
 279         RESULT_SUCCESS
 280 };
 281
 282 /* Port flags. */
 283 #define FLAG_ATAPI              0x00000001      /* is this an ATAPI device? */
 284 #define FLAG_HAS_MEDIUM         0x00000002      /* is a medium present? */
 285 #define FLAG_USE_DMADIR         0x00000004      /* use ATAPI DMADIR flag? */
 286 #define FLAG_READONLY           0x00000008      /* is the device read-only? */
 287 #define FLAG_BUSY               0x00000010      /* is an operation ongoing? */
 288 #define FLAG_FAILURE            0x00000020      /* did the operation fail? */
 289 #define FLAG_BARRIER            0x00000040      /* no access until unset */
 290 #define FLAG_HAS_WCACHE         0x00000080      /* is a write cache present? */
 291 #define FLAG_HAS_FLUSH          0x00000100      /* is FLUSH CACHE supported? */
 292 #define FLAG_SUSPENDED          0x00000200      /* is the thread suspended? */
 293 #define FLAG_HAS_FUA            0x00000400      /* is WRITE DMA FUA EX sup.? */
 294 #define FLAG_HAS_NCQ            0x00000800      /* is NCQ supported? */
 295 #define FLAG_NCQ_MODE           0x00001000      /* issuing NCQ commands? */
 296
 297 /* Mapping between devices and ports. */
 298 #define NO_PORT         -1      /* this device maps to no port */
 299 #define NO_DEVICE       -1      /* this port maps to no device */
 300
 301 /* Output verbosity levels. */
 302 enum {
 303         V_NONE,         /* no output at all; keep silent */
 304         V_ERR,          /* important error information only (the default) */
 305         V_INFO,         /* general information about the driver and devices */
 306         V_DEV,          /* device details, to help with detection problems */
 307         V_REQ           /* detailed information about requests */
 308 };
 309
 310 #endif /* _AHCI_H */