kernel/arch/i386/include/archconst.h

   1
   2 #ifndef _I386_ACONST_H
   3 #define _I386_ACONST_H 1
   4
   5 #include <machine/interrupt.h>
   6 #include <machine/memory.h>
   7
   8 /* Constants for protected mode. */
   9
  10 /* Table sizes. */
  11 #define IDT_SIZE 256    /* the table is set to it's maximal size */
  12
  13 /* GDT layout (SYSENTER/SYSEXIT compliant) */
  14 #define KERN_CS_INDEX        1
  15 #define KERN_DS_INDEX        2
  16 #define USER_CS_INDEX        3
  17 #define USER_DS_INDEX        4
  18 #define LDT_INDEX            5
  19 #define TSS_INDEX_FIRST      6
  20 #define TSS_INDEX(cpu)       (TSS_INDEX_FIRST + (cpu)) /* per cpu kernel tss */
  21 #define GDT_SIZE             (TSS_INDEX(CONFIG_MAX_CPUS))       /* LDT descriptor */
  22
  23 #define SEG_SELECTOR(i)          ((i)*8)
  24 #define KERN_CS_SELECTOR SEG_SELECTOR(KERN_CS_INDEX)
  25 #define KERN_DS_SELECTOR SEG_SELECTOR(KERN_DS_INDEX)
  26 #define USER_CS_SELECTOR (SEG_SELECTOR(USER_CS_INDEX) | USER_PRIVILEGE)
  27 #define USER_DS_SELECTOR (SEG_SELECTOR(USER_DS_INDEX) | USER_PRIVILEGE)
  28 #define LDT_SELECTOR SEG_SELECTOR(LDT_INDEX)
  29 #define TSS_SELECTOR(cpu)       SEG_SELECTOR(TSS_INDEX(cpu))
  30
  31 #define DESC_SIZE       8
  32
  33 /* Privileges. */
  34 #define INTR_PRIVILEGE       0  /* kernel and interrupt handlers */
  35 #define USER_PRIVILEGE       3  /* servers and user processes */
  36 #define RPL_MASK             0x03       /* bits in selector RPL */
  37
  38 /* 286 hardware constants. */
  39
  40 /* Exception vector numbers. */
  41 #define BOUNDS_VECTOR        5  /* bounds check failed */
  42 #define INVAL_OP_VECTOR      6  /* invalid opcode */
  43 #define COPROC_NOT_VECTOR    7  /* coprocessor not available */
  44 #define DOUBLE_FAULT_VECTOR  8
  45 #define COPROC_SEG_VECTOR    9  /* coprocessor segment overrun */
  46 #define INVAL_TSS_VECTOR    10  /* invalid TSS */
  47 #define SEG_NOT_VECTOR      11  /* segment not present */
  48 #define STACK_FAULT_VECTOR  12  /* stack exception */
  49 #define PROTECTION_VECTOR   13  /* general protection */
  50
  51 /* Selector bits. */
  52 #define TI                0x04  /* table indicator */
  53 #define RPL               0x03  /* requester privilege level */
  54
  55 /* Base and limit sizes and shifts. */
  56 #define BASE_MIDDLE_SHIFT   16  /* shift for base --> base_middle */
  57
  58 /* Access-byte and type-byte bits. */
  59 #define PRESENT           0x80  /* set for descriptor present */
  60 #define DPL               0x60  /* descriptor privilege level mask */
  61 #define DPL_SHIFT            5
  62 #define SEGMENT           0x10  /* set for segment-type descriptors */
  63
  64 /* Access-byte bits. */
  65 #define EXECUTABLE        0x08  /* set for executable segment */
  66 #define CONFORMING        0x04  /* set for conforming segment if executable */
  67 #define EXPAND_DOWN       0x04  /* set for expand-down segment if !executable*/
  68 #define READABLE          0x02  /* set for readable segment if executable */
  69 #define WRITEABLE         0x02  /* set for writeable segment if !executable */
  70 #define TSS_BUSY          0x02  /* set if TSS descriptor is busy */
  71 #define ACCESSED          0x01  /* set if segment accessed */
  72
  73 /* Special descriptor types. */
  74 #define AVL_286_TSS          1  /* available 286 TSS */
  75 #define LDT                  2  /* local descriptor table */
  76 #define BUSY_286_TSS         3  /* set transparently to the software */
  77 #define CALL_286_GATE        4  /* not used */
  78 #define TASK_GATE            5  /* only used by debugger */
  79 #define INT_286_GATE         6  /* interrupt gate, used for all vectors */
  80 #define TRAP_286_GATE        7  /* not used */
  81
  82 #define INT_GATE_TYPE   (INT_286_GATE | DESC_386_BIT)
  83 #define TSS_TYPE        (AVL_286_TSS  | DESC_386_BIT)
  84
  85
  86 /* Extra 386 hardware constants. */
  87
  88 /* Exception vector numbers. */
  89 #define PAGE_FAULT_VECTOR   14
  90 #define COPROC_ERR_VECTOR   16  /* coprocessor error */
  91 #define ALIGNMENT_CHECK_VECTOR  17
  92 #define MACHINE_CHECK_VECTOR    18
  93 #define SIMD_EXCEPTION_VECTOR   19     /* SIMD Floating-Point Exception (#XM) */
  94
  95 /* Descriptor structure offsets. */
  96 #define DESC_GRANULARITY     6  /* to granularity byte */
  97 #define DESC_BASE_HIGH       7  /* to base_high */
  98
  99 /* Type-byte bits. */
 100 #define DESC_386_BIT  0x08 /* 386 types are obtained by ORing with this */
 101                                 /* LDT's and TASK_GATE's don't need it */
 102
 103 /* Base and limit sizes and shifts. */
 104 #define BASE_HIGH_SHIFT     24  /* shift for base --> base_high */
 105 #define BYTE_GRAN_MAX   0xFFFFFL   /* maximum size for byte granular segment */
 106 #define GRANULARITY_SHIFT   16  /* shift for limit --> granularity */
 107 #define OFFSET_HIGH_SHIFT   16  /* shift for (gate) offset --> offset_high */
 108 #define PAGE_GRAN_SHIFT     12  /* extra shift for page granular limits */
 109
 110 /* Granularity byte. */
 111 #define GRANULAR          0x80  /* set for 4K granularilty */
 112 #define DEFAULT           0x40  /* set for 32-bit defaults (executable seg) */
 113 #define BIG               0x40  /* set for "BIG" (expand-down seg) */
 114 #define AVL               0x10  /* 0 for available */
 115 #define LIMIT_HIGH        0x0F  /* mask for high bits of limit */
 116
 117 /* Program stack words and masks. */
 118 #define INIT_PSW      0x0200    /* initial psw */
 119 #define INIT_TASK_PSW 0x1200    /* initial psw for tasks (with IOPL 1) */
 120 #define TRACEBIT      0x0100    /* OR this with psw in proc[] for tracing */
 121 #define SETPSW(rp, new)         /* permits only certain bits to be set */ \
 122         ((rp)->p_reg.psw = ((rp)->p_reg.psw & ~0xCD5) | ((new) & 0xCD5))
 123 #define IF_MASK 0x00000200
 124 #define IOPL_MASK 0x003000
 125
 126 #define INTEL_CPUID_GEN_EBX     0x756e6547 /* ASCII value of "Genu" */
 127 #define INTEL_CPUID_GEN_EDX     0x49656e69 /* ASCII value of "ineI" */
 128 #define INTEL_CPUID_GEN_ECX     0x6c65746e /* ASCII value of "ntel" */
 129
 130 #define AMD_CPUID_GEN_EBX       0x68747541 /* ASCII value of "Auth" */
 131 #define AMD_CPUID_GEN_EDX       0x69746e65 /* ASCII value of "enti" */
 132 #define AMD_CPUID_GEN_ECX       0x444d4163 /* ASCII value of "cAMD" */
 133
 134 #define CPU_VENDOR_INTEL        0
 135 #define CPU_VENDOR_AMD          2
 136 #define CPU_VENDOR_UNKNOWN      0xff
 137
 138 /* fpu context should be saved in 16-byte aligned memory */
 139 #define FPUALIGN                16
 140
 141 /* Poweroff 16-bit code address */
 142 #define BIOS_POWEROFF_ENTRY 0x1000
 143
 144
 145 /*
 146  * defines how many bytes are reserved at the top of the kernel stack for global
 147  * information like currently scheduled process or current cpu id
 148  */
 149 #define X86_STACK_TOP_RESERVED  (2 * sizeof(reg_t))
 150
 151 #define PG_ALLOCATEME ((phys_bytes)-1)
 152
 153 /* MSRs */
 154 #define INTEL_MSR_PERFMON_CRT0         0xc1
 155 #define INTEL_MSR_SYSENTER_CS         0x174
 156 #define INTEL_MSR_SYSENTER_ESP        0x175
 157 #define INTEL_MSR_SYSENTER_EIP        0x176
 158 #define INTEL_MSR_PERFMON_SEL0        0x186
 159
 160 #define INTEL_MSR_PERFMON_SEL0_ENABLE (1 << 22)
 161
 162 #define AMD_EFER_SCE            (1L << 0) /* SYSCALL/SYSRET enabled */
 163 #define AMD_MSR_EFER            0xC0000080      /* extended features msr */
 164 #define AMD_MSR_STAR            0xC0000081      /* SYSCALL params msr */
 165
 166 /* trap styles recorded on kernel entry and exit */
 167 #define KTS_NONE        1 /* invalid */
 168 #define KTS_INT_HARD    2 /* exception / hard interrupt */
 169 #define KTS_INT_ORIG    3 /* soft interrupt from libc */
 170 #define KTS_INT_UM      4 /* soft interrupt from usermapped code */
 171 #define KTS_FULLCONTEXT 5 /* must restore full context */
 172 #define KTS_SYSENTER    6 /* SYSENTER instruction (usermapped) */
 173 #define KTS_SYSCALL     7 /* SYSCALL instruction (usermapped) */
 174
 175 #endif /* _I386_ACONST_H */