drivers/audio/es1370/es1370.c

   1 /* Best viewed with tabsize 4 */
   2
   3 /* Ensoniq ES1370 driver
   4  *
   5  * aka AudioPCI '97
   6  *
   7  * This is the main file of the ES1370 sound driver. There is no main function
   8  * over here, instead the main function is located in the generic dma driver.
   9  * All this driver does is implement the interface audio/audio_fw.h. All
  10  * functions having the prefix 'drv_' are dictated by audio/audio_fw.h. The
  11  * function prototypes you see below define a set of private helper functions.
  12  * Control over the AK4531 codec is delegated ak4531.c.
  13  *
  14  * September 2007    ES1370 driver (Pieter Hijma),
  15  * based on ES1371 driver by Laurens Bronwasser
  16  */
  17
  18 #include <ibm/pci.h>
  19
  20 #include "../framework/audio_fw.h"
  21 #include "es1370.h"
  22 #include "ak4531.h"
  23 #include "pci_helper.h"
  24
  25
  26 /* reg(n) will be the device specific addresses */
  27 #define reg(n) dev.base + n
  28
  29
  30 /* prototypes of private functions */
  31 FORWARD _PROTOTYPE( int detect_hw, (void) );
  32 FORWARD _PROTOTYPE( int disable_int, (int sub_dev) );
  33 FORWARD _PROTOTYPE( int set_stereo, (u32_t stereo, int sub_dev) );
  34 FORWARD _PROTOTYPE( int set_bits, (u32_t nr_of_bits, int sub_dev) );
  35 FORWARD _PROTOTYPE( int set_sample_rate, (u32_t rate, int sub_dev) );
  36 FORWARD _PROTOTYPE( int set_sign, (u32_t val, int sub_dev) );
  37 FORWARD _PROTOTYPE( int get_max_frag_size,
  38                 (u32_t * val, int *len, int sub_dev) );
  39 FORWARD _PROTOTYPE( int set_frag_size, (u32_t fragment_size, int sub_dev) );
  40 FORWARD _PROTOTYPE( int set_int_cnt, (int sub_dev) );
  41 FORWARD _PROTOTYPE( int free_buf, (u32_t *val, int *len, int sub_dev) );
  42 FORWARD _PROTOTYPE( int get_samples_in_buf,
  43                 (u32_t *val, int *len, int sub_dev) );
  44 FORWARD _PROTOTYPE( int get_set_volume, (struct volume_level *level, int *len,
  45                 int sub_dev, int flag) );
  46 FORWARD _PROTOTYPE( int reset, (int sub_dev) );
  47
  48
  49 DEV_STRUCT dev;
  50 aud_sub_dev_conf_t aud_conf[4];
  51
  52
  53 PUBLIC sub_dev_t sub_dev[4];
  54 PUBLIC special_file_t special_file[4];
  55 PUBLIC drv_t drv;
  56
  57
  58 PUBLIC int drv_init(void) {
  59         drv.DriverName = DRIVER_NAME;
  60         drv.NrOfSubDevices = 4;
  61         drv.NrOfSpecialFiles = 4;
  62
  63         sub_dev[DAC1_CHAN].readable = 0;
  64         sub_dev[DAC1_CHAN].writable = 1;
  65         sub_dev[DAC1_CHAN].DmaSize = 64 * 1024;
  66         sub_dev[DAC1_CHAN].NrOfDmaFragments = 2;
  67         sub_dev[DAC1_CHAN].MinFragmentSize = 1024;
  68         sub_dev[DAC1_CHAN].NrOfExtraBuffers = 4;
  69
  70         sub_dev[ADC1_CHAN].readable = 1;
  71         sub_dev[ADC1_CHAN].writable = 0;
  72         sub_dev[ADC1_CHAN].DmaSize = 64 * 1024;
  73         sub_dev[ADC1_CHAN].NrOfDmaFragments = 2;
  74         sub_dev[ADC1_CHAN].MinFragmentSize = 1024;
  75         sub_dev[ADC1_CHAN].NrOfExtraBuffers = 4;
  76
  77         sub_dev[MIXER].writable = 0;
  78         sub_dev[MIXER].readable = 0;
  79
  80         sub_dev[DAC2_CHAN].readable = 0;
  81         sub_dev[DAC2_CHAN].writable = 1;
  82         sub_dev[DAC2_CHAN].DmaSize = 64 * 1024;
  83         sub_dev[DAC2_CHAN].NrOfDmaFragments = 2;
  84         sub_dev[DAC2_CHAN].MinFragmentSize = 1024;
  85         sub_dev[DAC2_CHAN].NrOfExtraBuffers = 4;
  86
  87         special_file[0].minor_dev_nr = 0;
  88         special_file[0].write_chan = DAC1_CHAN;
  89         special_file[0].read_chan = NO_CHANNEL;
  90         special_file[0].io_ctl = DAC1_CHAN;
  91
  92         special_file[1].minor_dev_nr = 1;
  93         special_file[1].write_chan = NO_CHANNEL;
  94         special_file[1].read_chan = ADC1_CHAN;
  95         special_file[1].io_ctl = ADC1_CHAN;
  96
  97         special_file[2].minor_dev_nr = 2;
  98         special_file[2].write_chan = NO_CHANNEL;
  99         special_file[2].read_chan = NO_CHANNEL;
 100         special_file[2].io_ctl = MIXER;
 101
 102         special_file[3].minor_dev_nr = 3;
 103         special_file[3].write_chan = DAC2_CHAN;
 104         special_file[3].read_chan = NO_CHANNEL;
 105         special_file[3].io_ctl = DAC2_CHAN;
 106
 107         return OK;
 108 }
 109
 110
 111 PUBLIC int drv_init_hw (void) {
 112         u16_t i, j;
 113         u16_t chip_sel_ctrl_reg;
 114
 115         /* First, detect the hardware */
 116         if (detect_hw() != OK) {
 117                 return EIO;
 118         }
 119
 120         /* PCI command register
 121          * enable the SERR# driver, PCI bus mastering and I/O access
 122          */
 123         pci_attr_w16 (dev.devind, PCI_CR, SERR_EN|PCI_MASTER|IO_ACCESS);
 124
 125         /* turn everything off */
 126         pci_outl(reg(CHIP_SEL_CTRL),  0x0UL);
 127
 128         /* turn off legacy (legacy control is undocumented) */
 129         pci_outl(reg(LEGACY), 0x0UL);
 130         pci_outl(reg(LEGACY+4), 0x0UL);
 131
 132         /* turn off serial interface */
 133         pci_outl(reg(SERIAL_INTERFACE_CTRL), 0x0UL);
 134         /*pci_outl(reg(SERIAL_INTERFACE_CTRL), 0x3UL);*/
 135
 136
 137         /* enable the codec */
 138         chip_sel_ctrl_reg = pci_inw(reg(CHIP_SEL_CTRL));
 139         chip_sel_ctrl_reg |= XCTL0 | CDC_EN;
 140         pci_outw(reg(CHIP_SEL_CTRL), chip_sel_ctrl_reg);
 141
 142         /* initialize the codec */
 143         if (ak4531_init(reg(CODEC_WRITE_ADDRESS),
 144                                 reg(INTERRUPT_STATUS), CWRIP, reg(0)) < 0) {
 145                 return EINVAL;
 146         }
 147
 148         /* clear all the memory */
 149         for (i = 0; i < 0x10; ++i) {
 150                 pci_outb(reg(MEM_PAGE), i);
 151                 for (j = 0; j < 0x10; j += 4) {
 152                         pci_outl  (reg(MEMORY) + j, 0x0UL);
 153                 }
 154         }
 155
 156         /* initialize variables for each sub_device */
 157         for (i = 0; i < drv.NrOfSubDevices; i++) {
 158                 if(i != MIXER) {
 159                         aud_conf[i].busy = 0;
 160                         aud_conf[i].stereo = DEFAULT_STEREO;
 161                         aud_conf[i].sample_rate = DEFAULT_RATE;
 162                         aud_conf[i].nr_of_bits = DEFAULT_NR_OF_BITS;
 163                         aud_conf[i].sign = DEFAULT_SIGNED;
 164                         aud_conf[i].fragment_size =
 165                                 sub_dev[i].DmaSize / sub_dev[i].NrOfDmaFragments;
 166                 }
 167         }
 168         return OK;
 169 }
 170
 171
 172 PRIVATE int detect_hw(void) {
 173         u32_t device;
 174         int devind;
 175         u16_t v_id, d_id;
 176
 177         /* detect_hw tries to find device and get IRQ and base address
 178            with a little (much) help from the PCI library.
 179            This code is quite device independent and you can copy it.
 180            (just make sure to get the bugs out first)*/
 181
 182         pci_init();
 183         /* get first device and then search through the list */
 184         device = pci_first_dev(&devind, &v_id, &d_id);
 185         while( device > 0 ) {
 186                 /* if we have a match...break */
 187                 if (v_id == VENDOR_ID && d_id == DEVICE_ID) break;
 188                 device = pci_next_dev(&devind, &v_id, &d_id);
 189         }
 190
 191         /* did we find anything? */
 192         if (v_id != VENDOR_ID || d_id != DEVICE_ID) {
 193                 return EIO;
 194         }
 195
 196         pci_reserve(devind);
 197
 198         dev.name = pci_dev_name(v_id, d_id);
 199
 200         /* get base address of our device, ignore least signif. bit
 201            this last bit thing could be device dependent, i don't know */
 202         dev.base = pci_attr_r32(devind, PCI_BAR) & 0xfffffffe;
 203
 204         /* get IRQ */
 205         dev.irq = pci_attr_r8(devind, PCI_ILR);
 206         dev.revision = pci_attr_r8(devind, PCI_REV);
 207         dev.d_id = d_id;
 208         dev.v_id = v_id;
 209         dev.devind = devind; /* pci device identifier */
 210
 211         return OK;
 212 }
 213
 214
 215 PRIVATE int reset(int chan) {
 216         drv_stop(chan);
 217         sub_dev[chan].OutOfData = 1;
 218
 219         return OK;
 220 }
 221
 222
 223 int drv_reset() {
 224         return OK;
 225 }
 226
 227
 228 int drv_start(int sub_dev, int DmaMode) {
 229         u32_t enable_bit, result = 0;
 230
 231         /* Write default values to device in case user failed to configure.
 232            If user did configure properly, everything is written twice.
 233            please raise your hand if you object against to this strategy...*/
 234         result |= set_sample_rate(aud_conf[sub_dev].sample_rate, sub_dev);
 235         result |= set_stereo(aud_conf[sub_dev].stereo, sub_dev);
 236         result |= set_bits(aud_conf[sub_dev].nr_of_bits, sub_dev);
 237         result |= set_sign(aud_conf[sub_dev].sign, sub_dev);
 238
 239         /* set the interrupt count */
 240         result |= set_int_cnt(sub_dev);
 241
 242         if (result) {
 243                 return EIO;
 244         }
 245
 246         /* if device currently paused, resume */
 247         drv_resume(sub_dev);
 248
 249         switch(sub_dev) {
 250                 case ADC1_CHAN: enable_bit = ADC1_EN;break;
 251                 case DAC1_CHAN: enable_bit = DAC1_EN;break;
 252                 case DAC2_CHAN: enable_bit = DAC2_EN;break;
 253                 default: return EINVAL;
 254         }
 255
 256         /* enable interrupts from 'sub device' */
 257         drv_reenable_int(sub_dev);
 258
 259         /* this means play!!! */
 260         pci_outw(reg(CHIP_SEL_CTRL), pci_inw(reg(CHIP_SEL_CTRL)) | enable_bit);
 261
 262         aud_conf[sub_dev].busy = 1;
 263
 264                 return OK;
 265 }
 266
 267
 268 int drv_stop(int sub_dev)
 269 {
 270         u32_t enable_bit;
 271         int status;
 272
 273         switch(sub_dev) {
 274                 case ADC1_CHAN: enable_bit = ADC1_EN;break;
 275                 case DAC1_CHAN: enable_bit = DAC1_EN;break;
 276                 case DAC2_CHAN: enable_bit = DAC2_EN;break;
 277                 default: return EINVAL;
 278         }
 279
 280         /* stop the specified channel */
 281         pci_outw(reg(CHIP_SEL_CTRL),
 282                         pci_inw(reg(CHIP_SEL_CTRL)) & ~enable_bit);
 283         aud_conf[sub_dev].busy = 0;
 284         status = disable_int(sub_dev);
 285
 286         return status;
 287 }
 288
 289
 290 /* all IO-ctl's sent to the upper driver are passed to this function */
 291 int drv_io_ctl(int request, void * val, int * len, int sub_dev) {
 292
 293         int status;
 294
 295         switch(request) {
 296                 case DSPIORATE:
 297                         status = set_sample_rate(*((u32_t *) val), sub_dev); break;
 298                 case DSPIOSTEREO:
 299                         status = set_stereo(*((u32_t *) val), sub_dev); break;
 300                 case DSPIOBITS:
 301                         status = set_bits(*((u32_t *) val), sub_dev); break;
 302                 case DSPIOSIZE:
 303                         status = set_frag_size(*((u32_t *) val), sub_dev); break;
 304                 case DSPIOSIGN:
 305                         status = set_sign(*((u32_t *) val), sub_dev); break;
 306                 case DSPIOMAX:
 307                         status = get_max_frag_size(val, len, sub_dev); break;
 308                 case DSPIORESET:
 309                         status = reset(sub_dev); break;
 310                 case DSPIOFREEBUF:
 311                         status = free_buf(val, len, sub_dev); break;
 312                 case DSPIOSAMPLESINBUF:
 313                         status = get_samples_in_buf(val, len, sub_dev); break;
 314                 case DSPIOPAUSE:
 315                         status = drv_pause(sub_dev); break;
 316                 case DSPIORESUME:
 317                         status = drv_resume(sub_dev); break;
 318                 case MIXIOGETVOLUME:
 319                         status = get_set_volume(val, len, sub_dev, 0); break;
 320                 case MIXIOSETVOLUME:
 321                         status = get_set_volume(val, len, sub_dev, 1); break;
 322                 default:
 323                         status = EINVAL; break;
 324         }
 325
 326         return status;
 327 }
 328
 329
 330 int drv_get_irq(char *irq) {
 331         *irq = dev.irq;
 332         return OK;
 333 }
 334
 335
 336 int drv_get_frag_size(u32_t *frag_size, int sub_dev) {
 337         *frag_size = aud_conf[sub_dev].fragment_size;
 338         return OK;
 339 }
 340
 341
 342 int drv_set_dma(u32_t dma, u32_t length, int chan) {
 343         /* dma length in bytes,
 344            max is 64k long words for es1370 = 256k bytes */
 345         u32_t page, frame_count_reg, dma_add_reg;
 346
 347         switch(chan) {
 348                 case ADC1_CHAN: page = ADC_MEM_PAGE;
 349                                                 frame_count_reg = ADC_BUFFER_SIZE;
 350                                                 dma_add_reg = ADC_PCI_ADDRESS;
 351                                                 break;
 352                 case DAC1_CHAN: page = DAC_MEM_PAGE;
 353                                                 frame_count_reg = DAC1_BUFFER_SIZE;
 354                                                 dma_add_reg = DAC1_PCI_ADDRESS;
 355                                                 break;
 356                 case DAC2_CHAN: page = DAC_MEM_PAGE;
 357                                                 frame_count_reg = DAC2_BUFFER_SIZE;
 358                                                 dma_add_reg = DAC2_PCI_ADDRESS;
 359                                                 break;
 360                 default: return EIO;
 361         }
 362         pci_outb(reg(MEM_PAGE), page);
 363         pci_outl(reg(dma_add_reg), dma);
 364
 365         /* device expects long word count in stead of bytes */
 366         length /= 4;
 367
 368         /* It seems that register _CURRENT_COUNT is overwritten, but this is
 369          * the way to go. The register frame_count_reg is only longword
 370          * addressable.
 371          * It expects length -1
 372          */
 373         pci_outl(reg(frame_count_reg), (u32_t) (length - 1));
 374
 375         return OK;
 376 }
 377
 378
 379 /* return status of the interrupt summary bit */
 380 int drv_int_sum(void) {
 381         return pci_inl(reg(INTERRUPT_STATUS)) & INTR;
 382 }
 383
 384
 385 int drv_int(int sub_dev) {
 386         u32_t int_status;
 387         u32_t bit;
 388
 389         /* return status of interrupt bit of specified channel*/
 390         switch (sub_dev) {
 391                 case DAC1_CHAN:  bit = DAC1; break;
 392                 case DAC2_CHAN:  bit = DAC2; break;
 393                 case ADC1_CHAN:  bit = ADC; break;
 394                 default: return EINVAL;
 395         }
 396
 397         int_status = pci_inl(reg(INTERRUPT_STATUS)) & bit;
 398
 399         return int_status;
 400 }
 401
 402
 403 int drv_reenable_int(int chan) {
 404         u16_t ser_interface, int_en_bit;
 405
 406         switch(chan) {
 407                 case ADC1_CHAN: int_en_bit = R1_INT_EN; break;
 408                 case DAC1_CHAN: int_en_bit = P1_INTR_EN; break;
 409                 case DAC2_CHAN: int_en_bit = P2_INTR_EN; break;
 410                 default: return EINVAL;
 411         }
 412
 413         /* clear and reenable an interrupt */
 414         ser_interface = pci_inw(reg(SERIAL_INTERFACE_CTRL));
 415         pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface & ~int_en_bit);
 416         pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface | int_en_bit);
 417
 418         return OK;
 419 }
 420
 421
 422 int drv_pause(int sub_dev) {
 423         u32_t pause_bit;
 424
 425         disable_int(sub_dev); /* don't send interrupts */
 426
 427         switch(sub_dev) {
 428                 case DAC1_CHAN: pause_bit = P1_PAUSE;break;
 429                 case DAC2_CHAN: pause_bit = P2_PAUSE;break;
 430                 default: return EINVAL;
 431         }
 432
 433         /* pause */
 434         pci_outl(reg(SERIAL_INTERFACE_CTRL),
 435                         pci_inl(reg(SERIAL_INTERFACE_CTRL)) | pause_bit);
 436
 437         return OK;
 438 }
 439
 440
 441 int drv_resume(int sub_dev) {
 442         u32_t pause_bit = 0;
 443
 444         drv_reenable_int(sub_dev); /* enable interrupts */
 445
 446         switch(sub_dev) {
 447                 case DAC1_CHAN: pause_bit = P1_PAUSE;break;
 448                 case DAC2_CHAN: pause_bit = P2_PAUSE;break;
 449                 default: return EINVAL;
 450         }
 451
 452         /* clear pause bit */
 453         pci_outl(reg(SERIAL_INTERFACE_CTRL),
 454                         pci_inl(reg(SERIAL_INTERFACE_CTRL)) & ~pause_bit);
 455
 456         return OK;
 457 }
 458
 459
 460 PRIVATE int set_bits(u32_t nr_of_bits, int sub_dev) {
 461         /* set format bits for specified channel. */
 462         u16_t size_16_bit, ser_interface;
 463
 464         switch(sub_dev) {
 465                 case ADC1_CHAN: size_16_bit = R1_S_EB; break;
 466                 case DAC1_CHAN: size_16_bit = P1_S_EB; break;
 467                 case DAC2_CHAN: size_16_bit = P2_S_EB; break;
 468                 default: return EINVAL;
 469         }
 470
 471         ser_interface = pci_inw(reg(SERIAL_INTERFACE_CTRL));
 472         ser_interface &= ~size_16_bit;
 473         switch(nr_of_bits) {
 474                 case 16: ser_interface |= size_16_bit;break;
 475                 case  8: break;
 476                 default: return EINVAL;
 477         }
 478         pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface);
 479         aud_conf[sub_dev].nr_of_bits = nr_of_bits;
 480         return OK;
 481 }
 482
 483
 484 PRIVATE int set_stereo(u32_t stereo, int sub_dev) {
 485         /* set format bits for specified channel. */
 486         u16_t stereo_bit, ser_interface;
 487
 488         switch(sub_dev) {
 489                 case ADC1_CHAN: stereo_bit = R1_S_MB; break;
 490                 case DAC1_CHAN: stereo_bit = P1_S_MB; break;
 491                 case DAC2_CHAN: stereo_bit = P2_S_MB; break;
 492                 default: return EINVAL;
 493         }
 494         ser_interface = pci_inw(reg(SERIAL_INTERFACE_CTRL));
 495         ser_interface &= ~stereo_bit;
 496         if (stereo) {
 497                 ser_interface |= stereo_bit;
 498         }
 499         pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface);
 500         aud_conf[sub_dev].stereo = stereo;
 501
 502         return OK;
 503 }
 504
 505
 506 PRIVATE int set_sign(u32_t val, int sub_dev) {
 507         return OK;
 508 }
 509
 510
 511 PRIVATE int set_frag_size(u32_t fragment_size, int sub_dev_nr) {
 512         if (fragment_size > (sub_dev[sub_dev_nr].DmaSize /
 513                                 sub_dev[sub_dev_nr].NrOfDmaFragments) ||
 514                         fragment_size < sub_dev[sub_dev_nr].MinFragmentSize) {
 515                 return EINVAL;
 516         }
 517         aud_conf[sub_dev_nr].fragment_size = fragment_size;
 518
 519         return OK;
 520 }
 521
 522
 523 PRIVATE int set_sample_rate(u32_t rate, int sub_dev) {
 524         /* currently only 44.1kHz */
 525         u32_t controlRegister;
 526
 527         if (rate > MAX_RATE || rate < MIN_RATE) {
 528                 return EINVAL;
 529         }
 530
 531         controlRegister = pci_inl(reg(CHIP_SEL_CTRL));
 532         controlRegister |= FREQ_44K100;
 533         pci_outl(reg(CHIP_SEL_CTRL), controlRegister);
 534
 535         aud_conf[sub_dev].sample_rate = rate;
 536
 537         return OK;
 538 }
 539
 540
 541 PRIVATE int set_int_cnt(int chan) {
 542         /* Write interrupt count for specified channel.
 543            After <DspFragmentSize> bytes, an interrupt will be generated  */
 544
 545         int sample_count;
 546         u16_t int_cnt_reg;
 547
 548         if (aud_conf[chan].fragment_size >
 549                         (sub_dev[chan].DmaSize / sub_dev[chan].NrOfDmaFragments)
 550                         || aud_conf[chan].fragment_size < sub_dev[chan].MinFragmentSize) {
 551                 return EINVAL;
 552         }
 553
 554         switch(chan) {
 555                 case ADC1_CHAN: int_cnt_reg = ADC_SAMP_CT; break;
 556                 case DAC1_CHAN: int_cnt_reg = DAC1_SAMP_CT; break;
 557                 case DAC2_CHAN: int_cnt_reg = DAC2_SAMP_CT; break;
 558                 default: return EINVAL;
 559         }
 560
 561         sample_count = aud_conf[chan].fragment_size;
 562
 563         /* adjust sample count according to sample format */
 564         if( aud_conf[chan].stereo == TRUE ) sample_count >>= 1;
 565         switch(aud_conf[chan].nr_of_bits) {
 566                 case 16:   sample_count >>= 1;break;
 567                 case  8:   break;
 568                 default: return EINVAL;
 569         }
 570
 571         /* set the sample count - 1 for the specified channel. */
 572         pci_outw(reg(int_cnt_reg), sample_count - 1);
 573
 574         return OK;
 575 }
 576
 577
 578 PRIVATE int get_max_frag_size(u32_t * val, int * len, int sub_dev_nr) {
 579         *len = sizeof(*val);
 580         *val = (sub_dev[sub_dev_nr].DmaSize /
 581                         sub_dev[sub_dev_nr].NrOfDmaFragments);
 582         return OK;
 583 }
 584
 585
 586 PRIVATE int disable_int(int chan) {
 587         u16_t ser_interface, int_en_bit;
 588
 589         switch(chan) {
 590                 case ADC1_CHAN: int_en_bit = R1_INT_EN; break;
 591                 case DAC1_CHAN: int_en_bit = P1_INTR_EN; break;
 592                 case DAC2_CHAN: int_en_bit = P2_INTR_EN; break;
 593                 default: return EINVAL;
 594         }
 595         /* clear the interrupt */
 596         ser_interface = pci_inw(reg(SERIAL_INTERFACE_CTRL));
 597         pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface & ~int_en_bit);
 598         return OK;
 599 }
 600
 601
 602 PRIVATE int get_samples_in_buf (u32_t *samples_in_buf, int *len, int chan) {
 603         u16_t samp_ct_reg;
 604         u16_t curr_samp_ct_reg;
 605         u16_t samp_ct;  /* nr of samples - 1 that will be played back */
 606         u16_t curr_samp_ct; /* counts back from SAMP_CT till 0 */
 607
 608         *len = sizeof(*samples_in_buf);
 609
 610         switch(chan) {
 611                 case ADC1_CHAN:
 612                         curr_samp_ct_reg = ADC_CURR_SAMP_CT;
 613                         samp_ct_reg = ADC_SAMP_CT; break;
 614                 case DAC1_CHAN:
 615                         curr_samp_ct_reg = DAC1_CURR_SAMP_CT;
 616                         samp_ct_reg = DAC1_SAMP_CT; break;
 617                 case DAC2_CHAN:
 618                         curr_samp_ct_reg = DAC2_CURR_SAMP_CT;
 619                         samp_ct_reg = DAC2_SAMP_CT; break;
 620                 default: return EINVAL;
 621         }
 622
 623         samp_ct = pci_inw(reg(samp_ct_reg));
 624         curr_samp_ct = pci_inw(reg(curr_samp_ct_reg));
 625
 626         *samples_in_buf = (u32_t) (sub_dev[chan].BufLength * 8192) +
 627                 curr_samp_ct;
 628
 629         return OK;
 630 }
 631
 632
 633 /* returns 1 if there are free buffers */
 634 PRIVATE int free_buf (u32_t *val, int *len, int sub_dev_nr) {
 635         *len = sizeof(*val);
 636         if (sub_dev[sub_dev_nr].BufLength ==
 637                         sub_dev[sub_dev_nr].NrOfExtraBuffers) {
 638                 *val = 0;
 639         }
 640         else {
 641                 *val = 1;
 642         }
 643         return OK;
 644 }
 645
 646
 647 PRIVATE int get_set_volume(struct volume_level *level, int *len, int sub_dev,
 648                 int flag) {
 649         *len = sizeof(struct volume_level);
 650         if (sub_dev == MIXER) {
 651                 return ak4531_get_set_volume(level, flag);
 652         }
 653         else {
 654                 return EINVAL;
 655         }
 656 }