drivers/audio/es1370/es1370.h

   1 #ifndef ES1370_H
   2 #define ES1370_H
   3 /* best viewed with tabsize=4 */
   4
   5 #include <sys/types.h>
   6 #include "../../drivers.h"
   7 #include <sys/ioc_sound.h>
   8
   9
  10 /* set your vendor and device ID's here */
  11 #define VENDOR_ID                               0x1274
  12 #define DEVICE_ID                               0x5000
  13 #define DRIVER_NAME                             "ES1370"
  14
  15
  16 /* channels or subdevices */
  17 #define DAC1_CHAN                               0
  18 #define ADC1_CHAN                               1
  19 #define MIXER                                   2
  20 #define DAC2_CHAN                               3
  21
  22
  23 /* PCI command register defines */
  24 #define SERR_EN                                 0x0100
  25 #define PCI_MASTER                              0x0004
  26 #define IO_ACCESS                               0x0001
  27
  28
  29 /* Interrupt/Chip Select Control */
  30 #define CHIP_SEL_CTRL                   0x00
  31 #define FREQ_44K100                             0x3000          /* 44.1 Khz */
  32 #define CDC_EN                                  0x0002          /* codec enable */
  33 #define ADC1_EN                                 0x0010
  34 #define DAC1_EN                                 0x0040
  35 #define DAC2_EN                                 0x0020
  36 #define XCTL0                                   0x0100
  37 #define CCB_INTRM                               0x0400
  38
  39
  40 /* Interrupt/Chip Select Status */
  41 #define INTERRUPT_STATUS                0x04
  42 #define ADC                                             0x0001
  43 #define DAC2                                    0x0002
  44 #define DAC1                                    0x0004
  45 #define CSTAT                                   0x0400          /* == CBUSY || CWRIP */
  46 #define CWRIP                                   0x0100          /* == CBUSY || CWRIP */
  47 #define INTR                                    0x80000000
  48
  49
  50 /* AK4531 address */
  51 #define CODEC_WRITE_ADDRESS             0x10
  52
  53
  54 /* Legacy address */
  55 #define LEGACY                                  0x18
  56
  57
  58 /* Memory related defines */
  59 #define MEM_PAGE                                0x0c
  60 #define ADC_MEM_PAGE                    0x0d
  61 #define DAC_MEM_PAGE                    0x0c            /* for DAC1 and DAC2 */
  62
  63 #define MEMORY                                  0x30
  64 #define ADC_BUFFER_SIZE                 0x34
  65 #define DAC1_BUFFER_SIZE                0x34
  66 #define DAC2_BUFFER_SIZE                0X3c
  67 #define ADC_PCI_ADDRESS                 0x30
  68 #define DAC1_PCI_ADDRESS                0x30
  69 #define DAC2_PCI_ADDRESS                0x38
  70
  71
  72 /* Serial Interface Control */
  73 #define SERIAL_INTERFACE_CTRL   0x20
  74 #define P1_S_MB                                 0x0001          /* DAC1 Stereo/Mono bit */
  75 #define P1_S_EB                                 0x0002          /* DAC1 Sixteen/Eight bit */
  76 #define P2_S_MB                                 0x0004          /* DAC2 Stereo/Mono bit */
  77 #define P2_S_EB                                 0x0008          /* DAC2 Sixteen/Eight bit */
  78 #define R1_S_MB                                 0x0010          /* ADC Stereo/Mono bit */
  79 #define R1_S_EB                                 0x0020          /* ADC Sixteen/Eight bit */
  80 #define P1_INTR_EN                              0x0100
  81 #define P2_INTR_EN                              0x0200
  82 #define R1_INT_EN                               0x0400
  83 #define P1_PAUSE                                0x0800
  84 #define P2_PAUSE                                0x1000
  85
  86
  87 #define DAC1_SAMP_CT                    0x24
  88 #define DAC1_CURR_SAMP_CT               0x26
  89 #define DAC2_SAMP_CT                    0x28
  90 #define DAC2_CURR_SAMP_CT               0x2a
  91 #define ADC_SAMP_CT                             0x2c
  92 #define ADC_CURR_SAMP_CT                0x2e
  93
  94
  95 typedef struct {
  96         u32_t stereo;
  97         u16_t sample_rate;
  98         u32_t nr_of_bits;
  99         u32_t sign;
 100         u32_t busy;
 101         u32_t fragment_size;
 102 } aud_sub_dev_conf_t;
 103
 104 /* Some defaults for the aud_sub_dev_conf_t*/
 105 #define DEFAULT_RATE                44100      /* Sample rate */
 106 #define DEFAULT_NR_OF_BITS              16             /* Nr. of bits per sample per chan */
 107 #define DEFAULT_SIGNED                  0          /* 0 = unsigned, 1 = signed */
 108 #define DEFAULT_STEREO                  1          /* 0 = mono, 1 = stereo */
 109 #define MAX_RATE                                44100      /* Max sample speed in KHz */
 110 #define MIN_RATE                                4000       /* Min sample speed in KHz */
 111
 112
 113 typedef struct DEVSTRUCT {
 114         char*     name;
 115         u16_t     v_id;                                                 /* vendor id */
 116         u16_t     d_id;                                                 /* device id */
 117         u32_t     devind;                                               /* minix pci device id, for
 118                                                                                          * pci configuration space */
 119         u32_t     base;                                                 /* changed to 32 bits */
 120         char      irq;
 121         char      revision;                                             /* version of the device */
 122 } DEV_STRUCT;
 123
 124
 125 #endif /* ES1370_H */