drivers/lance/lance.h

   1 #include <net/gen/ether.h>
   2 #include <net/gen/eth_io.h>
   3
   4 /* PCI STUFF */
   5 #define PCI_BASE_ADDRESS_0              0x10
   6 #define PCI_BASE_ADDRESS_1              0x14
   7 #define PCI_BASE_ADDRESS_2              0x18
   8 #define PCI_BASE_ADDRESS_3              0x1c
   9 #define PCI_BASE_ADDRESS_4              0x20
  10 #define PCI_BASE_ADDRESS_5              0x24
  11
  12 #define PCI_BASE_ADDRESS_IO_MASK        (~0x03)
  13 #define PCI_BASE_ADDRESS_SPACE_IO       0x01
  14 #define PCI_INTERRUPT_LINE              0x3c
  15 #define PCI_INTERRUPT_PIN               0x3d
  16
  17 #define PCI_COMMAND_MASTER              0x4
  18
  19 #define PCI_VENDOR_ID_AMD       0x1022
  20 #define PCI_DEVICE_ID_AMD_LANCE 0x2000
  21
  22
  23 /* supported max number of ether cards */
  24 #define EC_PORT_NR_MAX 2
  25
  26 /* macros for 'mode' */
  27 #define EC_DISABLED    0x0
  28 #define EC_SINK        0x1
  29 #define EC_ENABLED     0x2
  30
  31 /* macros for 'flags' */
  32 #define ECF_EMPTY       0x000
  33 #define ECF_PACK_SEND   0x001
  34 #define ECF_PACK_RECV   0x002
  35 #define ECF_SEND_AVAIL  0x004
  36 #define ECF_READING     0x010
  37 #define ECF_PROMISC     0x040
  38 #define ECF_MULTI       0x080
  39 #define ECF_BROAD       0x100
  40 #define ECF_ENABLED     0x200
  41 #define ECF_STOPPED     0x400
  42
  43 /* === macros for ether cards (our generalized version) === */
  44 #define EC_ISR_RINT     0x0001
  45 #define EC_ISR_WINT     0x0002
  46 #define EC_ISR_RERR     0x0010
  47 #define EC_ISR_WERR     0x0020
  48 #define EC_ISR_ERR      0x0040
  49 #define EC_ISR_RST      0x0100
  50
  51 /* IOVEC */
  52 #define IOVEC_NR        16
  53 typedef struct iovec_dat
  54 {
  55   iovec_s_t iod_iovec[IOVEC_NR];
  56   int iod_iovec_s;
  57   int iod_proc_nr;
  58   cp_grant_id_t iod_grant;
  59   vir_bytes iod_iovec_offset;
  60 } iovec_dat_t;
  61
  62 #define ETH0_SELECTOR  0x61
  63 #define ETH1_SELECTOR  0x69
  64
  65 /* ====== ethernet card info. ====== */
  66 typedef struct ether_card
  67 {
  68   /* ####### MINIX style ####### */
  69   char port_name[sizeof("eth_card#n")];
  70   int flags;
  71   int mode;
  72   int transfer_mode;
  73   eth_stat_t eth_stat;
  74   iovec_dat_t read_iovec;
  75   iovec_dat_t write_iovec;
  76   iovec_dat_t tmp_iovec;
  77   vir_bytes write_s;
  78   vir_bytes read_s;
  79   int client;
  80   message sendmsg;
  81
  82   /* ######## device info. ####### */
  83   port_t ec_port;
  84   phys_bytes ec_linmem;
  85   int ec_irq;
  86   int ec_int_pending;
  87   int ec_hook;
  88
  89   int ec_ramsize;
  90   /* PCI */
  91   u8_t ec_pcibus;
  92   u8_t ec_pcidev;
  93   u8_t ec_pcifunc;
  94
  95   /* Addrassing */
  96   u16_t ec_memseg;
  97   vir_bytes ec_memoff;
  98
  99   ether_addr_t mac_address;
 100 } ether_card_t;
 101
 102 #define DEI_DEFAULT    0x8000
 103
 104 /*
 105  * NOTE: Not all the CSRs are defined. Just the ones that were deemed
 106  * necessary or potentially useful.
 107  */
 108
 109 /* Control and Status Register Addresses */
 110 #define LANCE_CSR0   0   /* Controller Status Register */
 111 #define LANCE_CSR1   1   /* Initialization Block Address (Lower) */
 112 #define LANCE_CSR2   2   /* Initialization Block Address (Upper) */
 113 #define LANCE_CSR3   3   /* Interrupt Masks and Deferral Control */
 114 #define LANCE_CSR4   4   /* Test and Features Control */
 115 #define LANCE_CSR5   5   /* Extended Control and Interrupt */
 116 #define LANCE_CSR8   8   /* Logical Address Filter 0 */
 117 #define LANCE_CSR9   9   /* Logical Address Filter 1 */
 118 #define LANCE_CSR10 10   /* Logical Address Filter 2 */
 119 #define LANCE_CSR11 11   /* Logical Address Filter 3 */
 120 #define LANCE_CSR15 15   /* Mode */
 121 #define LANCE_CSR88 88   /* Chip ID Register (Lower) */
 122 #define LANCE_CSR89 89   /* Chip ID Register (Upper) */
 123
 124 /* Control and Status Register 0 (CSR0) */
 125 #define LANCE_CSR0_ERR       0x8000 /* Error Occurred */
 126 #define LANCE_CSR0_BABL      0x4000 /* Transmitter Timeout Error */
 127 #define LANCE_CSR0_CERR      0x2000 /* Collision Error */
 128 #define LANCE_CSR0_MISS      0x1000 /* Missed Frame */
 129 #define LANCE_CSR0_MERR      0x0800 /* Memory Error */
 130 #define LANCE_CSR0_RINT      0x0400 /* Receive Interrupt */
 131 #define LANCE_CSR0_TINT      0x0200 /* Transmit Interrupt */
 132 #define LANCE_CSR0_IDON      0x0100 /* Initialization Done */
 133 #define LANCE_CSR0_INTR      0x0080 /* Interrupt Flag */
 134 #define LANCE_CSR0_IENA      0x0040 /* Interrupt Enable */
 135 #define LANCE_CSR0_RXON      0x0020 /* Receive On */
 136 #define LANCE_CSR0_TXON      0x0010 /* Transmit On */
 137 #define LANCE_CSR0_TDMD      0x0008 /* Transmit Demand */
 138 #define LANCE_CSR0_STOP      0x0004 /* Stop */
 139 #define LANCE_CSR0_STRT      0x0002 /* Start */
 140 #define LANCE_CSR0_INIT      0x0001 /* Init */
 141
 142 /* Control and Status Register 3 (CSR3) */
 143 /*                           0x8000    Reserved */
 144 #define LANCE_CSR3_BABLM     0x4000 /* Babble Mask */
 145 /*                           0x2000    Reserved */
 146 #define LANCE_CSR3_MISSM     0x1000 /* Missed Frame Mask */
 147 #define LANCE_CSR3_MERRM     0x0800 /* Memory Error Mask */
 148 #define LANCE_CSR3_RINTM     0x0400 /* Receive Interrupt Mask */
 149 #define LANCE_CSR3_TINTM     0x0200 /* Transmit Interrupt Mask */
 150 #define LANCE_CSR3_IDONM     0x0100 /* Initialization Done Mask */
 151 /*                           0x0080    Reserved */
 152 #define LANCE_CSR3_DXSUFLO   0x0040 /* Disable Transmit Stop on Underflow */
 153 #define LANCE_CSR3_LAPPEN    0x0020 /* Look Ahead Packet Processing Enable */
 154 #define LANCE_CSR3_DXMT2PD   0x0010 /* Disable Transmit Two Part Deferral */
 155 #define LANCE_CSR3_EMBA      0x0008 /* Enable Modified Back-off Algorithm */
 156 #define LANCE_CSR3_BSWP      0x0004 /* Byte Swap */
 157 /*                           0x0002    Reserved
 158  *                           0x0001    Reserved */
 159
 160 /* Control and Status Register 4 (CSR4) */
 161 #define LANCE_CSR4_EN124     0x8000 /* Enable CSR124 Access */
 162 #define LANCE_CSR4_DMAPLUS   0x4000 /* Disable DMA Burst Transfer Counter */
 163 #define LANCE_CSR4_TIMER     0x2000 /* Enable Bus Activity Timer */
 164 #define LANCE_CSR4_DPOLL     0x1000 /* Disable Transmit Polling */
 165 #define LANCE_CSR4_APAD_XMT  0x0800 /* Auto Pad Transmit */
 166 #define LANCE_CSR4_ASTRP_RCV 0x0400 /* Auto Strip Receive */
 167 #define LANCE_CSR4_MFCO      0x0200 /* Missed Frame Counter Overflow */
 168 #define LANCE_CSR4_MFCOM     0x0100 /* Missed Frame Counter Overflow Mask */
 169 #define LANCE_CSR4_UINTCMD   0x0080 /* User Interrupt Command */
 170 #define LANCE_CSR4_UINT      0x0040 /* User Interrupt */
 171 #define LANCE_CSR4_RCVCCO    0x0020 /* Receive Collision Counter Overflow */
 172 #define LANCE_CSR4_RCVCCOM   0x0010 /* Receive Collision Counter Overflow
 173                                      * Mask */
 174 #define LANCE_CSR4_TXSTRT    0x0008 /* Transmit Start */
 175 #define LANCE_CSR4_TXSTRTM   0x0004 /* Transmit Start Mask */
 176 #define LANCE_CSR4_JAB       0x0002 /* Jabber Error */
 177 #define LANCE_CSR4_JABM      0x0001 /* Jabber Error Mask */
 178
 179 /* Control and Status Register 5 (CSR5) */
 180 #define LANCE_CSR5_TOKINTD   0x8000 /* Transmit OK Interrupt Disable */
 181 #define LANCE_CSR5_LINTEN    0x4000 /* Last Transmit Interrupt Enable */
 182 /*                           0x2000    Reserved
 183  *                           0x1000    Reserved */
 184 #define LANCE_CSR5_SINT      0x0800 /* System Interrupt */
 185 #define LANCE_CSR5_SINTE     0x0400 /* System Interrupt Enable */
 186 #define LANCE_CSR5_SLPINT    0x0200 /* Sleep Interrupt */
 187 #define LANCE_CSR5_SLPINTE   0x0100 /* Sleep Interrupt Enable */
 188 #define LANCE_CSR5_EXDINT    0x0080 /* Excessive Deferral Interrupt */
 189 #define LANCE_CSR5_EXDINTE   0x0040 /* Excessive Deferral Interrupt Enable */
 190 #define LANCE_CSR5_MPPLBA    0x0020 /* Magic Packet Physical Logical Broadcast
 191                                      * Accept */
 192 #define LANCE_CSR5_MPINT     0x0010 /* Magic Packet Interrupt */
 193 #define LANCE_CSR5_MPINTE    0x0008 /* Magic Packet Interrupt Enable */
 194 #define LANCE_CSR5_MPEN      0x0004 /* Magic Packet Enable */
 195 #define LANCE_CSR5_MPMODE    0x0002 /* Magic Packet Mode */
 196 #define LANCE_CSR5_SPND      0x0001 /* Suspend */
 197
 198 /* Control and Status Register 15 (CSR15) */
 199 #define LANCE_CSR15_PROM     0x8000 /* Promiscuous Mode */
 200 #define LANCE_CSR15_DRCVBC   0x4000 /* Disable Receive Broadcast */
 201 #define LANCE_CSR15_DRCVPA   0x2000 /* Disable Receive Physical Address */
 202 #define LANCE_CSR15_DLNKTST  0x1000 /* Disable Link Status */
 203 #define LANCE_CSR15_DAPC     0x0800 /* Disable Automatic Polarity Correction */
 204 #define LANCE_CSR15_MENDECL  0x0400 /* MENDEC Loopback Mode */
 205 #define LANCE_CSR15_LRT      0x0200 /* Low Receive Threshold (T-MAU Mode) */
 206 #define LANCE_CSR15_TSEL     0x0200 /* Transmit Mode Select  (AUI Mode) */
 207 /*                           0x0100    Portsel[1]
 208  *                           0x0080    Portsel[0] */
 209 #define LANCE_CSR15_INTL     0x0040 /* Internal Loopback */
 210 #define LANCE_CSR15_DRTY     0x0020 /* Disable Retry */
 211 #define LANCE_CSR15_FCOLL    0x0010 /* Force Collision */
 212 #define LANCE_CSR15_DXMTFCS  0x0008 /* Disable Transmit CRC (FCS) */
 213 #define LANCE_CSR15_LOOP     0x0004 /* Loopback Enable */
 214 #define LANCE_CSR15_DTX      0x0002 /* Disable Transmit */
 215 #define LANCE_CSR15_DRX      0x0001 /* Disable Receiver */