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dec21140A ethernet driver for virtualpc, contributed by nicolas tittley.
[minix.git] / drivers / rtl8139 / rtl8139.h
blob218be4b5cb36383ba696fc9ff1b1f7039f23abc3
1 /*
2 ibm/rtl8139.h
3
4 Created: Aug 2003 by Philip Homburg <philip@cs.vu.nl>
5 */
6
7 #include "../drivers.h"
8
9 #include <stdlib.h>
10 #include <stdio.h>
11 #include <string.h>
12 #include <stddef.h>
13 #include <minix/com.h>
14 #include <minix/ds.h>
15 #include <minix/keymap.h>
16 #include <minix/syslib.h>
17 #include <minix/type.h>
18 #include <minix/sysutil.h>
19 #include <minix/endpoint.h>
20 #include <timers.h>
21 #include <net/hton.h>
22 #include <net/gen/ether.h>
23 #include <net/gen/eth_io.h>
24 #include <ibm/pci.h>
25
26 #include <sys/types.h>
27 #include <fcntl.h>
28 #include <assert.h>
29 #include <unistd.h>
30 #include <sys/ioc_memory.h>
31 #include "../../kernel/const.h"
32 #include "../../kernel/config.h"
33 #include "../../kernel/type.h"
34
35 #define RL_IDR 0x00 /* Ethernet address
36 * Note: RL_9346CR_EEM_CONFIG mode is
37 * required the change the ethernet
38 * address.
39 * Note: 4-byte write access only.
40 */
41 #define RL_N_TX 4 /* Number of transmit buffers */
42 #define RL_TSD0 0x010 /* Transmit Status of Descriptor 0 */
43 #define RL_TSD_CRS 0x80000000 /* Carrier Sense Lost */
44 #define RL_TSD_TABT 0x40000000 /* Transmit Abort */
45 #define RL_TSD_OWC 0x20000000 /* Out of Window Collision */
46 #define RL_TSD_CDH 0x10000000 /* CD Heart Beat */
47 #define RL_TSD_NCC_M 0x0F000000 /* Number of Collision Count */
48 #define RL_TSD_RES 0x00C00000 /* Reserved */
49 #define RL_TSD_ERTXTH_M 0x003F0000 /* Early Tx Threshold */
50 #define RL_TSD_ERTXTH_S 16 /* shift */
51 #define RL_TSD_ERTXTH_8 0x00000000 /* 8 bytes */
52 #define RL_TSD_TOK 0x00008000 /* Transmit OK */
53 #define RL_TSD_TUN 0x00004000 /* Transmit FIFO Underrun */
54 #define RL_TSD_OWN 0x00002000 /* Controller (does not) Own Buf. */
55 #define RL_TSD_SIZE 0x00001FFF /* Descriptor Size */
56 #define RL_TSAD0 0x20 /* Transmit Start Address of Descriptor 0 */
57 #define RL_RBSTART 0x30 /* Receive Buffer Start Address */
58 #define RL_CR 0x37 /* Command Register */
59 #define RL_CR_RES0 0xE0 /* Reserved */
60 #define RL_CR_RST 0x10 /* Reset */
61 #define RL_CR_RE 0x08 /* Receiver Enable */
62 #define RL_CR_TE 0x04 /* Transmitter Enable *
63 * Note: start with transmit buffer
64 * 0 after RL_CR_TE has been reset.
65 */
66 #define RL_CR_RES1 0x02 /* Reserved */
67 #define RL_CR_BUFE 0x01 /* Receive Buffer Empty */
68 #define RL_CAPR 0x38 /* Current Address of Packet Read */
69 #define RL_CAPR_DATA_OFF 0x10 /* Packet Starts at Offset */
70 #define RL_CBR 0x3A /* Current Buffer Address */
71 #define RL_IMR 0x3C /* Interrupt Mask Register */
72 #define RL_IMR_SERR 0x8000 /* System Error */
73 #define RL_IMR_TIMEOUT 0x4000 /* Time Out */
74 #define RL_IMR_LENCHG 0x2000 /* Cable Length Change */
75 #define RL_IMR_RES 0x1F80 /* Reserved */
76 #define RL_IMR_FOVW 0x0040 /* Rx FIFO Overflow */
77 #define RL_IMR_PUN 0x0020 /* Packet Underrun / Link Change */
78 #define RL_IMR_RXOVW 0x0010 /* Rx Buffer Overflow */
79 #define RL_IMR_TER 0x0008 /* Transmit Error */
80 #define RL_IMR_TOK 0x0004 /* Transmit OK */
81 #define RL_IMR_RER 0x0002 /* Receive Error */
82 #define RL_IMR_ROK 0x0001 /* Receive OK */
83 #define RL_ISR 0x3E /* Interrupt Status Register */
84 #define RL_ISR_SERR 0x8000 /* System Error */
85 #define RL_ISR_TIMEOUT 0x4000 /* Time Out */
86 #define RL_ISR_LENCHG 0x2000 /* Cable Length Change */
87 #define RL_ISR_RES 0x1F80 /* Reserved */
88 #define RL_ISR_FOVW 0x0040 /* Rx FIFO Overflow */
89 #define RL_ISR_PUN 0x0020 /* Packet Underrun / Link Change */
90 #define RL_ISR_RXOVW 0x0010 /* Rx Buffer Overflow */
91 #define RL_ISR_TER 0x0008 /* Transmit Error */
92 #define RL_ISR_TOK 0x0004 /* Transmit OK */
93 #define RL_ISR_RER 0x0002 /* Receive Error */
94 #define RL_ISR_ROK 0x0001 /* Receive OK */
95 #define RL_TCR 0x40 /* Transmit Configuration Register
96 * Note: RL_CR_TE has to be set to
97 * set/change RL_TCR.
98 */
99 #define RL_TCR_RES0 0x80000000 /* Reserved */
100 #define RL_TCR_HWVER_AM 0x7C000000 /* Hardware Version ID A */
101 #define RL_TCR_IFG_M 0x03000000 /* Interframe Gap Time */
102 #define RL_TCR_IFG_STD 0x03000000 /* IEEE 802.3 std */
103 #if 0
104 #undef RL_TCR_IFG_STD
105 #define RL_TCR_IFG_STD 0x00000000
106 #endif
107 #define RL_TCR_HWVER_BM 0x00C00000 /* Hardware Version ID B */
108 #define RL_TCR_HWVER_RTL8139 0x60000000 /* RTL8139 */
109 #define RL_TCR_HWVER_RTL8139A 0x70000000 /* RTL8139A */
110 #define RL_TCR_HWVER_RTL8139AG 0x74000000 /* RTL8139A-G */
111 #define RL_TCR_HWVER_RTL8139B 0x78000000 /* RTL8139B */
112 #define RL_TCR_HWVER_RTL8130 0x78000000 /* RTL8130 (dup) */
113 #define RL_TCR_HWVER_RTL8139C 0x74000000 /* RTL8139C (dup) */
114 #define RL_TCR_HWVER_RTL8100 0x78800000 /* RTL8100 */
115 #define RL_TCR_HWVER_RTL8100B 0x74400000 /* RTL8100B /
116 RTL8139D */
117 #define RL_TCR_HWVER_RTL8139CP 0x74800000 /* RTL8139C+ */
118 #define RL_TCR_HWVER_RTL8101 0x74C00000 /* RTL8101 */
119 #define RL_TCR_RES1 0x00380000 /* Reserved */
120 #define RL_TCR_LBK_M 0x00060000 /* Loopback Test */
121 #define RL_TCR_LBK_NORMAL 0x00000000 /* Normal */
122 #define RL_TCR_LBK_LOOKBOCK 0x00060000 /* Loopback Mode */
123 #define RL_TCR_CRC 0x00010000 /* (Do not) Append CRC */
124 #define RL_TCR_RES2 0x0000F800 /* Reserved */
125 #define RL_TCR_MXDMA_M 0x00000700 /* Max DMA Burst Size Tx */
126 #define RL_TCR_MXDMA_16 0x00000000 /* 16 bytes */
127 #define RL_TCR_MXDMA_32 0x00000100 /* 32 bytes */
128 #define RL_TCR_MXDMA_64 0x00000200 /* 64 bytes */
129 #define RL_TCR_MXDMA_128 0x00000300 /* 128 bytes */
130 #define RL_TCR_MXDMA_128 0x00000300 /* 128 bytes */
131 #define RL_TCR_MXDMA_256 0x00000400 /* 256 bytes */
132 #define RL_TCR_MXDMA_512 0x00000500 /* 512 bytes */
133 #define RL_TCR_MXDMA_1024 0x00000600 /* 1024 bytes */
134 #define RL_TCR_MXDMA_2048 0x00000700 /* 2048 bytes */
135 #define RL_TCR_TXRR_M 0x000000F0 /* Tx Retry Count */
136 #define RL_TCR_RES3 0x0000000E /* Reserved */
137 #define RL_TCR_CLRABT 0x00000001 /* Clear Abort */
138 #define RL_RCR 0x44 /* Receive Configuration Register
139 * Note: RL_CR_RE has to be set to
140 * set/change RL_RCR.
141 */
142 #define RL_RCR_RES0 0xF0000000 /* Reserved */
143 #define RL_RCR_ERTH_M 0x0F000000 /* Early Rx Threshold */
144 #define RL_RCR_ERTH_0 0x00000000 /* No threshold */
145 #define RL_RCR_ERTH_1 0x01000000 /* 1/16 */
146 #define RL_RCR_ERTH_2 0x02000000 /* 2/16 */
147 #define RL_RCR_ERTH_3 0x03000000 /* 3/16 */
148 #define RL_RCR_ERTH_4 0x04000000 /* 4/16 */
149 #define RL_RCR_ERTH_5 0x05000000 /* 5/16 */
150 #define RL_RCR_ERTH_6 0x06000000 /* 6/16 */
151 #define RL_RCR_ERTH_7 0x07000000 /* 7/16 */
152 #define RL_RCR_ERTH_8 0x08000000 /* 8/16 */
153 #define RL_RCR_ERTH_9 0x09000000 /* 9/16 */
154 #define RL_RCR_ERTH_10 0x0A000000 /* 10/16 */
155 #define RL_RCR_ERTH_11 0x0B000000 /* 11/16 */
156 #define RL_RCR_ERTH_12 0x0C000000 /* 12/16 */
157 #define RL_RCR_ERTH_13 0x0D000000 /* 13/16 */
158 #define RL_RCR_ERTH_14 0x0E000000 /* 14/16 */
159 #define RL_RCR_ERTH_15 0x0F000000 /* 15/16 */
160 #define RL_RCR_RES1 0x00FC0000 /* Reserved */
161 #define RL_RCR_MULERINT 0x00020000 /* Multiple Early Int Select */
162 #define RL_RCR_RER8 0x00010000 /* Receive small error packet */
163 #define RL_RCR_RXFTH_M 0x0000E000 /* Rx FIFO Threshold */
164 #define RL_RCR_RXFTH_16 0x00000000 /* 16 bytes */
165 #define RL_RCR_RXFTH_32 0x00002000 /* 32 bytes */
166 #define RL_RCR_RXFTH_64 0x00004000 /* 64 bytes */
167 #define RL_RCR_RXFTH_128 0x00006000 /* 128 bytes */
168 #define RL_RCR_RXFTH_256 0x00008000 /* 256 bytes */
169 #define RL_RCR_RXFTH_512 0x0000A000 /* 512 bytes */
170 #define RL_RCR_RXFTH_1024 0x0000C000 /* 1024 bytes */
171 #define RL_RCR_RXFTH_UNLIM 0x0000E000 /* unlimited */
172 #define RL_RCR_RBLEM_M 0x00001800 /* Rx Buffer Length */
173 #define RL_RCR_RBLEN_8K 0x00000000 /* 8KB + 16 bytes */
174 #define RL_RCR_RBLEN_8K_SIZE (8*1024)
175 #define RL_RCR_RBLEN_16K 0x00000800 /* 16KB + 16 bytes */
176 #define RL_RCR_RBLEN_16K_SIZE (16*1024)
177 #define RL_RCR_RBLEN_32K 0x00001000 /* 32KB + 16 bytes */
178 #define RL_RCR_RBLEN_32K_SIZE (32*1024)
179 #define RL_RCR_RBLEN_64K 0x00001800 /* 64KB + 16 bytes */
180 #define RL_RCR_RBLEN_64K_SIZE (64*1024)
181 /* Note: the documentation for the RTL8139C(L) or
182 * for the RTL8139D(L) claims that the buffer should
183 * be 16 bytes larger. Multiples of 8KB are the
184 * correct values.
185 */
186 #define RL_RCR_MXDMA_M 0x00000700 /* Rx DMA burst size */
187 #define RL_RCR_MXDMA_16 0x00000000 /* 16 bytes */
188 #define RL_RCR_MXDMA_32 0x00000100 /* 32 bytes */
189 #define RL_RCR_MXDMA_64 0x00000200 /* 64 bytes */
190 #define RL_RCR_MXDMA_128 0x00000300 /* 128 bytes */
191 #define RL_RCR_MXDMA_256 0x00000400 /* 256 bytes */
192 #define RL_RCR_MXDMA_512 0x00000500 /* 512 bytes */
193 #define RL_RCR_MXDMA_1024 0x00000600 /* 1024 bytes */
194 #define RL_RCR_MXDMA_UNLIM 0x00000700 /* unlimited */
195 #define RL_RCR_WRAP 0x00000080 /* (Do not) Wrap on receive */
196 #define RL_RCR_RES2 0x00000040 /* EEPROM type? */
197 #define RL_RCR_AER 0x00000020 /* Accept Error Packets */
198 #define RL_RCR_AR 0x00000010 /* Accept Runt Packets */
199 #define RL_RCR_AB 0x00000008 /* Accept Broadcast Packets */
200 #define RL_RCR_AM 0x00000004 /* Accept Multicast Packets */
201 #define RL_RCR_APM 0x00000002 /* Accept Physical Match Packets */
202 #define RL_RCR_AAP 0x00000001 /* Accept All Packets */
203 #define RL_MPC 0x4c /* Missed Packet Counter */
204 #define RL_9346CR 0x50 /* 93C46 Command Register */
205 #define RL_9346CR_EEM_M 0xC0 /* Operating Mode */
206 #define RL_9346CR_EEM_NORMAL 0x00 /* Normal Mode */
207 #define RL_9346CR_EEM_AUTOLOAD 0x40 /* Load from 93C46 */
208 #define RL_9346CR_EEM_PROG 0x80 /* 93C46 Programming */
209 #define RL_9346CR_EEM_CONFIG 0xC0 /* Config Write Enable */
210 #define RL_9346CR_RES 0x30 /* Reserved */
211 #define RL_9346CR_EECS 0x08 /* EECS Pin */
212 #define RL_9346CR_EESK 0x04 /* EESK Pin */
213 #define RL_9346CR_EEDI 0x02 /* EEDI Pin */
214 #define RL_9346CR_EEDO 0x01 /* EEDO Pin */
215 #define RL_CONFIG0 0x51 /* Configuration Register 0 */
216 #define RL_CONFIG1 0x52 /* Configuration Register 1 */
217 #define RL_MSR 0x58 /* Media Status Register */
218 #define RL_MSR_TXFCE 0x80 /* Tx Flow Control Enable */
219 #define RL_MSR_RXFCE 0x40 /* Rx Flow Control Enable */
220 #define RL_MSR_RES 0x20 /* Reserved */
221 #define RL_MSR_AUXSTAT 0x10 /* Aux. Power Present */
222 #define RL_MSR_SPEED_10 0x08 /* In 10 Mbps mode */
223 #define RL_MSR_LINKB 0x04 /* link Failed */
224 #define RL_MSR_TXPF 0x02 /* Sent Pause Packet */
225 #define RL_MSR_RXPF 0x01 /* Received Pause Packet */
226 #define RL_CONFIG3 0x59 /* Configuration Register 3 */
227 #define RL_CONFIG4 0x5A /* Configuration Register 4 */
228 /* 0x5B */ /* Reserved */
229 #define RL_REVID 0x5E /* PCI Revision ID */
230 /* 0x5F */ /* Reserved */
231 #define RL_TSAD 0x60 /* Transmit Status of All Descriptors */
232 #define RL_TSAD_TOK3 0x8000 /* TOK bit of Descriptor 3 */
233 #define RL_TSAD_TOK2 0x4000 /* TOK bit of Descriptor 2 */
234 #define RL_TSAD_TOK1 0x2000 /* TOK bit of Descriptor 1 */
235 #define RL_TSAD_TOK0 0x1000 /* TOK bit of Descriptor 0 */
236 #define RL_TSAD_TUN3 0x0800 /* TUN bit of Descriptor 3 */
237 #define RL_TSAD_TUN2 0x0400 /* TUN bit of Descriptor 2 */
238 #define RL_TSAD_TUN1 0x0200 /* TUN bit of Descriptor 1 */
239 #define RL_TSAD_TUN0 0x0100 /* TUN bit of Descriptor 0 */
240 #define RL_TSAD_TABT3 0x0080 /* TABT bit of Descriptor 3 */
241 #define RL_TSAD_TABT2 0x0040 /* TABT bit of Descriptor 2 */
242 #define RL_TSAD_TABT1 0x0020 /* TABT bit of Descriptor 1 */
243 #define RL_TSAD_TABT0 0x0010 /* TABT bit of Descriptor 0 */
244 #define RL_TSAD_OWN3 0x0008 /* OWN bit of Descriptor 3 */
245 #define RL_TSAD_OWN2 0x0004 /* OWN bit of Descriptor 2 */
246 #define RL_TSAD_OWN1 0x0002 /* OWN bit of Descriptor 1 */
247 #define RL_TSAD_OWN0 0x0001 /* OWN bit of Descriptor 0 */
248 #define RL_BMCR 0x62 /* Basic Mode Control Register (MII_CTRL) */
249 #define RL_BMSR 0x64 /* Basic Mode Status Register (MII_STATUS) */
250 #define RL_ANAR 0x66 /* Auto-Neg Advertisement Register (MII_ANA) */
251 #define RL_ANLPAR 0x68 /* Auto-Neg Link Partner Register (MII_ANLPA) */
252 #define RL_ANER 0x6a /* Auto-Neg Expansion Register (MII_ANE) */
253 #define RL_NWAYTR 0x70 /* N-way Test Register */
254 #define RL_CSCR 0x74 /* CS Configuration Register */
255 #define RL_CONFIG5 0xD8 /* Configuration Register 5 */
256
257 /* Status word in receive buffer */
258 #define RL_RXS_LEN_M 0xFFFF0000 /* Length Field, Excl. Status word */
259 #define RL_RXS_LEN_S 16 /* Shift For Length */
260 #define RL_RXS_MAR 0x00008000 /* Multicast Address Received */
261 #define RL_RXS_PAR 0x00004000 /* Physical Address Matched */
262 #define RL_RXS_BAR 0x00002000 /* Broadcast Address Received */
263 #define RL_RXS_RES_M 0x00001FC0 /* Reserved */
264 #define RL_RXS_ISE 0x00000020 /* Invalid Symbol Error */
265 #define RL_RXS_RUNT 0x00000010 /* Runt Packet Received */
266 #define RL_RXS_LONG 0x00000008 /* Long (>4KB) Packet */
267 #define RL_RXS_CRC 0x00000004 /* CRC Error */
268 #define RL_RXS_FAE 0x00000002 /* Frame Alignment Error */
269 #define RL_RXS_ROK 0x00000001 /* Receive OK */
270
271 /* Registers in the Machine Independent Interface (MII) to the PHY.
272 * IEEE 802.3 (2000 Edition) Clause 22.
273 */
274 #define MII_CTRL 0x0 /* Control Register (basic) */
275 #define MII_CTRL_RST 0x8000 /* Reset PHY */
276 #define MII_CTRL_LB 0x4000 /* Enable Loopback Mode */
277 #define MII_CTRL_SP_LSB 0x2000 /* Speed Selection (LSB) */
278 #define MII_CTRL_ANE 0x1000 /* Auto Negotiation Enable */
279 #define MII_CTRL_PD 0x0800 /* Power Down */
280 #define MII_CTRL_ISO 0x0400 /* Isolate */
281 #define MII_CTRL_RAN 0x0200 /* Restart Auto-Negotiation Process */
282 #define MII_CTRL_DM 0x0100 /* Full Duplex */
283 #define MII_CTRL_CT 0x0080 /* Enable COL Signal Test */
284 #define MII_CTRL_SP_MSB 0x0040 /* Speed Selection (MSB) */
285 #define MII_CTRL_SP_10 0x0000 /* 10 Mb/s */
286 #define MII_CTRL_SP_100 0x2000 /* 100 Mb/s */
287 #define MII_CTRL_SP_1000 0x0040 /* 1000 Mb/s */
288 #define MII_CTRL_SP_RES 0x2040 /* Reserved */
289 #define MII_CTRL_RES 0x003F /* Reserved */
290 #define MII_STATUS 0x1 /* Status Register (basic) */
291 #define MII_STATUS_100T4 0x8000 /* 100Base-T4 support */
292 #define MII_STATUS_100XFD 0x4000 /* 100Base-X FD support */
293 #define MII_STATUS_100XHD 0x2000 /* 100Base-X HD support */
294 #define MII_STATUS_10FD 0x1000 /* 10 Mb/s FD support */
295 #define MII_STATUS_10HD 0x0800 /* 10 Mb/s HD support */
296 #define MII_STATUS_100T2FD 0x0400 /* 100Base-T2 FD support */
297 #define MII_STATUS_100T2HD 0x0200 /* 100Base-T2 HD support */
298 #define MII_STATUS_EXT_STAT 0x0100 /* Supports MII_EXT_STATUS */
299 #define MII_STATUS_RES 0x0080 /* Reserved */
300 #define MII_STATUS_MFPS 0x0040 /* MF Preamble Suppression */
301 #define MII_STATUS_ANC 0x0020 /* Auto-Negotiation Completed */
302 #define MII_STATUS_RF 0x0010 /* Remote Fault Detected */
303 #define MII_STATUS_ANA 0x0008 /* Auto-Negotiation Ability */
304 #define MII_STATUS_LS 0x0004 /* Link Up */
305 #define MII_STATUS_JD 0x0002 /* Jabber Condition Detected */
306 #define MII_STATUS_EC 0x0001 /* Ext Register Capabilities */
307 #define MII_PHYID_H 0x2 /* PHY ID (high) */
308 #define MII_PHYID_L 0x3 /* PHY ID (low) */
309 #define MII_ANA 0x4 /* Auto-Negotiation Advertisement */
310 #define MII_ANA_NP 0x8000 /* Next PAge */
311 #define MII_ANA_RES 0x4000 /* Reserved */
312 #define MII_ANA_RF 0x2000 /* Remote Fault */
313 #define MII_ANA_TAF_M 0x1FE0 /* Technology Ability Field */
314 #define MII_ANA_TAF_S 5 /* Shift */
315 #define MII_ANA_TAF_RES 0x1000 /* Reserved */
316 #define MII_ANA_PAUSE_ASYM 0x0800 /* Asym. Pause */
317 #define MII_ANA_PAUSE_SYM 0x0400 /* Sym. Pause */
318 #define MII_ANA_100T4 0x0200 /* 100Base-T4 */
319 #define MII_ANA_100TXFD 0x0100 /* 100Base-TX FD */
320 #define MII_ANA_100TXHD 0x0080 /* 100Base-TX HD */
321 #define MII_ANA_10TFD 0x0040 /* 10Base-T FD */
322 #define MII_ANA_10THD 0x0020 /* 10Base-T HD */
323 #define MII_ANA_SEL_M 0x001F /* Selector Field */
324 #define MII_ANA_SEL_802_3 0x0001 /* 802.3 */
325 #define MII_ANLPA 0x5 /* Auto-Neg Link Partner Ability Register */
326 #define MII_ANLPA_NP 0x8000 /* Next Page */
327 #define MII_ANLPA_ACK 0x4000 /* Acknowledge */
328 #define MII_ANLPA_RF 0x2000 /* Remote Fault */
329 #define MII_ANLPA_TAF_M 0x1FC0 /* Technology Ability Field */
330 #define MII_ANLPA_SEL_M 0x001F /* Selector Field */
331 #define MII_ANE 0x6 /* Auto-Negotiation Expansion */
332 #define MII_ANE_RES 0xFFE0 /* Reserved */
333 #define MII_ANE_PDF 0x0010 /* Parallel Detection Fault */
334 #define MII_ANE_LPNPA 0x0008 /* Link Partner is Next Page Able */
335 #define MII_ANE_NPA 0x0002 /* Local Device is Next Page Able */
336 #define MII_ANE_PR 0x0002 /* New Page has been received */
337 #define MII_ANE_LPANA 0x0001 /* Link Partner is Auto-Neg.able */
338 #define MII_ANNPT 0x7 /* Auto-Negotiation Next Page Transmit */
339 #define MII_ANLPRNP 0x8 /* Auto-Neg Link Partner Received Next Page */
340 #define MII_MS_CTRL 0x9 /* MASTER-SLAVE Control Register */
341 #define MII_MS_STATUS 0xA /* MASTER-SLAVE Status Register */
342 /* 0xB ... 0xE */ /* Reserved */
343 #define MII_EXT_STATUS 0xF /* Extended Status */
344 #define MII_ESTAT_1000XFD 0x8000 /* 1000Base-X Full Duplex */
345 #define MII_ESTAT_1000XHD 0x4000 /* 1000Base-X Half Duplex */
346 #define MII_ESTAT_1000TFD 0x2000 /* 1000Base-T Full Duplex */
347 #define MII_ESTAT_1000THD 0x1000 /* 1000Base-T Half Duplex */
348 #define MII_ESTAT_RES 0x0FFF /* Reserved */
349 /* 0x10 ... 0x1F */ /* Vendor Specific */
350
351 #if 0
352 34-35 R ERBCR Early Receive (Rx) Byte Count Register
353 36 R ERSR Early Rx Status Register
354 7-4 reserved
355 3 R ERGood Early Rx Good packet
356 2 R ERBad Early Rx Bad packet
357 1 R EROVW Early Rx OverWrite
358 0 R EROK Early Rx OK
359 51 R/W CONFIG0 Configuration Register 0
360 7 R SCR Scrambler Mode
361 6 R PCS PCS Mode
362 5 R T10 10 Mbps Mode
363 4-3 R PL[1-0] Select 10 Mbps medium type
364 2-0 R BS[2-0] Select Boot ROM size
365 52 R/W CONFIG1 Configuration Register 1
366 7-6 R/W LEDS[1-0] LED PIN
367 5 R/W DVRLOAD Driver Load
368 4 R/W LWACT LWAKE active mode
369 3 R MEMMAP Memory Mapping
370 2 R IOMAP I/O Mapping
371 1 R/W VPD Set to enable Vital Product Data
372 0 R/W PMEn Power Management Enable
373 59 R/W CONFIG3 Configuration Register 3
374 7 R GNTSel Gnt Select
375 6 R/W PARM_En Parameter Enable
376 5 R/W Magic Magic Packet
377 4 R/W LinkUp Link Up
378 3 reserved
379 2 R CLKRUN_En CLKRUN Enable
380 1 reserved
381 0 R FBtBEn Fast Back to Back Enable
382 5a R/W CONFIG4 Configuration Register 4
383 7 R/W RxFIFOAutoClr Auto Clear the Rx FIFO on overflow
384 6 R/W AnaOff Analog Power Off
385 5 R/W LongWF Long Wake-up Frame
386 4 R/W LWPME LANWAKE vs PMEB
387 3 reserved
388 2 R/W LWPTN LWAKE pattern
389 1 reserved
390 0 R/W PBWakeup Pre-Boot Wakeup
391 5c-5d R/W MULINT Multiple Interrupt Select
392 15-12 reserved
393 11-0 R/W MISR[11-0] Multiple Interrupt Select
394 68-69 R ANLPAR Auto-Negotiation Link Partnet Register
395 15 R NP Next Page bit
396 14 R ACK acknowledge received from link partner
397 13 R/W RF received remote fault detection capability
398 12-11 reserved
399 10 R Pause Flow control is supported
400 9 R T4 100Base-T4 is supported
401 8 R/W TXFD 100Base-TX full duplex is supported
402 7 R/W TX 100Base-TX is supported
403 6 R/W 10FD 10Base-T full duplex is supported
404 5 R/W 10 10Base-T is supported
405 4-0 R/W Selector Binary encoded selector
406 6a-6b R ANER Auto-Negotiation Expansion Register
407 15-5 reserved
408 4 R MLF Multiple link fault occured
409 3 R LP_NP_ABLE Link partner supports Next Page
410 2 R NP_ABLE Local node is able to send add. Next Pages
411 1 R PAGE_RX Link Code Word Page received
412 0 R LP_NW_ABLE Link partner supports NWay auto-negotiation
413 70-71 R/W NWAYTR N-way Test Register
414 15-8 reserved
415 7 R/W NWLPBK NWay loopback mode
416 6-4 reserved
417 3 R ENNWLE LED0 pin indicates linkpulse
418 2 R FLAGABD Auto-neg experienced ability detect state
419 1 R FLAGPDF Auto-neg exp. par. detection fault state
420 0 R FLAGLSC Auto-neg experienced link status check state
421 74-75 R/W CSCR CS Configuration Register
422 15 W Testfun Auto-neg speeds up internal timer
423 14-10 reserved
424 9 R/W LD Active low TPI link disable signal
425 8 R/W HEARTBEAT HEART BEAT enable
426 7 R/W JBEN Enable jabber function
427 6 R/W F_LINK_100 Force 100 Mbps
428 5 R/W F_Conect Bypass disconnect function
429 4 reserved
430 3 R Con_status Connected link detected
431 2 R/W Con_status_En Configures LED1 to indicate conn. stat.
432 1 reserved
433 0 R/W PASS_SCR Bypass scramble
434 76-77 reserved
435 78-7b R/W PHY1_PARM PHY parameter 1
436 7c-7f R/W TW_PARM Twister parameter
437 80 R/W PHY2_PARM PHY parameter 2
438 81-83 reserved
439 84-8b R/W CRC[0-7] Power Management CRC reg.[0-7] for frame[0-7]
440 8c-cb R/W Wakeup[0-7] Power Management wakeup frame[0-7] (64 bit)
441 cc-d3 R/W LSBCRC[0-7] LSB of the mask byte of makeup frame[0-7]
442 d4-d7 reserved
443 d8 R/W Config5 Configuration register 5
444 7 reserved
445 6 R/W BWF Broadcast Wakeup Frame
446 5 R/W MWF Multicast Wakeup Frame
447 4 R/W UWF Unicast Wakeup Frame
448 3 R/W FifoAddrPtr FIFO Address Pointer
449 2 R/W LDPS Link Down Power Saving mode
450 1 R/W LANWake LANWake Signal
451 0 R/W PME_STS PME_Status bit
452 d9-ff reserved
453 #endif
454
455 #define tmra_ut timer_t
456 #define tmra_inittimer(tp) tmr_inittimer(tp)
457 #define Proc_number(p) proc_number(p)
458 #define debug 0
459 #define printW() ((void)0)
460 #define vm_1phys2bus(p) (p)
461
462 #define VERBOSE 1 /* display message during init */
463
464 #define RX_BUFSIZE RL_RCR_RBLEN_64K_SIZE
465 #define RX_BUFBITS RL_RCR_RBLEN_64K
466 #define N_TX_BUF RL_N_TX
467
468 #define RE_PORT_NR 1 /* Minix */
469
470 /* I/O vectors are handled IOVEC_NR entries at a time. */
471 #define IOVEC_NR 16
472
473 /* Configuration */
474 #define RL_ENVVAR "RTLETH"
475
476 typedef struct re
477 {
478 port_t re_base_port;
479 int re_irq;
480 int re_mode;
481 int re_flags;
482 int re_client;
483 int re_link_up;
484 int re_got_int;
485 int re_send_int;
486 int re_report_link;
487 int re_clear_rx;
488 int re_need_reset;
489 int re_tx_alive;
490 char *re_model;
491
492 /* Rx */
493 phys_bytes re_rx_buf;
494 char *v_re_rx_buf;
495 vir_bytes re_read_s;
496
497 /* Tx */
498 int re_tx_head;
499 int re_tx_tail;
500 struct
501 {
502 int ret_busy;
503 phys_bytes ret_buf;
504 char * v_ret_buf;
505 } re_tx[N_TX_BUF];
506 u32_t re_ertxth; /* Early Tx Threshold */
507
508 /* PCI related */
509 int re_seen; /* TRUE iff device available */
510 u8_t re_pcibus;
511 u8_t re_pcidev;
512 u8_t re_pcifunc;
513
514 /* 'large' items */
515 int re_hook_id; /* IRQ hook id at kernel */
516 eth_stat_t re_stat;
517 ether_addr_t re_address;
518 message re_rx_mess;
519 message re_tx_mess;
520 char re_name[sizeof("rtl8139#n")];
521 iovec_t re_iovec[IOVEC_NR];
522 iovec_s_t re_iovec_s[IOVEC_NR];
523 }
524 re_t;
525
526 #define REM_DISABLED 0x0
527 #define REM_ENABLED 0x1
528
529 #define REF_PACK_SENT 0x001
530 #define REF_PACK_RECV 0x002
531 #define REF_SEND_AVAIL 0x004
532 #define REF_READING 0x010
533 #define REF_EMPTY 0x000
534 #define REF_PROMISC 0x040
535 #define REF_MULTI 0x080
536 #define REF_BROAD 0x100
537 #define REF_ENABLED 0x200
538
539 /*
540 * $PchId: rtl8139.h,v 1.1 2003/09/05 10:58:50 philip Exp $
541 */
MINIX 3 (repo.or.cz mirror)