1 #include <minix/drivers.h>
2 #include <minix/blockdriver.h>
3 #include <minix/drvlib.h>
5 #define VERBOSE 0 /* display identify messages during boot */
6 #define VERBOSE_DMA 0 /* display DMA debugging information */
7 #define ENABLE_ATAPI 1 /* add ATAPI cd-rom support to driver */
9 #define ATAPI_DEBUG 0 /* To debug ATAPI code. */
11 /* I/O Ports used by winchester disk controllers. */
13 /* Read and write registers */
14 #define REG_CMD_BASE0 0x1F0 /* command base register of controller 0 */
15 #define REG_CMD_BASE1 0x170 /* command base register of controller 1 */
16 #define REG_CTL_BASE0 0x3F6 /* control base register of controller 0 */
17 #define REG_CTL_BASE1 0x376 /* control base register of controller 1 */
19 #define PCI_CTL_OFF 2 /* Offset of control registers from BAR2 */
20 #define PCI_DMA_2ND_OFF 8 /* Offset of DMA registers from BAR4 for
24 #define REG_DATA 0 /* data register (offset from the base reg.) */
25 #define REG_PRECOMP 1 /* start of write precompensation */
26 #define REG_COUNT 2 /* sectors to transfer */
27 #define REG_SECTOR 3 /* sector number */
28 #define REG_CYL_LO 4 /* low byte of cylinder number */
29 #define REG_CYL_HI 5 /* high byte of cylinder number */
30 #define REG_LDH 6 /* lba, drive and head */
31 #define LDH_DEFAULT 0xA0 /* ECC enable, 512 bytes per sector */
32 #define LDH_LBA 0x40 /* Use LBA addressing */
33 #define LDH_DEV 0x10 /* Drive 1 iff set */
34 #define ldh_init(drive) (LDH_DEFAULT | ((drive) << 4))
36 /* Read only registers */
37 #define REG_STATUS 7 /* status */
38 #define STATUS_BSY 0x80 /* controller busy */
39 #define STATUS_RDY 0x40 /* drive ready */
40 #define STATUS_WF 0x20 /* write fault */
41 #define STATUS_SC 0x10 /* seek complete (obsolete) */
42 #define STATUS_DRQ 0x08 /* data transfer request */
43 #define STATUS_CRD 0x04 /* corrected data */
44 #define STATUS_IDX 0x02 /* index pulse */
45 #define STATUS_ERR 0x01 /* error */
46 #define STATUS_ADMBSY 0x100 /* administratively busy (software) */
47 #define REG_ERROR 1 /* error code */
48 #define ERROR_BB 0x80 /* bad block */
49 #define ERROR_ECC 0x40 /* bad ecc bytes */
50 #define ERROR_ID 0x10 /* id not found */
51 #define ERROR_AC 0x04 /* aborted command */
52 #define ERROR_TK 0x02 /* track zero error */
53 #define ERROR_DM 0x01 /* no data address mark */
55 /* Write only registers */
56 #define REG_COMMAND 7 /* command */
57 #define CMD_IDLE 0x00 /* for w_command: drive idle */
58 #define CMD_RECALIBRATE 0x10 /* recalibrate drive */
59 #define CMD_READ 0x20 /* read data */
60 #define CMD_READ_EXT 0x24 /* read data (LBA48 addressed) */
61 #define CMD_READ_DMA_EXT 0x25 /* read data using DMA (w/ LBA48) */
62 #define CMD_WRITE 0x30 /* write data */
63 #define CMD_WRITE_EXT 0x34 /* write data (LBA48 addressed) */
64 #define CMD_WRITE_DMA_EXT 0x35 /* write data using DMA (w/ LBA48) */
65 #define CMD_READVERIFY 0x40 /* read verify */
66 #define CMD_FORMAT 0x50 /* format track */
67 #define CMD_SEEK 0x70 /* seek cylinder */
68 #define CMD_DIAG 0x90 /* execute device diagnostics */
69 #define CMD_SPECIFY 0x91 /* specify parameters */
70 #define CMD_READ_DMA 0xC8 /* read data using DMA */
71 #define CMD_WRITE_DMA 0xCA /* write data using DMA */
72 #define CMD_FLUSH_CACHE 0xE7 /* flush the write cache */
73 #define ATA_IDENTIFY 0xEC /* identify drive */
74 /* #define REG_CTL 0x206 */ /* control register */
75 #define REG_CTL 0 /* control register */
76 #define CTL_NORETRY 0x80 /* disable access retry */
77 #define CTL_NOECC 0x40 /* disable ecc retry */
78 #define CTL_EIGHTHEADS 0x08 /* more than eight heads */
79 #define CTL_RESET 0x04 /* reset controller */
80 #define CTL_INTDISABLE 0x02 /* disable interrupts */
81 #define REG_CTL_ALTSTAT 0 /* alternate status register */
84 #define ID_GENERAL 0x00 /* General configuration information */
85 #define ID_GEN_NOT_ATA 0x8000 /* Not an ATA device */
86 #define ID_CAPABILITIES 0x31 /* Capabilities (49)*/
87 #define ID_CAP_LBA 0x0200 /* LBA supported */
88 #define ID_CAP_DMA 0x0100 /* DMA supported */
89 #define ID_FIELD_VALIDITY 0x35 /* Field Validity (53) */
90 #define ID_FV_88 0x04 /* Word 88 is valid (UDMA) */
91 #define ID_MULTIWORD_DMA 0x3f /* Multiword DMA (63) */
92 #define ID_MWDMA_2_SEL 0x0400 /* Mode 2 is selected */
93 #define ID_MWDMA_1_SEL 0x0200 /* Mode 1 is selected */
94 #define ID_MWDMA_0_SEL 0x0100 /* Mode 0 is selected */
95 #define ID_MWDMA_2_SUP 0x0004 /* Mode 2 is supported */
96 #define ID_MWDMA_1_SUP 0x0002 /* Mode 1 is supported */
97 #define ID_MWDMA_0_SUP 0x0001 /* Mode 0 is supported */
98 #define ID_CSS 0x53 /* Command Sets Supported (83) */
99 #define ID_CSS_LBA48 0x0400
100 #define ID_ULTRA_DMA 0x58 /* Ultra DMA (88) */
101 #define ID_UDMA_5_SEL 0x2000 /* Mode 5 is selected */
102 #define ID_UDMA_4_SEL 0x1000 /* Mode 4 is selected */
103 #define ID_UDMA_3_SEL 0x0800 /* Mode 3 is selected */
104 #define ID_UDMA_2_SEL 0x0400 /* Mode 2 is selected */
105 #define ID_UDMA_1_SEL 0x0200 /* Mode 1 is selected */
106 #define ID_UDMA_0_SEL 0x0100 /* Mode 0 is selected */
107 #define ID_UDMA_5_SUP 0x0020 /* Mode 5 is supported */
108 #define ID_UDMA_4_SUP 0x0010 /* Mode 4 is supported */
109 #define ID_UDMA_3_SUP 0x0008 /* Mode 3 is supported */
110 #define ID_UDMA_2_SUP 0x0004 /* Mode 2 is supported */
111 #define ID_UDMA_1_SUP 0x0002 /* Mode 1 is supported */
112 #define ID_UDMA_0_SUP 0x0001 /* Mode 0 is supported */
115 #define DMA_COMMAND 0 /* Command register */
116 #define DMA_CMD_WRITE 0x08 /* PCI bus master writes */
117 #define DMA_CMD_START 0x01 /* Start Bus Master */
118 #define DMA_STATUS 2 /* Status register */
119 #define DMA_ST_D1_DMACAP 0x40 /* Drive 1 is DMA capable */
120 #define DMA_ST_D0_DMACAP 0x20 /* Drive 0 is DMA capable */
121 #define DMA_ST_INT 0x04 /* Interrupt */
122 #define DMA_ST_ERROR 0x02 /* Error */
123 #define DMA_ST_BM_ACTIVE 0x01 /* Bus Master IDE Active */
124 #define DMA_PRDTP 4 /* PRD Table Pointer */
126 /* Check for the presence of LBA48 only on drives that are 'big'. */
127 #define LBA48_CHECK_SIZE 0x0f000000
128 #define LBA_MAX_SIZE 0x0fffffff /* Highest sector size for
133 #define ERROR_SENSE 0xF0 /* sense key mask */
134 #define SENSE_NONE 0x00 /* no sense key */
135 #define SENSE_RECERR 0x10 /* recovered error */
136 #define SENSE_NOTRDY 0x20 /* not ready */
137 #define SENSE_MEDERR 0x30 /* medium error */
138 #define SENSE_HRDERR 0x40 /* hardware error */
139 #define SENSE_ILRQST 0x50 /* illegal request */
140 #define SENSE_UATTN 0x60 /* unit attention */
141 #define SENSE_DPROT 0x70 /* data protect */
142 #define SENSE_ABRT 0xb0 /* aborted command */
143 #define SENSE_MISCOM 0xe0 /* miscompare */
144 #define ERROR_MCR 0x08 /* media change requested */
145 #define ERROR_ABRT 0x04 /* aborted command */
146 #define ERROR_EOM 0x02 /* end of media detected */
147 #define ERROR_ILI 0x01 /* illegal length indication */
148 #define REG_FEAT 1 /* features */
149 #define FEAT_OVERLAP 0x02 /* overlap */
150 #define FEAT_DMA 0x01 /* dma */
151 #define REG_IRR 2 /* interrupt reason register */
152 #define IRR_REL 0x04 /* release */
153 #define IRR_IO 0x02 /* direction for xfer */
154 #define IRR_COD 0x01 /* command or data */
156 #define REG_CNT_LO 4 /* low byte of cylinder number */
157 #define REG_CNT_HI 5 /* high byte of cylinder number */
158 #define REG_DRIVE 6 /* drive select */
161 #define REG_STATUS 7 /* status */
162 #define STATUS_BSY 0x80 /* controller busy */
163 #define STATUS_DRDY 0x40 /* drive ready */
164 #define STATUS_DMADF 0x20 /* dma ready/drive fault */
165 #define STATUS_SRVCDSC 0x10 /* service or dsc */
166 #define STATUS_DRQ 0x08 /* data transfer request */
167 #define STATUS_CORR 0x04 /* correctable error occurred */
168 #define STATUS_CHECK 0x01 /* check error */
171 #define ATAPI_PACKETCMD 0xA0 /* packet command */
172 #define ATAPI_IDENTIFY 0xA1 /* identify drive */
173 #define SCSI_READ10 0x28 /* read from disk */
174 #define SCSI_SENSE 0x03 /* sense request */
177 /* Interrupt request lines. */
178 #define NO_IRQ 0 /* no IRQ set yet */
180 #define ATAPI_PACKETSIZE 12
181 #define SENSE_PACKETSIZE 18
184 #define ERR (-1) /* general error */
185 #define ERR_BAD_SECTOR (-2) /* block marked bad detected */
187 /* Some controllers don't interrupt, the clock will wake us up. */
188 #define WAKEUP_SECS 32 /* drive may be out for 31 seconds max */
189 #define WAKEUP_TICKS (WAKEUP_SECS*system_hz)
193 #define COMPAT_DRIVES 4
194 #define MAX_SECS 256 /* controller can transfer this many sectors */
195 #define MAX_ERRORS 4 /* how often to try rd/wt before quitting */
196 #define NR_MINORS (MAX_DRIVES * DEV_PER_DRIVE)
197 #define SUB_PER_DRIVE (NR_PARTITIONS * NR_PARTITIONS)
198 #define NR_SUBDEVS (MAX_DRIVES * SUB_PER_DRIVE)
199 #define DELAY_USECS 1000 /* controller timeout in microseconds */
200 #define DELAY_TICKS 1 /* controller timeout in ticks */
201 #define DEF_TIMEOUT_USECS 5000000L /* controller timeout in microseconds */
202 #define RECOVERY_USECS 500000 /* controller recovery time in microseconds */
203 #define RECOVERY_TICKS 30 /* controller recovery time in ticks */
204 #define INITIALIZED 0x01 /* drive is initialized */
205 #define DEAF 0x02 /* controller must be reset */
206 #define SMART 0x04 /* drive supports ATA commands */
208 #define ATAPI 0x08 /* it is an ATAPI device */
210 #define ATAPI 0 /* don't bother with ATAPI; optimise out */
212 #define IDENTIFIED 0x10 /* w_identify done successfully */
213 #define IGNORING 0x20 /* w_identify failed once */
215 #define NO_DMA_VAR "ata_no_dma"
217 /* BIOS parameter table layout. */
218 #define bp_cylinders(t) (t[0] | (t[1] << 8))
219 #define bp_heads(t) (t[2])
220 #define bp_precomp(t) (t[5] | (t[6] << 8))
221 #define bp_sectors(t) (t[14])
