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opendir change: refinement
[minix.git] / drivers / atl2 / atl2.c
blob4869317d6324c12b7f583d9ac0d080d017a7c03b
1 /* Attansic/Atheros L2 FastEthernet driver, by D.C. van Moolenbroek */
2
3 /* No documentation is available for this card. The FreeBSD driver is based
4 * heavily on the official Linux driver; this driver is based heavily on both.
5 */
6
7 #include <minix/drivers.h>
8 #include <minix/netdriver.h>
9
10 #include <sys/mman.h>
11 #include <minix/ds.h>
12 #include <minix/vm.h>
13 #include <machine/pci.h>
14 #include <net/gen/ether.h>
15 #include <net/gen/eth_io.h>
16 #include <assert.h>
17
18 #include "atl2.h"
19
20 #define VERBOSE 0 /* Verbose debugging output */
21 #define ATL2_FKEY 1 /* Register Shift+F11 for dumping statistics */
22
23 #if VERBOSE
24 #define ATL2_DEBUG(x) printf x
25 #else
26 #define ATL2_DEBUG(x)
27 #endif
28
29 typedef struct {
30 u32_t hdr;
31 u32_t vtag;
32 u8_t data[ATL2_RXD_SIZE - sizeof(u32_t) * 2];
33 } rxd_t;
34
35 static struct {
36 int devind; /* PCI device index */
37 int irq; /* IRQ number */
38 int hook_id; /* IRQ hook ID */
39 int mode; /* datalink mode */
40 volatile u8_t *base; /* base address of memory-mapped registers */
41 u32_t size; /* size of memory-mapped area */
42 u32_t hwaddr[2]; /* MAC address, in register representation */
43
44 u8_t *txd_base; /* local address of TxD ring buffer base */
45 u32_t *txs_base; /* local address of TxS ring buffer base */
46 u8_t *rxd_base_u; /* unaligned base address of RxD ring buffer */
47 rxd_t *rxd_base; /* local address of RxD ring buffer base */
48
49 int rxd_align; /* alignment offset of RxD ring buffer */
50
51 vir_bytes txd_phys; /* physical address of TxD ring buffer */
52 vir_bytes txs_phys; /* physical address of TxS ring buffer */
53 vir_bytes rxd_phys; /* physical address of RxD ring buffer */
54
55 int txd_tail; /* tail index into TxD, in bytes */
56 int txd_num; /* head-tail offset into TxD, in bytes */
57 int txs_tail; /* tail index into TxS, in elements */
58 int txs_num; /* head-tail offset into TxS, in elements */
59 int rxd_tail; /* tail index into RxD, in elements */
60
61 int flags; /* state flags (ATL2_FLAG_) */
62 message read_msg; /* suspended read request (READ_PEND) */
63 message write_msg; /* suspended write request (WRITE_PEND) */
64 endpoint_t task_endpt; /* requester endpoint (PACK_RCVD|PACK_SENT) */
65 size_t recv_count; /* packet size (PACK_RCVD) */
66
67 eth_stat_t stat; /* statistics */
68 } state;
69
70 #define ATL2_FLAG_RX_AVAIL 0x01 /* packet available for receipt */
71 #define ATL2_FLAG_READ_PEND 0x02 /* read request pending */
72 #define ATL2_FLAG_WRITE_PEND 0x04 /* write request pending */
73 #define ATL2_FLAG_PACK_RCVD 0x08 /* packet received */
74 #define ATL2_FLAG_PACK_SENT 0x10 /* packet transmitted */
75
76 #define ATL2_READ_U8(off) (* (u8_t *) (state.base + (off)))
77 #define ATL2_READ_U16(off) (* (u16_t *) (state.base + (off)))
78 #define ATL2_READ_U32(off) (* (u32_t *) (state.base + (off)))
79 #define ATL2_WRITE_U8(off, val) * (u8_t *) (state.base + (off)) = (val);
80 #define ATL2_WRITE_U16(off, val) * (u16_t *) (state.base + (off)) = (val);
81 #define ATL2_WRITE_U32(off, val) * (u32_t *) (state.base + (off)) = (val);
82
83 #define ATL2_ALIGN_32(n) (((n) + 3) & ~3)
84
85 static iovec_s_t iovec[NR_IOREQS];
86
87 static int instance;
88
89 /*===========================================================================*
90 * atl2_read_vpd *
91 *===========================================================================*/
92 static int atl2_read_vpd(int index, u32_t *res)
93 {
94 /* Read a value from the VPD register area.
95 */
96 u32_t off, val;
97 int i;
98
99 ATL2_WRITE_U32(ATL2_VPD_DATA_REG, 0);
100
101 off = ATL2_VPD_REGBASE + index * sizeof(u32_t);
102
103 ATL2_WRITE_U32(ATL2_VPD_CAP_REG,
104 (off << ATL2_VPD_CAP_ADDR_SHIFT) & ATL2_VPD_CAP_ADDR_MASK);
105
106 for (i = 0; i < ATL2_VPD_NTRIES; i++) {
107 micro_delay(ATL2_VPD_DELAY);
108
109 val = ATL2_READ_U32(ATL2_VPD_CAP_REG);
110 if (val & ATL2_VPD_CAP_DONE)
111 break;
112 }
113
114 if (i == ATL2_VPD_NTRIES) {
115 printf("ATL2: timeout reading EEPROM register %d\n", index);
116 return FALSE;
117 }
118
119 *res = ATL2_READ_U32(ATL2_VPD_DATA_REG);
120 return TRUE;
121 }
122
123 /*===========================================================================*
124 * atl2_get_vpd_hwaddr *
125 *===========================================================================*/
126 static int atl2_get_vpd_hwaddr(void)
127 {
128 /* Read the MAC address from the EEPROM, using the Vital Product Data
129 * register interface.
130 */
131 u32_t key, val;
132 int i, n, found[2];
133
134 /* No idea, copied from FreeBSD which copied it from Linux. */
135 val = ATL2_READ_U32(ATL2_SPICTL_REG);
136 if (val & ATL2_SPICTL_VPD_EN) {
137 val &= ~ATL2_SPICTL_VPD_EN;
138 ATL2_WRITE_U32(ATL2_SPICTL_REG, val);
139 }
140
141 /* Is VPD supported? */
142 #ifdef PCI_CAP_VPD /* FIXME: just a guess at the future name */
143 if (!pci_find_cap(state.devind, PCI_CAP_VPD, &n))
144 return FALSE;
145 #endif
146
147 /* Read out the set of key/value pairs. Look for the two parts that
148 * make up the MAC address.
149 */
150 found[0] = found[1] = FALSE;
151 for (i = 0; i < ATL2_VPD_NREGS; i += 2) {
152 if (!atl2_read_vpd(i, &key))
153 break;
154
155 if ((key & ATL2_VPD_SIG_MASK) != ATL2_VPD_SIG)
156 break;
157
158 key >>= ATL2_VPD_REG_SHIFT;
159
160 if (key != ATL2_HWADDR0_REG && key != ATL2_HWADDR1_REG)
161 continue;
162
163 if (!atl2_read_vpd(i + 1, &val))
164 break;
165
166 n = (key == ATL2_HWADDR1_REG);
167 state.hwaddr[n] = val;
168 found[n] = TRUE;
169
170 if (found[1 - n]) break;
171 }
172
173 return found[0] && found[1];
174 }
175
176 /*===========================================================================*
177 * atl2_get_hwaddr *
178 *===========================================================================*/
179 static void atl2_get_hwaddr(void)
180 {
181 /* Get the MAC address of the card. First try the EEPROM; if that
182 * fails, just use whatever the card was already set to.
183 */
184
185 if (!atl2_get_vpd_hwaddr()) {
186 printf("ATL2: unable to read from VPD\n");
187
188 state.hwaddr[0] = ATL2_READ_U32(ATL2_HWADDR0_REG);
189 state.hwaddr[1] = ATL2_READ_U32(ATL2_HWADDR1_REG) & 0xffff;
190 }
191
192 ATL2_DEBUG(("ATL2: MAC address %04lx%08lx\n",
193 state.hwaddr[1], state.hwaddr[0]));
194 }
195
196 /*===========================================================================*
197 * atl2_read_mdio *
198 *===========================================================================*/
199 static int atl2_read_mdio(int addr, u16_t *res)
200 {
201 /* Read a MII PHY register using MDIO.
202 */
203 u32_t rval;
204 int i;
205
206 rval = ((addr << ATL2_MDIO_ADDR_SHIFT) & ATL2_MDIO_ADDR_MASK) |
207 ATL2_MDIO_START | ATL2_MDIO_READ | ATL2_MDIO_SUP_PREAMBLE |
208 ATL2_MDIO_CLK_25_4;
209
210 ATL2_WRITE_U32(ATL2_MDIO_REG, rval);
211
212 for (i = 0; i < ATL2_MDIO_NTRIES; i++) {
213 micro_delay(ATL2_MDIO_DELAY);
214
215 rval = ATL2_READ_U32(ATL2_MDIO_REG);
216
217 if (!(rval & (ATL2_MDIO_START | ATL2_MDIO_BUSY)))
218 break;
219 }
220
221 if (i == ATL2_MDIO_NTRIES) return FALSE;
222
223 *res = (u16_t) (rval & ATL2_MDIO_DATA_MASK);
224 return TRUE;
225 }
226
227 /*===========================================================================*
228 * atl2_alloc_dma *
229 *===========================================================================*/
230 static int atl2_alloc_dma(void)
231 {
232 /* Allocate DMA ring buffers.
233 */
234
235 state.txd_base = alloc_contig(ATL2_TXD_BUFSIZE,
236 AC_ALIGN4K, &state.txd_phys);
237 state.txs_base = alloc_contig(ATL2_TXS_COUNT * sizeof(u32_t),
238 AC_ALIGN4K, &state.txs_phys);
239
240 /* The data buffer in each RxD descriptor must be 128-byte aligned.
241 * The two Tx buffers merely require a 4-byte start alignment.
242 */
243 state.rxd_align = 128 - offsetof(rxd_t, data);
244 state.rxd_base_u =
245 alloc_contig(state.rxd_align + ATL2_RXD_COUNT * ATL2_RXD_SIZE,
246 AC_ALIGN4K, &state.rxd_phys);
247
248 /* Unlike mmap, alloc_contig returns NULL on failure. */
249 if (!state.txd_base || !state.txs_base || !state.rxd_base_u)
250 return ENOMEM;
251
252 state.rxd_base = (rxd_t *) (state.rxd_base_u + state.rxd_align);
253 state.rxd_phys += state.rxd_align;
254
255 /* Zero out just in case. */
256 memset(state.txd_base, 0, ATL2_TXD_BUFSIZE);
257 memset(state.txs_base, 0, ATL2_TXS_COUNT * sizeof(u32_t));
258 memset(state.rxd_base, 0, ATL2_RXD_COUNT * ATL2_RXD_SIZE);
259
260 return OK;
261 }
262
263 /*===========================================================================*
264 * atl2_stop *
265 *===========================================================================*/
266 static int atl2_stop(void)
267 {
268 /* Stop the device.
269 */
270 u32_t val;
271 int i;
272
273 /* Clear and disable interrupts. */
274 ATL2_WRITE_U32(ATL2_IMR_REG, 0);
275 ATL2_WRITE_U32(ATL2_ISR_REG, 0xffffffff);
276
277 /* Stop Rx/Tx MACs. */
278 val = ATL2_READ_U32(ATL2_MAC_REG);
279 if (val & (ATL2_MAC_RX_EN | ATL2_MAC_TX_EN)) {
280 val &= ~(ATL2_MAC_RX_EN | ATL2_MAC_TX_EN);
281 ATL2_WRITE_U32(ATL2_MAC_REG, val);
282 }
283
284 ATL2_WRITE_U8(ATL2_DMAWRITE_REG, 0);
285 ATL2_WRITE_U8(ATL2_DMAREAD_REG, 0);
286
287 /* Wait until everything is idle. */
288 for (i = 0; i < ATL2_IDLE_NTRIES; i++) {
289 if (ATL2_READ_U32(ATL2_IDLE_REG) == 0)
290 break;
291
292 micro_delay(ATL2_IDLE_DELAY);
293 }
294
295 /* The caller will generally ignore this return value. */
296 return (i < ATL2_IDLE_NTRIES);
297 }
298
299 /*===========================================================================*
300 * atl2_reset *
301 *===========================================================================*/
302 static int atl2_reset(void)
303 {
304 /* Reset the device to a known good state.
305 */
306 u32_t val;
307 int i;
308
309 /* Issue a soft reset, and wait for the device to respond. */
310 ATL2_WRITE_U32(ATL2_MASTER_REG, ATL2_MASTER_SOFT_RESET);
311
312 for (i = 0; i < ATL2_RESET_NTRIES; i++) {
313 val = ATL2_READ_U32(ATL2_MASTER_REG);
314 if (!(val & ATL2_MASTER_SOFT_RESET))
315 break;
316
317 micro_delay(ATL2_RESET_DELAY);
318 }
319
320 if (i == ATL2_RESET_NTRIES)
321 return FALSE;
322
323 /* Wait until everything is idle. */
324 for (i = 0; i < ATL2_IDLE_NTRIES; i++) {
325 if (ATL2_READ_U32(ATL2_IDLE_REG) == 0)
326 break;
327
328 micro_delay(ATL2_IDLE_DELAY);
329 }
330
331 return (i < ATL2_IDLE_NTRIES);
332 }
333
334 /*===========================================================================*
335 * atl2_set_mode *
336 *===========================================================================*/
337 static void atl2_set_mode(void)
338 {
339 /* Reconfigure the device's promiscuity, multicast, and broadcast mode
340 * settings.
341 */
342 u32_t val;
343
344 val = ATL2_READ_U32(ATL2_MAC_REG);
345 val &= ~(ATL2_MAC_PROMISC_EN | ATL2_MAC_MCAST_EN | ATL2_MAC_BCAST_EN);
346
347 if (state.mode & DL_PROMISC_REQ)
348 val |= ATL2_MAC_PROMISC_EN;
349 if (state.mode & DL_MULTI_REQ)
350 val |= ATL2_MAC_MCAST_EN;
351 if (state.mode & DL_BROAD_REQ)
352 val |= ATL2_MAC_BCAST_EN;
353
354 ATL2_WRITE_U32(ATL2_MAC_REG, val);
355 }
356
357 /*===========================================================================*
358 * atl2_setup *
359 *===========================================================================*/
360 static int atl2_setup(void)
361 {
362 /* Set up the device for normal operation.
363 */
364 u32_t val;
365
366 atl2_stop();
367
368 if (!atl2_reset())
369 return FALSE;
370
371 /* Initialize PCIE module. Magic. */
372 ATL2_WRITE_U32(ATL2_LTSSM_TESTMODE_REG, ATL2_LTSSM_TESTMODE_DEFAULT);
373 ATL2_WRITE_U32(ATL2_DLL_TX_CTRL_REG, ATL2_DLL_TX_CTRL_DEFAULT);
374
375 /* Enable PHY. */
376 ATL2_WRITE_U32(ATL2_PHY_ENABLE_REG, ATL2_PHY_ENABLE);
377 micro_delay(1000);
378
379 /* Clear and disable interrupts. */
380 ATL2_WRITE_U32(ATL2_ISR_REG, 0xffffffff);
381
382 /* Set the MAC address. */
383 ATL2_WRITE_U32(ATL2_HWADDR0_REG, state.hwaddr[0]);
384 ATL2_WRITE_U32(ATL2_HWADDR1_REG, state.hwaddr[1]);
385
386 /* Initialize ring buffer addresses and sizes. */
387 ATL2_WRITE_U32(ATL2_DESC_ADDR_HI_REG, 0); /* no 64 bit */
388 ATL2_WRITE_U32(ATL2_TXD_ADDR_LO_REG, state.txd_phys);
389 ATL2_WRITE_U32(ATL2_TXS_ADDR_LO_REG, state.txs_phys);
390 ATL2_WRITE_U32(ATL2_RXD_ADDR_LO_REG, state.rxd_phys);
391
392 ATL2_WRITE_U16(ATL2_RXD_COUNT_REG, ATL2_RXD_COUNT);
393 ATL2_WRITE_U16(ATL2_TXD_BUFSIZE_REG, ATL2_TXD_BUFSIZE / sizeof(u32_t));
394 ATL2_WRITE_U16(ATL2_TXS_COUNT_REG, ATL2_TXS_COUNT);
395
396 /* A whole lot of other initialization copied from Linux/FreeBSD. */
397 ATL2_WRITE_U32(ATL2_IFG_REG, ATL2_IFG_DEFAULT);
398
399 ATL2_WRITE_U32(ATL2_HDPX_REG, ATL2_HDPX_DEFAULT);
400
401 ATL2_WRITE_U16(ATL2_IMT_REG, ATL2_IMT_DEFAULT);
402 val = ATL2_READ_U32(ATL2_MASTER_REG);
403 ATL2_WRITE_U32(ATL2_MASTER_REG, val | ATL2_MASTER_IMT_EN);
404
405 ATL2_WRITE_U16(ATL2_ICT_REG, ATL2_ICT_DEFAULT);
406
407 ATL2_WRITE_U32(ATL2_CUT_THRESH_REG, ATL2_CUT_THRESH_DEFAULT);
408
409 ATL2_WRITE_U16(ATL2_FLOW_THRESH_HI_REG, (ATL2_RXD_COUNT / 8) * 7);
410 ATL2_WRITE_U16(ATL2_FLOW_THRESH_LO_REG, ATL2_RXD_COUNT / 12);
411
412 /* Set MTU. */
413 ATL2_WRITE_U16(ATL2_MTU_REG, ATL2_MTU_DEFAULT);
414
415 /* Reset descriptors, and enable DMA. */
416 state.txd_tail = state.txs_tail = state.rxd_tail = 0;
417 state.txd_num = state.txs_num = 0;
418 state.flags &= ~ATL2_FLAG_RX_AVAIL;
419 ATL2_WRITE_U16(ATL2_TXD_IDX_REG, 0);
420 ATL2_WRITE_U16(ATL2_RXD_IDX_REG, 0);
421
422 ATL2_WRITE_U8(ATL2_DMAREAD_REG, ATL2_DMAREAD_EN);
423 ATL2_WRITE_U8(ATL2_DMAWRITE_REG, ATL2_DMAWRITE_EN);
424
425 /* Did everything go alright? */
426 val = ATL2_READ_U32(ATL2_ISR_REG);
427 if (val & ATL2_ISR_PHY_LINKDOWN) {
428 printf("ATL2: initialization failed\n");
429 return FALSE;
430 }
431
432 /* Clear interrupt status. */
433 ATL2_WRITE_U32(ATL2_ISR_REG, 0x3fffffff);
434 ATL2_WRITE_U32(ATL2_ISR_REG, 0);
435
436 /* Enable interrupts. */
437 ATL2_WRITE_U32(ATL2_IMR_REG, ATL2_IMR_DEFAULT);
438
439 /* Configure MAC. */
440 ATL2_WRITE_U32(ATL2_MAC_REG, ATL2_MAC_DEFAULT);
441
442 /* Inet does not tell us about the multicast addresses that it is
443 * interested in, so we have to simply accept all multicast packets.
444 */
445 ATL2_WRITE_U32(ATL2_MHT0_REG, 0xffffffff);
446 ATL2_WRITE_U32(ATL2_MHT1_REG, 0xffffffff);
447
448 atl2_set_mode();
449
450 /* Enable Tx/Rx. */
451 val = ATL2_READ_U32(ATL2_MAC_REG);
452 ATL2_WRITE_U32(ATL2_MAC_REG, val | ATL2_MAC_TX_EN | ATL2_MAC_RX_EN);
453
454 return TRUE;
455 }
456
457 /*===========================================================================*
458 * atl2_probe *
459 *===========================================================================*/
460 static int atl2_probe(int skip)
461 {
462 /* Find a matching PCI device.
463 */
464 u16_t vid, did;
465 #if VERBOSE
466 char *dname;
467 #endif
468 int r, devind;
469
470 pci_init();
471
472 r = pci_first_dev(&devind, &vid, &did);
473 if (r <= 0)
474 return -1;
475
476 while (skip--) {
477 r = pci_next_dev(&devind, &vid, &did);
478 if (r <= 0)
479 return -1;
480 }
481
482 #if VERBOSE
483 dname = pci_dev_name(vid, did);
484 ATL2_DEBUG(("ATL2: found %s (%x/%x) at %s\n",
485 dname ? dname : "<unknown>", vid, did,
486 pci_slot_name(devind)));
487 #endif
488
489 pci_reserve(devind);
490
491 return devind;
492 }
493
494 /*===========================================================================*
495 * atl2_init *
496 *===========================================================================*/
497 static void atl2_init(int devind)
498 {
499 /* Initialize the device.
500 */
501 u32_t bar;
502 int r, flag;
503
504 /* Initialize global state. */
505 state.devind = devind;
506 state.mode = DL_NOMODE;
507 state.flags = 0;
508 state.recv_count = 0;
509
510 memset(&state.stat, 0, sizeof(state.stat));
511
512 if ((r = pci_get_bar(devind, PCI_BAR, &bar, &state.size, &flag)) != OK)
513 panic("unable to retrieve bar: %d", r);
514
515 if (state.size < ATL2_MIN_MMAP_SIZE || flag)
516 panic("invalid register bar");
517
518 state.base = vm_map_phys(SELF, (void *) bar, state.size);
519 if (state.base == MAP_FAILED)
520 panic("unable to map in registers");
521
522 if ((r = atl2_alloc_dma()) != OK)
523 panic("unable to allocate DMA buffers: %d", r);
524
525 state.irq = pci_attr_r8(devind, PCI_ILR);
526 state.hook_id = 0;
527
528 if ((r = sys_irqsetpolicy(state.irq, 0, &state.hook_id)) != OK)
529 panic("unable to register IRQ: %d", r);
530
531 if (!atl2_reset())
532 panic("unable to reset hardware");
533
534 if ((r = sys_irqenable(&state.hook_id)) != OK)
535 panic("unable to enable IRQ: %d", r);
536
537 atl2_get_hwaddr();
538
539 atl2_setup();
540 }
541
542 /*===========================================================================*
543 * atl2_tx_stat *
544 *===========================================================================*/
545 static void atl2_tx_stat(u32_t stat)
546 {
547 /* Update statistics for packet transmission.
548 */
549
550 if (stat & ATL2_TXS_SUCCESS)
551 state.stat.ets_packetT++;
552 else
553 state.stat.ets_recvErr++;
554
555 if (stat & ATL2_TXS_DEFER)
556 state.stat.ets_transDef++;
557 if (stat & (ATL2_TXS_EXCDEFER | ATL2_TXS_ABORTCOL))
558 state.stat.ets_transAb++;
559 if (stat & ATL2_TXS_SINGLECOL)
560 state.stat.ets_collision++;
561 if (stat & ATL2_TXS_MULTICOL)
562 state.stat.ets_collision++;
563 if (stat & ATL2_TXS_LATECOL)
564 state.stat.ets_OWC++;
565 if (stat & ATL2_TXS_UNDERRUN)
566 state.stat.ets_fifoUnder++;
567 }
568
569 /*===========================================================================*
570 * atl2_rx_stat *
571 *===========================================================================*/
572 static void atl2_rx_stat(u32_t stat)
573 {
574 /* Update statistics for packet receipt.
575 */
576
577 if (stat & ATL2_RXD_SUCCESS)
578 state.stat.ets_packetR++;
579 else
580 state.stat.ets_recvErr++;
581
582 if (stat & ATL2_RXD_CRCERR)
583 state.stat.ets_CRCerr++;
584 if (stat & ATL2_RXD_FRAG)
585 state.stat.ets_collision++;
586 if (stat & ATL2_RXD_TRUNC)
587 state.stat.ets_fifoOver++;
588 if (stat & ATL2_RXD_ALIGN)
589 state.stat.ets_frameAll++;
590 }
591
592 /*===========================================================================*
593 * atl2_tx_advance *
594 *===========================================================================*/
595 static int atl2_tx_advance(void)
596 {
597 /* Advance the TxD/TxS tails by as many sent packets as found.
598 */
599 u32_t stat, size, dsize;
600 int advanced;
601
602 advanced = FALSE;
603
604 while (state.txs_num > 0) {
605 /* Has the tail packet been processed by the driver? */
606 stat = state.txs_base[state.txs_tail];
607
608 if (!(stat & ATL2_TXS_UPDATE))
609 break;
610
611 /* The packet size from the status must match the packet size
612 * we put in. If they don't, there's not much we can do..
613 */
614 size = stat & ATL2_TXS_SIZE_MASK;
615
616 assert((u32_t) state.txd_tail <=
617 ATL2_TXD_BUFSIZE - sizeof(u32_t));
618 dsize = * (u32_t *) (state.txd_base + state.txd_tail);
619 if (size != dsize)
620 printf("ATL2: TxD/TxS size mismatch (%x vs %x)\n",
621 size, dsize);
622
623 /* Advance tails accordingly. */
624 size = sizeof(u32_t) + ATL2_ALIGN_32(dsize);
625 assert((u32_t) state.txd_num >= size);
626 state.txd_tail = (state.txd_tail + size) % ATL2_TXD_BUFSIZE;
627 state.txd_num -= size;
628
629 state.txs_tail = (state.txs_tail + 1) % ATL2_TXS_COUNT;
630 state.txs_num--;
631
632 if (stat & ATL2_TXS_SUCCESS) {
633 ATL2_DEBUG(("ATL2: successfully sent packet\n"));
634 } else {
635 ATL2_DEBUG(("ATL2: failed to send packet\n"));
636 }
637
638 /* Update statistics. */
639 atl2_tx_stat(stat);
640
641 advanced = TRUE;
642 }
643
644 return advanced;
645 }
646
647 /*===========================================================================*
648 * atl2_rx_advance *
649 *===========================================================================*/
650 static void atl2_rx_advance(int next)
651 {
652 /* Advance the RxD tail by as many failed receipts as possible, and
653 * see if there is an actual packet left to receive. If 'next' is set,
654 * the packet at the current tail has been processed.
655 */
656 int update_tail;
657 rxd_t *rxd;
658 u32_t hdr, size;
659
660 update_tail = FALSE;
661
662 if (next) {
663 state.rxd_tail = (state.rxd_tail + 1) % ATL2_RXD_COUNT;
664 update_tail = TRUE;
665
666 ATL2_DEBUG(("ATL2: successfully received packet\n"));
667
668 state.flags &= ~ATL2_FLAG_RX_AVAIL;
669 }
670
671 assert(!(state.flags & ATL2_FLAG_RX_AVAIL));
672
673 for (;;) {
674 /* Check the RxD tail for updates. */
675 rxd = &state.rxd_base[state.rxd_tail];
676
677 hdr = rxd->hdr;
678
679 if (!(hdr & ATL2_RXD_UPDATE))
680 break;
681
682 rxd->hdr = hdr & ~(ATL2_RXD_UPDATE);
683
684 /* Update statistics. */
685 atl2_rx_stat(hdr);
686
687 /* Stop at the first successful receipt. The packet will be
688 * picked up by Inet later.
689 */
690 size = hdr & ATL2_RXD_SIZE_MASK;
691
692 if ((hdr & ATL2_RXD_SUCCESS) && size >= ETH_MIN_PACK_SIZE) {
693 ATL2_DEBUG(("ATL2: packet available, size %ld\n",
694 size));
695
696 state.flags |= ATL2_FLAG_RX_AVAIL;
697 break;
698 }
699
700 ATL2_DEBUG(("ATL2: packet receipt failed\n"));
701
702 /* Advance tail. */
703 state.rxd_tail = (state.rxd_tail + 1) % ATL2_RXD_COUNT;
704 update_tail = TRUE;
705 }
706
707 /* If new RxD descriptors are now up for reuse, tell the device. */
708 if (update_tail) {
709 __insn_barrier();
710
711 ATL2_WRITE_U32(ATL2_RXD_IDX_REG, state.rxd_tail);
712 }
713 }
714
715 /*===========================================================================*
716 * atl2_reply *
717 *===========================================================================*/
718 static void atl2_reply(void)
719 {
720 /* Send a task reply to Inet.
721 */
722 message m;
723 int r, flags;
724
725 flags = DL_NOFLAGS;
726 if (state.flags & ATL2_FLAG_PACK_SENT)
727 flags |= DL_PACK_SEND;
728 if (state.flags & ATL2_FLAG_PACK_RCVD)
729 flags |= DL_PACK_RECV;
730
731 m.m_type = DL_TASK_REPLY;
732 m.DL_FLAGS = flags;
733 m.DL_COUNT = state.recv_count;
734
735 ATL2_DEBUG(("ATL2: sending reply, flags %x count %d\n", flags,
736 m.DL_COUNT));
737
738 if ((r = send(state.task_endpt, &m)) != OK)
739 panic("unable to reply: %d", r);
740
741 state.flags &= ~(ATL2_FLAG_PACK_SENT | ATL2_FLAG_PACK_RCVD);
742 state.recv_count = 0;
743 }
744
745 /*===========================================================================*
746 * atl2_readv *
747 *===========================================================================*/
748 static void atl2_readv(const message *m, int from_int)
749 {
750 /* Read packet data.
751 */
752 rxd_t *rxd;
753 iovec_s_t *iovp;
754 size_t count, off, left, size;
755 u8_t *pos;
756 int i, j, r, batch;
757
758 /* We can deal with only one read request from Inet at a time. */
759 assert(from_int || !(state.flags & ATL2_FLAG_READ_PEND));
760
761 state.task_endpt = m->m_source;
762
763 /* Are there any packets available at all? */
764 if (!(state.flags & ATL2_FLAG_RX_AVAIL))
765 goto suspend;
766
767 /* Get the first available packet's size. Cut off the CRC. */
768 rxd = &state.rxd_base[state.rxd_tail];
769
770 count = rxd->hdr & ATL2_RXD_SIZE_MASK;
771 count -= ETH_CRC_SIZE;
772
773 ATL2_DEBUG(("ATL2: readv: found packet with length %d\n", count));
774
775 /* Copy out the packet. */
776 off = 0;
777 left = count;
778 pos = rxd->data;
779
780 for (i = 0; i < m->DL_COUNT && left > 0; i += batch) {
781 /* Copy in the next batch. */
782 batch = MIN(m->DL_COUNT - i, NR_IOREQS);
783
784 r = sys_safecopyfrom(m->m_source, m->DL_GRANT, off,
785 (vir_bytes) iovec, batch * sizeof(iovec[0]));
786 if (r != OK)
787 panic("vector copy failed: %d", r);
788
789 /* Copy out each element in the batch, until we run out. */
790 for (j = 0, iovp = iovec; j < batch && left > 0; j++, iovp++) {
791 size = MIN(iovp->iov_size, left);
792
793 r = sys_safecopyto(m->m_source, iovp->iov_grant, 0,
794 (vir_bytes) pos, size);
795 if (r != OK)
796 panic("safe copy failed: %d", r);
797
798 pos += size;
799 left -= size;
800 }
801
802 off += batch * sizeof(iovec[0]);
803 }
804
805 /* Not sure what to do here. Inet shouldn't mess this up anyway. */
806 if (left > 0) {
807 printf("ATL2: truncated packet of %d bytes by %d bytes\n",
808 count, left);
809 count -= left;
810 }
811
812 /* We are done with this packet. Move on to the next. */
813 atl2_rx_advance(TRUE /*next*/);
814
815 /* We have now successfully received a packet. */
816 state.flags &= ~ATL2_FLAG_READ_PEND;
817 state.flags |= ATL2_FLAG_PACK_RCVD;
818 state.recv_count = count;
819
820 /* If called from the interrupt handler, the caller will reply. */
821 if (!from_int)
822 atl2_reply();
823
824 return;
825
826 suspend:
827 /* No packets are available at this time. If we were not already
828 * trying to resume receipt, save the read request for later, and tell
829 * Inet that the request has been suspended.
830 */
831 if (from_int)
832 return;
833
834 state.flags |= ATL2_FLAG_READ_PEND;
835 state.read_msg = *m;
836
837 atl2_reply();
838 }
839
840 /*===========================================================================*
841 * atl2_writev *
842 *===========================================================================*/
843 static void atl2_writev(const message *m, int from_int)
844 {
845 /* Write packet data.
846 */
847 iovec_s_t *iovp;
848 size_t off, count, left, pos, skip;
849 vir_bytes size;
850 u8_t *sizep;
851 int i, j, r, batch, maxnum;
852
853 /* We can deal with only one write request from Inet at a time. */
854 assert(from_int || !(state.flags & ATL2_FLAG_WRITE_PEND));
855
856 state.task_endpt = m->m_source;
857
858 /* If we are already certain that the packet won't fit, bail out.
859 * Keep at least some space between TxD head and tail, as it is not
860 * clear whether the device deals well with the case that they collide.
861 */
862 if (state.txs_num >= ATL2_TXS_COUNT)
863 goto suspend;
864 maxnum = ATL2_TXD_BUFSIZE - ETH_MIN_PACK_SIZE - sizeof(u32_t);
865 if (state.txd_num >= maxnum)
866 goto suspend;
867
868 /* Optimistically try to copy in the data; suspend if it turns out
869 * that it does not fit.
870 */
871 off = 0;
872 count = 0;
873 left = state.txd_num - sizeof(u32_t);
874 pos = (state.txd_tail + state.txd_num +
875 sizeof(u32_t)) % ATL2_TXD_BUFSIZE;
876
877 for (i = 0; i < m->DL_COUNT; i += batch) {
878 /* Copy in the next batch. */
879 batch = MIN(m->DL_COUNT - i, NR_IOREQS);
880
881 r = sys_safecopyfrom(m->m_source, m->DL_GRANT, off,
882 (vir_bytes) iovec, batch * sizeof(iovec[0]));
883 if (r != OK)
884 panic("vector copy failed: %d", r);
885
886 /* Copy in each element in the batch. */
887 for (j = 0, iovp = iovec; j < batch; j++, iovp++) {
888 size = iovp->iov_size;
889 if (size > left)
890 goto suspend;
891
892 skip = 0;
893 if (size > ATL2_TXD_BUFSIZE - pos) {
894 skip = ATL2_TXD_BUFSIZE - pos;
895 r = sys_safecopyfrom(m->m_source,
896 iovp->iov_grant, 0,
897 (vir_bytes) (state.txd_base + pos),
898 skip);
899 if (r != OK)
900 panic("safe copy failed: %d", r);
901 pos = 0;
902 }
903
904 r = sys_safecopyfrom(m->m_source, iovp->iov_grant,
905 skip, (vir_bytes) (state.txd_base + pos),
906 size - skip);
907 if (r != OK)
908 panic("safe copy failed: %d", r);
909
910 pos = (pos + size - skip) % ATL2_TXD_BUFSIZE;
911 left -= size;
912 count += size;
913 }
914
915 off += batch * sizeof(iovec[0]);
916 }
917
918 assert(count <= ETH_MAX_PACK_SIZE_TAGGED);
919
920 /* Write the length to the DWORD right before the packet. */
921 sizep = state.txd_base +
922 (state.txd_tail + state.txd_num) % ATL2_TXD_BUFSIZE;
923 * (u32_t *) sizep = count;
924
925 /* Update the TxD head. */
926 state.txd_num += sizeof(u32_t) + ATL2_ALIGN_32(count);
927 pos = ATL2_ALIGN_32(pos) % ATL2_TXD_BUFSIZE;
928 assert((int) pos ==
929 (state.txd_tail + state.txd_num) % ATL2_TXD_BUFSIZE);
930
931 /* Initialize and update the TxS head. */
932 state.txs_base[(state.txs_tail + state.txs_num) % ATL2_TXS_COUNT] = 0;
933 state.txs_num++;
934
935 /* Tell the device about our new position. */
936 __insn_barrier();
937
938 ATL2_WRITE_U32(ATL2_TXD_IDX_REG, pos / sizeof(u32_t));
939
940 /* We have now successfully set up the transmission of a packet. */
941 state.flags &= ~ATL2_FLAG_WRITE_PEND;
942 state.flags |= ATL2_FLAG_PACK_SENT;
943
944 /* If called from the interrupt handler, the caller will reply. */
945 if (!from_int)
946 atl2_reply();
947
948 return;
949
950 suspend:
951 /* We cannot transmit the packet at this time. If we were not already
952 * trying to resume transmission, save the write request for later,
953 * and tell Inet that the request has been suspended.
954 */
955 if (from_int)
956 return;
957
958 state.flags |= ATL2_FLAG_WRITE_PEND;
959 state.write_msg = *m;
960
961 atl2_reply();
962 }
963
964 /*===========================================================================*
965 * atl2_intr *
966 *===========================================================================*/
967 static void atl2_intr(const message *UNUSED(m))
968 {
969 /* Interrupt received.
970 */
971 u32_t val;
972 int r, try_write, try_read;
973
974 /* Clear and disable interrupts. */
975 val = ATL2_READ_U32(ATL2_ISR_REG);
976
977 ATL2_WRITE_U32(ATL2_ISR_REG, val | ATL2_ISR_DISABLE);
978
979 ATL2_DEBUG(("ATL2: interrupt (0x%08lx)\n", val));
980
981 /* If an error occurred, reset the card. */
982 if (val & (ATL2_ISR_DMAR_TIMEOUT | ATL2_ISR_DMAW_TIMEOUT |
983 ATL2_ISR_PHY_LINKDOWN)) {
984 atl2_setup();
985 }
986
987 try_write = try_read = FALSE;
988
989 /* Process sent data, and possibly send pending data. */
990 if (val & ATL2_ISR_TX_EVENT) {
991 if (atl2_tx_advance())
992 try_write = (state.flags & ATL2_FLAG_WRITE_PEND);
993 }
994
995 /* Receive new data, and possible satisfy a pending receive request. */
996 if (val & ATL2_ISR_RX_EVENT) {
997 if (!(state.flags & ATL2_FLAG_RX_AVAIL)) {
998 atl2_rx_advance(FALSE /*next*/);
999
1000 try_read = (state.flags & ATL2_FLAG_READ_PEND);
1001 }
1002 }
1003
1004 /* Reenable interrupts. */
1005 ATL2_WRITE_U32(ATL2_ISR_REG, 0);
1006
1007 if ((r = sys_irqenable(&state.hook_id)) != OK)
1008 panic("unable to enable IRQ: %d", r);
1009
1010 /* Attempt to satisfy pending write and read requests. */
1011 if (try_write)
1012 atl2_writev(&state.write_msg, TRUE /*from_int*/);
1013 if (try_read)
1014 atl2_readv(&state.read_msg, TRUE /*from_int*/);
1015 if (state.flags & (ATL2_FLAG_PACK_SENT | ATL2_FLAG_PACK_RCVD))
1016 atl2_reply();
1017 }
1018
1019 /*===========================================================================*
1020 * atl2_conf *
1021 *===========================================================================*/
1022 static void atl2_conf(message *m)
1023 {
1024 /* Configure the mode of the card.
1025 */
1026 ether_addr_t addr;
1027 int r;
1028
1029 state.mode = m->DL_MODE;
1030
1031 atl2_set_mode();
1032
1033 addr.ea_addr[0] = state.hwaddr[1] >> 8;
1034 addr.ea_addr[1] = state.hwaddr[1] & 0xff;
1035 addr.ea_addr[2] = state.hwaddr[0] >> 24;
1036 addr.ea_addr[3] = (state.hwaddr[0] >> 16) & 0xff;
1037 addr.ea_addr[4] = (state.hwaddr[0] >> 8) & 0xff;
1038 addr.ea_addr[5] = state.hwaddr[0] & 0xff;
1039
1040 memcpy(m->DL_HWADDR, &addr, sizeof(addr));
1041
1042 m->m_type = DL_CONF_REPLY;
1043 m->DL_STAT = OK;
1044
1045 if ((r = send(m->m_source, m)) != OK)
1046 printf("ATL2: unable to send reply (%d)\n", r);
1047 }
1048
1049 /*===========================================================================*
1050 * atl2_getstat *
1051 *===========================================================================*/
1052 static void atl2_getstat(message *m)
1053 {
1054 /* Copy out statistics.
1055 */
1056 int r;
1057
1058 sys_safecopyto(m->m_source, m->DL_GRANT, 0,
1059 (vir_bytes) &state.stat, sizeof(state.stat));
1060
1061 m->m_type = DL_STAT_REPLY;
1062
1063 if ((r = send(m->m_source, m)) != OK)
1064 printf("ATL2: unable to send reply (%d)\n", r);
1065 }
1066
1067 /*===========================================================================*
1068 * atl2_dump_link *
1069 *===========================================================================*/
1070 static void atl2_dump_link(void)
1071 {
1072 /* Dump link status.
1073 */
1074 u16_t val;
1075 int link_up;
1076
1077 /* The link status bit is latched. Read the status register twice. */
1078 atl2_read_mdio(ATL2_MII_BMSR, &val);
1079 if (!atl2_read_mdio(ATL2_MII_BMSR, &val)) return;
1080
1081 link_up = val & ATL2_MII_BMSR_LSTATUS;
1082 printf("link status: %4s\t", link_up ? "up" : "down");
1083
1084 if (!link_up) return;
1085
1086 if (!atl2_read_mdio(ATL2_MII_PSSR, &val)) return;
1087
1088 if (!(val & ATL2_MII_PSSR_RESOLVED)) {
1089 printf("(not resolved)\n");
1090
1091 return;
1092 }
1093
1094 switch (val & ATL2_MII_PSSR_SPEED) {
1095 case ATL2_MII_PSSR_10: printf("(10Mbps "); break;
1096 case ATL2_MII_PSSR_100: printf("(100Mbps "); break;
1097 case ATL2_MII_PSSR_1000: printf("(1000Mbps "); break;
1098 default: printf("(unknown, ");
1099 }
1100
1101 printf("%s duplex)", (val & ATL2_MII_PSSR_DUPLEX) ? "full" : "half");
1102 }
1103
1104 /*===========================================================================*
1105 * atl2_dump *
1106 *===========================================================================*/
1107 static void atl2_dump(void)
1108 {
1109 /* Dump statistics.
1110 */
1111
1112 printf("\n");
1113 printf("Attansic L2 statistics:\n");
1114
1115 printf("recvErr: %8ld\t", state.stat.ets_recvErr);
1116 printf("sendErr: %8ld\t", state.stat.ets_sendErr);
1117 printf("OVW: %8ld\n", state.stat.ets_OVW);
1118
1119 printf("CRCerr: %8ld\t", state.stat.ets_CRCerr);
1120 printf("frameAll: %8ld\t", state.stat.ets_frameAll);
1121 printf("missedP: %8ld\n", state.stat.ets_missedP);
1122
1123 printf("packetR: %8ld\t", state.stat.ets_packetR);
1124 printf("packetT: %8ld\t", state.stat.ets_packetT);
1125 printf("transDef: %8ld\n", state.stat.ets_transDef);
1126
1127 printf("collision: %8ld\t", state.stat.ets_collision);
1128 printf("transAb: %8ld\t", state.stat.ets_transAb);
1129 printf("carrSense: %8ld\n", state.stat.ets_carrSense);
1130
1131 printf("fifoUnder: %8ld\t", state.stat.ets_fifoUnder);
1132 printf("fifoOver: %8ld\t", state.stat.ets_fifoOver);
1133 printf("CDheartbeat: %8ld\n", state.stat.ets_CDheartbeat);
1134
1135 printf("OWC: %8ld\t", state.stat.ets_OWC);
1136 printf("TxD tail: %8d\t", state.txd_tail);
1137 printf("TxD count: %8d\n", state.txd_num);
1138
1139 printf("RxD tail: %8d\t", state.rxd_tail);
1140 printf("TxS tail: %8d\t", state.txs_tail);
1141 printf("TxS count: %8d\n", state.txs_num);
1142
1143 printf("flags: 0x%04x\t", state.flags);
1144 atl2_dump_link();
1145 printf("\n");
1146 }
1147
1148 /*===========================================================================*
1149 * sef_cb_init_fresh *
1150 *===========================================================================*/
1151 static int sef_cb_init_fresh(int UNUSED(type), sef_init_info_t *UNUSED(info))
1152 {
1153 /* Initialize the atl2 driver.
1154 */
1155 int r, devind;
1156 long v;
1157 #if ATL2_FKEY
1158 int fkeys, sfkeys;
1159 #endif
1160
1161 /* How many matching devices should we skip? */
1162 v = 0;
1163 (void) env_parse("instance", "d", 0, &v, 0, 255);
1164 instance = (int) v;
1165
1166 /* Try to find a recognized device. */
1167 devind = atl2_probe(instance);
1168
1169 if (devind < 0)
1170 panic("no matching device found");
1171
1172 /* Initialize the device. */
1173 atl2_init(devind);
1174
1175 /* Announce we are up! */
1176 netdriver_announce();
1177
1178 #if ATL2_FKEY
1179 /* Register debug dump function key. */
1180 fkeys = sfkeys = 0;
1181 bit_set(sfkeys, 11);
1182 if ((r = fkey_map(&fkeys, &sfkeys)) != OK)
1183 printf("ATL2: warning, could not map Shift+F11 key (%d)\n", r);
1184 #endif
1185
1186 return(OK);
1187 }
1188
1189 /*===========================================================================*
1190 * sef_cb_signal_handler *
1191 *===========================================================================*/
1192 static void sef_cb_signal_handler(int signo)
1193 {
1194 /* In case of a termination signal, shut down this driver.
1195 * Stop the device, and deallocate resources as proof of concept.
1196 */
1197 int r;
1198
1199 /* Only check for termination signal, ignore anything else. */
1200 if (signo != SIGTERM) return;
1201
1202 atl2_stop();
1203
1204 if ((r = sys_irqrmpolicy(&state.hook_id)) != OK)
1205 panic("unable to deregister IRQ: %d", r);
1206
1207 free_contig(state.txd_base, ATL2_TXD_BUFSIZE);
1208 free_contig(state.txs_base, ATL2_TXS_COUNT * sizeof(u32_t));
1209 free_contig(state.rxd_base_u,
1210 state.rxd_align + ATL2_RXD_COUNT * ATL2_RXD_SIZE);
1211
1212 vm_unmap_phys(SELF, (void *) state.base, state.size);
1213
1214 /* We cannot free the PCI device at this time. */
1215
1216 exit(0);
1217 }
1218
1219 /*===========================================================================*
1220 * sef_local_startup *
1221 *===========================================================================*/
1222 static void sef_local_startup(void)
1223 {
1224 /* Register init callbacks. */
1225 sef_setcb_init_fresh(sef_cb_init_fresh);
1226 sef_setcb_init_lu(sef_cb_init_fresh);
1227 sef_setcb_init_restart(sef_cb_init_fresh);
1228
1229 /* Register live update callbacks. */
1230 sef_setcb_lu_prepare(sef_cb_lu_prepare_always_ready);
1231 sef_setcb_lu_state_isvalid(sef_cb_lu_state_isvalid_workfree);
1232
1233 /* Register signal callbacks. */
1234 sef_setcb_signal_handler(sef_cb_signal_handler);
1235
1236 /* Let SEF perform startup. */
1237 sef_startup();
1238 }
1239
1240 /*===========================================================================*
1241 * main *
1242 *===========================================================================*/
1243 int main(int argc, char **argv)
1244 {
1245 /* Driver task.
1246 */
1247 message m;
1248 int ipc_status;
1249 int r;
1250
1251 /* Initialize SEF. */
1252 env_setargs(argc, argv);
1253 sef_local_startup();
1254
1255 while (TRUE) {
1256 if ((r = netdriver_receive(ANY, &m, &ipc_status)) != OK)
1257 panic("netdriver_receive failed: %d", r);
1258
1259 if (is_ipc_notify(ipc_status)) {
1260 switch (m.m_source) {
1261 case HARDWARE: /* interrupt */
1262 atl2_intr(&m);
1263
1264 break;
1265
1266 case TTY_PROC_NR: /* function key */
1267 atl2_dump();
1268
1269 break;
1270
1271 default:
1272 printf("ATL2: illegal notify from %d\n",
1273 m.m_source);
1274 }
1275
1276 continue;
1277 }
1278
1279 /* Process requests from Inet. */
1280 switch (m.m_type) {
1281 case DL_CONF: atl2_conf(&m); break;
1282 case DL_GETSTAT_S: atl2_getstat(&m); break;
1283 case DL_WRITEV_S: atl2_writev(&m, FALSE); break;
1284 case DL_READV_S: atl2_readv(&m, FALSE); break;
1285 default:
1286 printf("ATL2: illegal message %d from %d\n",
1287 m.m_type, m.m_source);
1288 }
1289 }
1290 }
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