1 /* $NetBSD: ffs.S,v 1.3 2011/07/04 12:18:05 mrg Exp $ */
4 * Copyright (c) 2002 The NetBSD Foundation, Inc.
7 * This code is derived from software contributed to The NetBSD Foundation
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
32 #include <machine/asm.h>
34 #if defined(LIBC_SCCS) && !defined(lint)
35 RCSID("$NetBSD: ffs.S,v 1.3 2011/07/04 12:18:05 mrg Exp $")
39 * ffs - find first bit set
41 * This code makes use of ``test 8bit'' and ``shift 8bit'' instructions.
42 * The remaining 8bit is tested in every 2bit.
45 WEAK_ALIAS(__ffssi2,ffs)
47 mov r4,r0 ! using r0 specific instructions
50 mov #0+1,r1 ! ret = 1..8
52 tst r0,r0 ! ffs(0) is 0
53 bt Lzero ! testing here to accelerate ret=1..8 cases
58 mov #8+1,r1 ! ret = 9..16
63 mov #16+1,r1 ! ret = 17..24
66 mov #24+1,r1 ! ret = 25..32
74 tst #0x01,r0 ! not bit 0 -> T
77 addc r1,r0 ! 0 + r1 + T -> r0