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137 .IX Title "OPENSSL_ia32cap 3"
138 .TH OPENSSL_ia32cap 3 "2011-06-05" "1.0.1n" "OpenSSL"
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144 OPENSSL_ia32cap \- finding the IA\-32 processor capabilities
148 .IX Header "SYNOPSIS"
150 \& unsigned long *OPENSSL_ia32cap_loc(void);
151 \& #define OPENSSL_ia32cap (*(OPENSSL_ia32cap_loc()))
154 .IX Header "DESCRIPTION"
155 Value returned by \fIOPENSSL_ia32cap_loc()\fR is address of a variable
156 containing \s-1IA\-32\s0 processor capabilities bit vector as it appears in \s-1EDX\s0
157 register after executing \s-1CPUID\s0 instruction with EAX=1 input value (see
158 Intel Application Note #241618). Naturally it's meaningful on IA\-32[E]
159 platforms only. The variable is normally set up automatically upon
160 toolkit initialization, but can be manipulated afterwards to modify
161 crypto library behaviour. For the moment of this writing six bits are
164 1. bit #28 denoting Hyperthreading, which is used to distiguish
165 cores with shared cache;
166 2. bit #26 denoting \s-1SSE2\s0 support;
167 3. bit #25 denoting \s-1SSE\s0 support;
168 4. bit #23 denoting \s-1MMX\s0 support;
169 5. bit #20, reserved by Intel, is used to choose between \s-1RC4\s0 code
171 6. bit #4 denoting presence of Time-Stamp Counter.
173 For example, clearing bit #26 at run-time disables high-performance
174 \&\s-1SSE2\s0 code present in the crypto library. You might have to do this if
175 target OpenSSL application is executed on \s-1SSE2\s0 capable \s-1CPU,\s0 but under
176 control of \s-1OS\s0 which does not support \s-1SSE2\s0 extentions. Even though you
177 can manipulate the value programmatically, you most likely will find it
178 more appropriate to set up an environment variable with the same name
179 prior starting target application, e.g. on Intel P4 processor 'env
180 OPENSSL_ia32cap=0x12900010 apps/openssl', to achieve same effect
181 without modifying the application source code. Alternatively you can
182 reconfigure the toolkit with no\-sse2 option and recompile.