Remove building with NOCRYPTO option
[minix.git] / minix / drivers / storage / ahci / ahci.h
blobab7c52c74e09344efc88ad2a2fd2bd6eafc867e5
1 #ifndef _AHCI_H
2 #define _AHCI_H
4 #include <minix/drivers.h>
6 #define NR_PORTS 32 /* maximum number of ports */
7 #define NR_CMDS 32 /* maximum number of queued commands */
9 /* Time values that can be set with options. */
10 #define SPINUP_TIMEOUT 5000 /* initial spin-up time (ms) */
11 #define DEVICE_TIMEOUT 30000 /* time to wait for device (ms) */
12 #define COMMAND_TIMEOUT 10000 /* time to wait for non-I/O cmd (ms) */
13 #define TRANSFER_TIMEOUT 30000 /* time to wait for I/O cmd (ms) */
14 #define FLUSH_TIMEOUT 60000 /* time to wait for flush cmd (ms) */
16 /* Time values that are defined by the standards. */
17 #define COMRESET_DELAY 1 /* time to assert port reset (ms) */
18 #define RESET_DELAY 1000 /* maximum HBA reset time (ms) */
19 #define PORTREG_DELAY 500 /* maximum port register update (ms) */
21 /* Other hardcoded time values. */
22 #define DEVICE_DELAY 100 /* time between device checks (ms) */
24 /* Generic FIS layout. */
25 #define ATA_FIS_TYPE 0 /* FIS Type */
26 #define ATA_FIS_TYPE_H2D 0x27 /* Register - Host to Device */
28 /* Register - Host to Device FIS layout. */
29 #define ATA_H2D_SIZE 20 /* byte size of H2D FIS */
30 #define ATA_H2D_FLAGS 1 /* C and PM Port */
31 #define ATA_H2D_FLAGS_C 0x80 /* update command register */
32 #define ATA_H2D_CMD 2 /* Command */
33 #define ATA_CMD_READ_DMA_EXT 0x25 /* READ DMA EXT */
34 #define ATA_CMD_WRITE_DMA_EXT 0x35 /* WRITE DMA EXT */
35 #define ATA_CMD_READ_FPDMA_QUEUED 0x60 /* READ FPDMA QUEUED */
36 #define ATA_CMD_WRITE_FPDMA_QUEUED 0x61 /* WRITE FPDMA QUEUED */
37 #define ATA_CMD_WRITE_DMA_FUA_EXT 0x3D /* WRITE DMA FUA EXT */
38 #define ATA_CMD_PACKET 0xA0 /* PACKET */
39 #define ATA_CMD_IDENTIFY_PACKET 0xA1 /* IDENTIFY PACKET DEVICE */
40 #define ATA_CMD_FLUSH_CACHE 0xE7 /* FLUSH CACHE */
41 #define ATA_CMD_IDENTIFY 0xEC /* IDENTIFY DEVICE */
42 #define ATA_CMD_SET_FEATURES 0xEF /* SET FEATURES */
43 #define ATA_H2D_FEAT 3 /* Features */
44 #define ATA_FEAT_PACKET_DMA 0x01 /* use DMA */
45 #define ATA_FEAT_PACKET_DMADIR 0x03 /* DMA is inbound */
46 #define ATA_H2D_LBA_LOW 4 /* LBA Low */
47 #define ATA_H2D_LBA_MID 5 /* LBA Mid */
48 #define ATA_H2D_LBA_HIGH 6 /* LBA High */
49 #define ATA_H2D_DEV 7 /* Device */
50 #define ATA_DEV_LBA 0x40 /* use LBA addressing */
51 #define ATA_DEV_FUA 0x80 /* Force Unit Access (FPDMA) */
52 #define ATA_H2D_LBA_LOW_EXP 8 /* LBA Low (exp) */
53 #define ATA_H2D_LBA_MID_EXP 9 /* LBA Mid (exp) */
54 #define ATA_H2D_LBA_HIGH_EXP 10 /* LBA High (exp) */
55 #define ATA_H2D_FEAT_EXP 11 /* Features (exp) */
56 #define ATA_H2D_SEC 12 /* Sector Count */
57 #define ATA_SEC_TAG_SHIFT 3 /* NCQ command tag */
58 #define ATA_H2D_SEC_EXP 13 /* Sector Count (exp) */
59 #define ATA_H2D_CTL 15 /* Control */
61 #define ATA_IS_FPDMA_CMD(c) \
62 ((c) == ATA_CMD_READ_FPDMA_QUEUED || \
63 (c) == ATA_CMD_WRITE_FPDMA_QUEUED)
65 /* ATA constants. */
66 #define ATA_SECTOR_SIZE 512 /* default sector size */
67 #define ATA_MAX_SECTORS 0x10000 /* max sectors per transfer */
69 #define ATA_ID_SIZE (256 * sizeof(u16_t)) /* IDENTIFY result size */
71 #define ATA_ID_GCAP 0 /* General capabililties */
72 #define ATA_ID_GCAP_ATAPI_MASK 0xC000 /* ATAPI device mask */
73 #define ATA_ID_GCAP_ATAPI 0x8000 /* ATAPI device */
74 #define ATA_ID_GCAP_ATA_MASK 0x8000 /* ATA device mask */
75 #define ATA_ID_GCAP_ATA 0x0000 /* ATA device */
76 #define ATA_ID_GCAP_TYPE_MASK 0x1F00 /* ATAPI device type */
77 #define ATA_ID_GCAP_TYPE_SHIFT 8 /* (one of ATAPI_TYPE_*) */
78 #define ATA_ID_GCAP_REMOVABLE 0x0080 /* Removable media device */
79 #define ATA_ID_GCAP_INCOMPLETE 0x0004 /* Incomplete response */
80 #define ATA_ID_CAP 49 /* Capabilities */
81 #define ATA_ID_CAP_DMA 0x0100 /* DMA supported (no DMADIR) */
82 #define ATA_ID_CAP_LBA 0x0200 /* LBA supported */
83 #define ATA_ID_DMADIR 62 /* DMADIR */
84 #define ATA_ID_DMADIR_DMADIR 0x8000 /* DMADIR required */
85 #define ATA_ID_DMADIR_DMA 0x0400 /* DMA supported (DMADIR) */
86 #define ATA_ID_QDEPTH 75 /* NCQ queue depth */
87 #define ATA_ID_QDEPTH_MASK 0x000F /* NCQ queue depth mask */
88 #define ATA_ID_SATA_CAP 76 /* SATA capabilities */
89 #define ATA_ID_SATA_CAP_NCQ 0x0100 /* NCQ support */
90 #define ATA_ID_SUP0 82 /* Features supported (1/3) */
91 #define ATA_ID_SUP0_WCACHE 0x0020 /* Write cache supported */
92 #define ATA_ID_SUP1 83 /* Features supported (2/3) */
93 #define ATA_ID_SUP1_VALID_MASK 0xC000 /* Word validity mask */
94 #define ATA_ID_SUP1_VALID 0x4000 /* Word contents are valid */
95 #define ATA_ID_SUP1_FLUSH 0x1000 /* FLUSH CACHE supported */
96 #define ATA_ID_SUP1_LBA48 0x0400 /* 48-bit LBA supported */
97 #define ATA_ID_ENA0 85 /* Features enabled (1/3) */
98 #define ATA_ID_ENA0_WCACHE 0x0020 /* Write cache enabled */
99 #define ATA_ID_ENA2 87 /* Features enabled (3/3) */
100 #define ATA_ID_ENA2_VALID_MASK 0xC000 /* Word validity mask */
101 #define ATA_ID_ENA2_VALID 0x4000 /* Word contents are valid */
102 #define ATA_ID_ENA2_FUA 0x0040 /* Forced Unit Access sup. */
103 #define ATA_ID_LBA0 100 /* Max. LBA48 address (LSW) */
104 #define ATA_ID_LBA1 101 /* Max. LBA48 address */
105 #define ATA_ID_LBA2 102 /* Max. LBA48 address */
106 #define ATA_ID_LBA3 103 /* Max. LBA48 address (MSW) */
107 #define ATA_ID_PLSS 106 /* Phys./logical sector size */
108 #define ATA_ID_PLSS_VALID_MASK 0xC000 /* Word validity mask */
109 #define ATA_ID_PLSS_VALID 0x4000 /* Word contents are valid */
110 #define ATA_ID_PLSS_LLS 0x1000 /* Long logical sectors */
111 #define ATA_ID_LSS0 118 /* Logical sector size (LSW) */
112 #define ATA_ID_LSS1 119 /* Logical sector size (MSW) */
114 #define ATA_SF_EN_WCACHE 0x02 /* Enable write cache */
115 #define ATA_SF_DI_WCACHE 0x82 /* Disable write cache */
117 /* ATAPI constants. */
118 #define ATAPI_PACKET_SIZE 16 /* ATAPI packet size */
120 #define ATAPI_TYPE_CDROM 5 /* CD-ROM device */
122 #define ATAPI_CMD_TEST_UNIT 0x00 /* Test Unit Ready */
123 #define ATAPI_CMD_REQUEST_SENSE 0x03 /* Request Sense */
124 #define ATAPI_REQUEST_SENSE_LEN 18 /* result length */
125 #define ATAPI_SENSE_UNIT_ATT 6 /* Unit Attention */
126 #define ATAPI_CMD_START_STOP 0x1B /* Start/Stop Unit */
127 #define ATAPI_START_STOP_EJECT 0x02 /* eject the medium */
128 #define ATAPI_START_STOP_LOAD 0x03 /* load the medium */
129 #define ATAPI_CMD_READ_CAPACITY 0x25 /* Read Capacity */
130 #define ATAPI_READ_CAPACITY_LEN 8 /* result length */
131 #define ATAPI_CMD_READ 0xA8 /* Read (12) */
132 #define ATAPI_CMD_WRITE 0xAA /* Write (12) */
134 /* Command List constants. */
135 #define AHCI_CL_ENTRY_SIZE 32 /* Command List header size */
136 #define AHCI_CL_ENTRY_DWORDS (AHCI_CL_ENTRY_SIZE / sizeof(u32_t))
138 #define AHCI_CL_PRDTL_SHIFT 16 /* PRD Table Length */
139 #define AHCI_CL_PREFETCHABLE (1L << 7) /* Prefetchable */
140 #define AHCI_CL_WRITE (1L << 6) /* Write */
141 #define AHCI_CL_ATAPI (1L << 5) /* ATAPI */
142 #define AHCI_CL_CFL_SHIFT 0 /* Command FIS Length */
144 /* Command Table offsets. */
145 #define AHCI_CT_PACKET_OFF 0x40 /* CT offset to ATAPI packet */
146 #define AHCI_CT_PRDT_OFF 0x80 /* CT offset to PRD table */
148 /* Host Bus Adapter (HBA) constants. */
149 #define AHCI_HBA_CAP 0 /* Host Capabilities */
150 #define AHCI_HBA_CAP_SNCQ (1L << 30) /* Native Cmd Queuing */
151 #define AHCI_HBA_CAP_SCLO (1L << 24) /* Cmd List Override */
152 #define AHCI_HBA_CAP_NCS_SHIFT 8 /* Nr of Cmd Slots */
153 #define AHCI_HBA_CAP_NCS_MASK 0x1FL
154 #define AHCI_HBA_CAP_NP_SHIFT 0 /* Nr of Ports */
155 #define AHCI_HBA_CAP_NP_MASK 0x1FL
156 #define AHCI_HBA_GHC 1 /* Global Host Control */
157 #define AHCI_HBA_GHC_AE (1L << 31) /* AHCI Enable */
158 #define AHCI_HBA_GHC_IE (1L << 1) /* Interrupt Enable */
159 #define AHCI_HBA_GHC_HR (1L << 0) /* HBA Reset */
160 #define AHCI_HBA_IS 2 /* Interrupt Status */
161 #define AHCI_HBA_PI 3 /* Ports Implemented */
162 #define AHCI_HBA_VS 4 /* Version */
163 #define AHCI_HBA_CAP2 9 /* Host Capabilities Extended */
165 /* Port constants. */
166 #define AHCI_PORT_CLB 0 /* Command List Base */
167 #define AHCI_PORT_CLBU 1 /* Command List Base, Upper 32 bits */
168 #define AHCI_PORT_FB 2 /* FIS Base */
169 #define AHCI_PORT_FBU 3 /* FIS Base, Upper 32 bits */
170 #define AHCI_PORT_IS 4 /* Interrupt Status */
171 #define AHCI_PORT_IS_TFES (1L << 30) /* Task File Error */
172 #define AHCI_PORT_IS_HBFS (1L << 29) /* Host Bus Fatal */
173 #define AHCI_PORT_IS_HBDS (1L << 28) /* Host Bus Data */
174 #define AHCI_PORT_IS_IFS (1L << 27) /* Interface Fatal */
175 #define AHCI_PORT_IS_PRCS (1L << 22) /* PhyRdy Change */
176 #define AHCI_PORT_IS_PCS (1L << 6) /* Port Conn Change */
177 #define AHCI_PORT_IS_SDBS (1L << 3) /* Set Dev Bits FIS */
178 #define AHCI_PORT_IS_PSS (1L << 1) /* PIO Setup FIS */
179 #define AHCI_PORT_IS_DHRS (1L << 0) /* D2H Register FIS */
180 #define AHCI_PORT_IS_RESTART \
181 (AHCI_PORT_IS_TFES | AHCI_PORT_IS_HBFS | AHCI_PORT_IS_HBDS | \
182 AHCI_PORT_IS_IFS)
183 #define AHCI_PORT_IS_MASK \
184 (AHCI_PORT_IS_RESTART | AHCI_PORT_IS_PRCS | AHCI_PORT_IS_DHRS | \
185 AHCI_PORT_IS_PSS | AHCI_PORT_IS_SDBS)
186 #define AHCI_PORT_IE 5 /* Interrupt Enable */
187 #define AHCI_PORT_IE_MASK AHCI_PORT_IS_MASK
188 #define AHCI_PORT_IE_PRCE AHCI_PORT_IS_PRCS
189 #define AHCI_PORT_IE_PCE AHCI_PORT_IS_PCS
190 #define AHCI_PORT_IE_NONE 0L
191 #define AHCI_PORT_CMD 6 /* Command and Status */
192 #define AHCI_PORT_CMD_CR (1L << 15) /* Cmd List Running */
193 #define AHCI_PORT_CMD_FR (1L << 14) /* FIS Recv Running */
194 #define AHCI_PORT_CMD_FRE (1L << 4) /* FIS Recv Enabled */
195 #define AHCI_PORT_CMD_CLO (1L << 3) /* Cmd List Override */
196 #define AHCI_PORT_CMD_SUD (1L << 1) /* Spin-Up Device */
197 #define AHCI_PORT_CMD_ST (1L << 0) /* Start */
198 #define AHCI_PORT_TFD 8 /* Task File Data */
199 #define AHCI_PORT_TFD_STS_BSY (1L << 7) /* Busy */
200 #define AHCI_PORT_TFD_STS_DF (1L << 5) /* Device Fault */
201 #define AHCI_PORT_TFD_STS_DRQ (1L << 3) /* Data Xfer Req'd */
202 #define AHCI_PORT_TFD_STS_ERR (1L << 0) /* Error */
203 #define AHCI_PORT_TFD_STS_INIT 0x7F /* Initial state */
204 #define AHCI_PORT_SIG 9 /* Signature */
205 #define ATA_SIG_ATA 0x00000101L /* ATA interface */
206 #define ATA_SIG_ATAPI 0xEB140101L /* ATAPI interface */
207 #define AHCI_PORT_SSTS 10 /* Serial ATA Status */
208 #define AHCI_PORT_SSTS_DET_MASK 0x00000007L /* Detection Mask */
209 #define AHCI_PORT_SSTS_DET_DET 0x00000001L /* Device Detected */
210 #define AHCI_PORT_SSTS_DET_PHY 0x00000003L /* PHY Comm Establ */
211 #define AHCI_PORT_SCTL 11 /* Serial ATA Control */
212 #define AHCI_PORT_SCTL_DET_INIT 0x00000001L /* Perform Init Seq */
213 #define AHCI_PORT_SCTL_DET_NONE 0x00000000L /* No Action Req'd */
214 #define AHCI_PORT_SERR 12 /* Serial ATA Error */
215 #define AHCI_PORT_SERR_DIAG_X (1L << 26) /* Exchanged */
216 #define AHCI_PORT_SERR_DIAG_N (1L << 16) /* PhyRdy Change */
217 #define AHCI_PORT_SACT 13 /* Serial ATA Active */
218 #define AHCI_PORT_CI 14 /* Command Issue */
220 /* Number of Physical Region Descriptors (PRDs). Must be at least NR_IOREQS+2,
221 * and at most 1024. There is currently no reason to use more than the minimum.
223 #define NR_PRDS (NR_IOREQS + 2)
225 /* Various size constants. */
226 #define AHCI_MEM_BASE_SIZE 0x100 /* memory-mapped base region size */
227 #define AHCI_MEM_PORT_SIZE 0x80 /* memory-mapped port region size */
229 #define AHCI_FIS_SIZE 256 /* size of FIS receive buffer */
230 #define AHCI_CL_SIZE 1024 /* size of command list buffer */
231 #define AHCI_TMP_SIZE ATA_ID_SIZE /* size of temporary storage buffer */
232 #define AHCI_TMP_ALIGN 2 /* required alignment for temp buf */
233 #define AHCI_CT_SIZE (128 + NR_PRDS * sizeof(u32_t) * 4)
234 /* size of command table buffer */
235 #define AHCI_CT_ALIGN 128 /* required alignment for CT buffer */
237 #define MAX_PRD_BYTES (1L << 22) /* maximum number of bytes per PRD */
238 #define MAX_TRANSFER MAX_PRD_BYTES /* maximum size of a single transfer */
240 /* Command Frame Information Structure (FIS). For internal use only;
241 * the contents of this structure are later converted to an actual FIS.
243 typedef struct {
244 u8_t cf_cmd; /* Command */
245 u8_t cf_feat; /* Features */
246 u32_t cf_lba; /* LBA (24-bit) */
247 u8_t cf_dev; /* Device */
248 u32_t cf_lba_exp; /* LBA (exp) (24-bit) */
249 u8_t cf_feat_exp; /* Features (exp) */
250 u8_t cf_sec; /* Sector Count */
251 u8_t cf_sec_exp; /* Sector Count (exp) */
252 u8_t cf_ctl; /* Control */
253 } cmd_fis_t;
255 /* Physical Region Descriptor (PRD). For internal and sys_vumap() use only;
256 * the contents of this structure are later converted to an actual PRD.
258 typedef struct vumap_phys prd_t;
260 /* These are from at_wini, as this driver is a drop-in replacement for at_wini.
261 * Practically speaking this is already the upper limit with 256 minor device
262 * numbers per driver, even though it means we can only ever expose 8 devices
263 * out of potentially 32.
265 #define MAX_DRIVES 8
266 #define NR_MINORS (MAX_DRIVES * DEV_PER_DRIVE)
267 #define NR_SUBDEVS (MAX_DRIVES * SUB_PER_DRIVE)
269 /* Port states. */
270 enum {
271 STATE_NO_PORT, /* this port is not present */
272 STATE_SPIN_UP, /* waiting for device or timeout after reset */
273 STATE_NO_DEV, /* no device has been detected on this port */
274 STATE_WAIT_DEV, /* waiting for functioning device to appear */
275 STATE_WAIT_ID, /* waiting for device identification */
276 STATE_BAD_DEV, /* an unusable device has been detected */
277 STATE_GOOD_DEV /* a usable device has been detected */
280 /* Command results. */
281 enum {
282 RESULT_FAILURE,
283 RESULT_SUCCESS
286 /* Port flags. */
287 #define FLAG_ATAPI 0x00000001 /* is this an ATAPI device? */
288 #define FLAG_HAS_MEDIUM 0x00000002 /* is a medium present? */
289 #define FLAG_USE_DMADIR 0x00000004 /* use ATAPI DMADIR flag? */
290 #define FLAG_READONLY 0x00000008 /* is the device read-only? */
291 #define FLAG_BUSY 0x00000010 /* is an operation ongoing? */
292 #define FLAG_FAILURE 0x00000020 /* did the operation fail? */
293 #define FLAG_BARRIER 0x00000040 /* no access until unset */
294 #define FLAG_HAS_WCACHE 0x00000080 /* is a write cache present? */
295 #define FLAG_HAS_FLUSH 0x00000100 /* is FLUSH CACHE supported? */
296 #define FLAG_SUSPENDED 0x00000200 /* is the thread suspended? */
297 #define FLAG_HAS_FUA 0x00000400 /* is WRITE DMA FUA EX sup.? */
298 #define FLAG_HAS_NCQ 0x00000800 /* is NCQ supported? */
299 #define FLAG_NCQ_MODE 0x00001000 /* issuing NCQ commands? */
301 /* Mapping between devices and ports. */
302 #define NO_PORT -1 /* this device maps to no port */
303 #define NO_DEVICE -1 /* this port maps to no device */
305 /* Output verbosity levels. */
306 enum {
307 V_NONE, /* no output at all; keep silent */
308 V_ERR, /* important error information only (the default) */
309 V_INFO, /* general information about the driver and devices */
310 V_DEV, /* device details, to help with detection problems */
311 V_REQ /* detailed information about requests */
314 #endif /* _AHCI_H */