sys/arch/x86/include/specialreg.h

   1 /*      $NetBSD: specialreg.h,v 1.83 2015/08/14 06:54:22 msaitoh Exp $  */
   2
   3 /*-
   4  * Copyright (c) 1991 The Regents of the University of California.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. Neither the name of the University nor the names of its contributors
  16  *    may be used to endorse or promote products derived from this software
  17  *    without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  * SUCH DAMAGE.
  30  *
  31  *      @(#)specialreg.h        7.1 (Berkeley) 5/9/91
  32  */
  33
  34 /*
  35  * Bits in 386 special registers:
  36  */
  37 #define CR0_PE  0x00000001      /* Protected mode Enable */
  38 #define CR0_MP  0x00000002      /* "Math" Present (NPX or NPX emulator) */
  39 #define CR0_EM  0x00000004      /* EMulate non-NPX coproc. (trap ESC only) */
  40 #define CR0_TS  0x00000008      /* Task Switched (if MP, trap ESC and WAIT) */
  41 #define CR0_ET  0x00000010      /* Extension Type (387 (if set) vs 287) */
  42 #define CR0_PG  0x80000000      /* PaGing enable */
  43
  44 /*
  45  * Bits in 486 special registers:
  46  */
  47 #define CR0_NE  0x00000020      /* Numeric Error enable (EX16 vs IRQ13) */
  48 #define CR0_WP  0x00010000      /* Write Protect (honor PG_RW in all modes) */
  49 #define CR0_AM  0x00040000      /* Alignment Mask (set to enable AC flag) */
  50 #define CR0_NW  0x20000000      /* Not Write-through */
  51 #define CR0_CD  0x40000000      /* Cache Disable */
  52
  53 /*
  54  * Cyrix 486 DLC special registers, accessible as IO ports.
  55  */
  56 #define CCR0    0xc0            /* configuration control register 0 */
  57 #define CCR0_NC0        0x01    /* first 64K of each 1M memory region is non-cacheable */
  58 #define CCR0_NC1        0x02    /* 640K-1M region is non-cacheable */
  59 #define CCR0_A20M       0x04    /* enables A20M# input pin */
  60 #define CCR0_KEN        0x08    /* enables KEN# input pin */
  61 #define CCR0_FLUSH      0x10    /* enables FLUSH# input pin */
  62 #define CCR0_BARB       0x20    /* flushes internal cache when entering hold state */
  63 #define CCR0_CO         0x40    /* cache org: 1=direct mapped, 0=2x set assoc */
  64 #define CCR0_SUSPEND    0x80    /* enables SUSP# and SUSPA# pins */
  65
  66 #define CCR1    0xc1            /* configuration control register 1 */
  67 #define CCR1_RPL        0x01    /* enables RPLSET and RPLVAL# pins */
  68 /* the remaining 7 bits of this register are reserved */
  69
  70 /*
  71  * bits in the %cr4 control register:
  72  */
  73 #define CR4_VME         0x00000001 /* virtual 8086 mode extension enable */
  74 #define CR4_PVI         0x00000002 /* protected mode virtual interrupt enable */
  75 #define CR4_TSD         0x00000004 /* restrict RDTSC instruction to cpl 0 */
  76 #define CR4_DE          0x00000008 /* debugging extension */
  77 #define CR4_PSE         0x00000010 /* large (4MB) page size enable */
  78 #define CR4_PAE         0x00000020 /* physical address extension enable */
  79 #define CR4_MCE         0x00000040 /* machine check enable */
  80 #define CR4_PGE         0x00000080 /* page global enable */
  81 #define CR4_PCE         0x00000100 /* enable RDPMC instruction for all cpls */
  82 #define CR4_OSFXSR      0x00000200 /* enable fxsave/fxrestor and SSE */
  83 #define CR4_OSXMMEXCPT  0x00000400 /* enable unmasked SSE exceptions */
  84 #define CR4_VMXE        0x00002000 /* enable VMX operations */
  85 #define CR4_SMXE        0x00004000 /* enable SMX operations */
  86 #define CR4_FSGSBASE    0x00010000 /* enable *FSBASE and *GSBASE instructions */
  87 #define CR4_PCIDE       0x00020000 /* enable Process Context IDentifiers */
  88 #define CR4_OSXSAVE     0x00040000 /* enable xsave and xrestore */
  89 #define CR4_SMEP        0x00100000 /* enable SMEP support */
  90 #define CR4_SMAP        0x00200000 /* enable SMAP support */
  91
  92 /*
  93  * Extended Control Register XCR0
  94  */
  95 #define XCR0_X87        0x00000001      /* x87 FPU/MMX state */
  96 #define XCR0_SSE        0x00000002      /* SSE state */
  97 #define XCR0_YMM_Hi128  0x00000004      /* AVX-256 (ymmn registers) */
  98 #define XCR0_BNDREGS    0x00000008      /* Memory protection ext bounds */
  99 #define XCR0_BNDCSR     0x00000010      /* Memory protection ext state */
 100 #define XCR0_Opmask     0x00000020      /* AVX-512 Opmask */
 101 #define XCR0_ZMM_Hi256  0x00000040      /* AVX-512 upper 256 bits low regs */
 102 #define XCR0_Hi16_ZMM   0x00000080      /* AVX-512 512 bits upper registers */
 103
 104 /*
 105  * Known fpu bits - only these get enabled
 106  * I think the XCR0_BNDREGS and XCR0_BNDCSR would need saving on
 107  * every context switch.
 108  * The save are is sized for all the fields below (max 2680 bytes).
 109  */
 110 #define XCR0_FPU        (XCR0_X87 | XCR0_SSE | XCR0_YMM_Hi128 | \
 111                         XCR0_Opmask | XCR0_ZMM_Hi256 | XCR0_Hi16_ZMM)
 112
 113 #define XCR0_BND        (XCR0_BNDREGS | XCR0_BNDCSR)
 114
 115 #define XCR0_FLAGS1     "\20" \
 116         "\1" "x87"      "\2" "SSE"      "\3" "AVX" \
 117         "\4" "BNDREGS"  "\5" "BNDCSR" \
 118         "\6" "Opmask"   "\7" "ZMM_Hi256" "\10" "Hi16_ZMM"
 119
 120
 121 /*
 122  * CPUID "features" bits
 123  */
 124
 125 /* Fn00000001 %edx features */
 126 #define CPUID_FPU       0x00000001      /* processor has an FPU? */
 127 #define CPUID_VME       0x00000002      /* has virtual mode (%cr4's VME/PVI) */
 128 #define CPUID_DE        0x00000004      /* has debugging extension */
 129 #define CPUID_PSE       0x00000008      /* has 4MB page size extension */
 130 #define CPUID_TSC       0x00000010      /* has time stamp counter */
 131 #define CPUID_MSR       0x00000020      /* has mode specific registers */
 132 #define CPUID_PAE       0x00000040      /* has phys address extension */
 133 #define CPUID_MCE       0x00000080      /* has machine check exception */
 134 #define CPUID_CX8       0x00000100      /* has CMPXCHG8B instruction */
 135 #define CPUID_APIC      0x00000200      /* has enabled APIC */
 136 #define CPUID_B10       0x00000400      /* reserved, MTRR */
 137 #define CPUID_SEP       0x00000800      /* has SYSENTER/SYSEXIT extension */
 138 #define CPUID_MTRR      0x00001000      /* has memory type range register */
 139 #define CPUID_PGE       0x00002000      /* has page global extension */
 140 #define CPUID_MCA       0x00004000      /* has machine check architecture */
 141 #define CPUID_CMOV      0x00008000      /* has CMOVcc instruction */
 142 #define CPUID_PAT       0x00010000      /* Page Attribute Table */
 143 #define CPUID_PSE36     0x00020000      /* 36-bit PSE */
 144 #define CPUID_PN        0x00040000      /* processor serial number */
 145 #define CPUID_CFLUSH    0x00080000      /* CFLUSH insn supported */
 146 #define CPUID_B20       0x00100000      /* reserved */
 147 #define CPUID_DS        0x00200000      /* Debug Store */
 148 #define CPUID_ACPI      0x00400000      /* ACPI performance modulation regs */
 149 #define CPUID_MMX       0x00800000      /* MMX supported */
 150 #define CPUID_FXSR      0x01000000      /* fast FP/MMX save/restore */
 151 #define CPUID_SSE       0x02000000      /* streaming SIMD extensions */
 152 #define CPUID_SSE2      0x04000000      /* streaming SIMD extensions #2 */
 153 #define CPUID_SS        0x08000000      /* self-snoop */
 154 #define CPUID_HTT       0x10000000      /* Hyper-Threading Technology */
 155 #define CPUID_TM        0x20000000      /* thermal monitor (TCC) */
 156 #define CPUID_IA64      0x40000000      /* IA-64 architecture */
 157 #define CPUID_SBF       0x80000000      /* signal break on FERR */
 158
 159 #define CPUID_FLAGS1    "\20" \
 160         "\1" "FPU"      "\2" "VME"      "\3" "DE"       "\4" "PSE" \
 161         "\5" "TSC"      "\6" "MSR"      "\7" "PAE"      "\10" "MCE" \
 162         "\11" "CX8"     "\12" "APIC"    "\13" "B10"     "\14" "SEP" \
 163         "\15" "MTRR"    "\16" "PGE"     "\17" "MCA"     "\20" "CMOV" \
 164         "\21" "PAT"     "\22" "PSE36"   "\23" "PN"      "\24" "CFLUSH" \
 165         "\25" "B20"     "\26" "DS"      "\27" "ACPI"    "\30" "MMX" \
 166         "\31" "FXSR"    "\32" "SSE"     "\33" "SSE2"    "\34" "SS" \
 167         "\35" "HTT"     "\36" "TM"      "\37" "IA64"    "\40" "SBF"
 168
 169 /* Blacklists of CPUID flags - used to mask certain features */
 170 #ifdef XEN
 171 /* Not on Xen */
 172 #define CPUID_FEAT_BLACKLIST     (CPUID_PGE|CPUID_PSE|CPUID_MTRR)
 173 #else
 174 #define CPUID_FEAT_BLACKLIST     0
 175 #endif /* XEN */
 176
 177 /*
 178  * CPUID "features" bits in Fn00000001 %ecx
 179  */
 180
 181 #define CPUID2_SSE3     0x00000001      /* Streaming SIMD Extensions 3 */
 182 #define CPUID2_PCLMUL   0x00000002      /* PCLMULQDQ instructions */
 183 #define CPUID2_DTES64   0x00000004      /* 64-bit Debug Trace */
 184 #define CPUID2_MONITOR  0x00000008      /* MONITOR/MWAIT instructions */
 185 #define CPUID2_DS_CPL   0x00000010      /* CPL Qualified Debug Store */
 186 #define CPUID2_VMX      0x00000020      /* Virtual Machine Extensions */
 187 #define CPUID2_SMX      0x00000040      /* Safer Mode Extensions */
 188 #define CPUID2_EST      0x00000080      /* Enhanced SpeedStep Technology */
 189 #define CPUID2_TM2      0x00000100      /* Thermal Monitor 2 */
 190 #define CPUID2_SSSE3    0x00000200      /* Supplemental SSE3 */
 191 #define CPUID2_CID      0x00000400      /* Context ID */
 192 #define CPUID2_SDBG     0x00000800      /* Silicon Debug */
 193 #define CPUID2_FMA      0x00001000      /* has Fused Multiply Add */
 194 #define CPUID2_CX16     0x00002000      /* has CMPXCHG16B instruction */
 195 #define CPUID2_xTPR     0x00004000      /* Task Priority Messages disabled? */
 196 #define CPUID2_PDCM     0x00008000      /* Perf/Debug Capability MSR */
 197 /* bit 16 unused        0x00010000 */
 198 #define CPUID2_PCID     0x00020000      /* Process Context ID */
 199 #define CPUID2_DCA      0x00040000      /* Direct Cache Access */
 200 #define CPUID2_SSE41    0x00080000      /* Streaming SIMD Extensions 4.1 */
 201 #define CPUID2_SSE42    0x00100000      /* Streaming SIMD Extensions 4.2 */
 202 #define CPUID2_X2APIC   0x00200000      /* xAPIC Extensions */
 203 #define CPUID2_MOVBE    0x00400000      /* MOVBE (move after byteswap) */
 204 #define CPUID2_POPCNT   0x00800000      /* popcount instruction available */
 205 #define CPUID2_DEADLINE 0x01000000      /* APIC Timer supports TSC Deadline */
 206 #define CPUID2_AES      0x02000000      /* AES instructions */
 207 #define CPUID2_XSAVE    0x04000000      /* XSAVE instructions */
 208 #define CPUID2_OSXSAVE  0x08000000      /* XGETBV/XSETBV instructions */
 209 #define CPUID2_AVX      0x10000000      /* AVX instructions */
 210 #define CPUID2_F16C     0x20000000      /* half precision conversion */
 211 #define CPUID2_RDRAND   0x40000000      /* RDRAND (hardware random number) */
 212 #define CPUID2_RAZ      0x80000000      /* RAZ. Indicates guest state. */
 213
 214 #define CPUID2_FLAGS1   "\20" \
 215         "\1" "SSE3"     "\2" "PCLMULQDQ" "\3" "DTES64"  "\4" "MONITOR" \
 216         "\5" "DS-CPL"   "\6" "VMX"      "\7" "SMX"      "\10" "EST" \
 217         "\11" "TM2"     "\12" "SSSE3"   "\13" "CID"     "\14" "SDBG" \
 218         "\15" "FMA"     "\16" "CX16"    "\17" "xTPR"    "\20" "PDCM" \
 219         "\21" "B16"     "\22" "PCID"    "\23" "DCA"     "\24" "SSE41" \
 220         "\25" "SSE42"   "\26" "X2APIC"  "\27" "MOVBE"   "\30" "POPCNT" \
 221         "\31" "DEADLINE" "\32" "AES"    "\33" "XSAVE"   "\34" "OSXSAVE" \
 222         "\35" "AVX"     "\36" "F16C"    "\37" "RDRAND"  "\40" "RAZ"
 223
 224 /* CPUID Fn00000001 %eax */
 225
 226 #define CPUID_TO_BASEFAMILY(cpuid)      (((cpuid) >> 8) & 0xf)
 227 #define CPUID_TO_BASEMODEL(cpuid)       (((cpuid) >> 4) & 0xf)
 228 #define CPUID_TO_STEPPING(cpuid)        ((cpuid) & 0xf)
 229
 230 /*
 231  * The Extended family bits should only be inspected when CPUID_TO_BASEFAMILY()
 232  * returns 15. They are use to encode family value 16 to 270 (add 15).
 233  * The Extended model bits are the high 4 bits of the model.
 234  * They are only valid for family >= 15 or family 6 (intel, but all amd
 235  * family 6 are documented to return zero bits for them).
 236  */
 237 #define CPUID_TO_EXTFAMILY(cpuid)       (((cpuid) >> 20) & 0xff)
 238 #define CPUID_TO_EXTMODEL(cpuid)        (((cpuid) >> 16) & 0xf)
 239
 240 /* The macros for the Display Family and the Display Model */
 241 #define CPUID_TO_FAMILY(cpuid)  (CPUID_TO_BASEFAMILY(cpuid)     \
 242             + ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f)             \
 243                 ? 0 : CPUID_TO_EXTFAMILY(cpuid)))
 244 #define CPUID_TO_MODEL(cpuid)   (CPUID_TO_BASEMODEL(cpuid)      \
 245             | ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f)             \
 246                 && (CPUID_TO_BASEFAMILY(cpuid) != 0x06)         \
 247                 ? 0 : (CPUID_TO_EXTMODEL(cpuid) << 4)))
 248
 249 /*
 250  * Intel Deterministic Cache Parameter Leaf
 251  * Fn0000_0004
 252  */
 253
 254 /* %eax */
 255 #define CPUID_DCP_CACHETYPE     __BITS(4, 0)    /* Cache type */
 256 #define CPUID_DCP_CACHETYPE_N   0               /*   NULL */
 257 #define CPUID_DCP_CACHETYPE_D   1               /*   Data cache */
 258 #define CPUID_DCP_CACHETYPE_I   2               /*   Instruction cache */
 259 #define CPUID_DCP_CACHETYPE_U   3               /*   Unified cache */
 260 #define CPUID_DCP_CACHELEVEL    __BITS(7, 5)    /* Cache level (start at 1) */
 261 #define CPUID_DCP_SELFINITCL    __BIT(8)        /* Self initializing cachelvl*/
 262 #define CPUID_DCP_FULLASSOC     __BIT(9)        /* Full associative */
 263 #define CPUID_DCP_SHAREING      __BITS(25, 14)  /* shareing */
 264 #define CPUID_DCP_CORE_P_PKG    __BITS(31, 26)  /* Cores/package */
 265
 266 /* %ebx */
 267 #define CPUID_DCP_LINESIZE      __BITS(11, 0)   /* System coherency linesize */
 268 #define CPUID_DCP_PARTITIONS    __BITS(21, 12)  /* Physical line partitions */
 269 #define CPUID_DCP_WAYS          __BITS(31, 22)  /* Ways of associativity */
 270
 271 /* Number of sets: %ecx */
 272
 273 /* %edx */
 274 #define CPUID_DCP_INVALIDATE    __BIT(0)        /* WB invalidate/invalidate */
 275 #define CPUID_DCP_INCLUSIVE     __BIT(1)        /* Cache inclusiveness */
 276 #define CPUID_DCP_COMPLEX       __BIT(2)        /* Complex cache indexing */
 277
 278 /*
 279  * Intel Digital Thermal Sensor and
 280  * Power Management, Fn0000_0006 - %eax.
 281  */
 282 #define CPUID_DSPM_DTS  __BIT(0)        /* Digital Thermal Sensor */
 283 #define CPUID_DSPM_IDA  __BIT(1)        /* Intel Dynamic Acceleration */
 284 #define CPUID_DSPM_ARAT __BIT(2)        /* Always Running APIC Timer */
 285 #define CPUID_DSPM_PLN  __BIT(4)        /* Power Limit Notification */
 286 #define CPUID_DSPM_ECMD __BIT(5)        /* Clock Modulation Extension */
 287 #define CPUID_DSPM_PTM  __BIT(6)        /* Package Level Thermal Management */
 288 #define CPUID_DSPM_HWP  __BIT(7)        /* HWP */
 289 #define CPUID_DSPM_HWP_NOTIFY __BIT(8)  /* HWP Notification */
 290 #define CPUID_DSPM_HWP_ACTWIN  __BIT(9) /* HWP Activity Window */
 291 #define CPUID_DSPM_HWP_EPP __BIT(10)    /* HWP Energy Performance Preference */
 292 #define CPUID_DSPM_HWP_PLR __BIT(11)    /* HWP Package Level Request */
 293 #define CPUID_DSPM_HDC  __BIT(13)       /* HDC */
 294
 295 #define CPUID_DSPM_FLAGS        "\20" \
 296         "\1" "DTS"      "\2" "IDA"      "\3" "ARAT"                     \
 297         "\5" "PLN"      "\6" "ECMD"     "\7" "PTM"      "\10" "HWP"     \
 298         "\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \
 299                         "\16" "HDC"
 300
 301 /*
 302  * Intel Digital Thermal Sensor and
 303  * Power Management, Fn0000_0006 - %ecx.
 304  */
 305 #define CPUID_DSPM_HWF  0x00000001      /* MSR_APERF/MSR_MPERF available */
 306 #define CPUID_DSPM_EPB  0x00000008      /* Energy Performance Bias */
 307
 308 #define CPUID_DSPM_FLAGS1       "\20" "\1" "HWF" "\4" "EPB"
 309
 310 /*
 311  * Intel Structured Extended Feature leaf Fn0000_0007
 312  * %eax == 0: Subleaf 0
 313  *      %eax: The Maximun input value for supported subleaf.
 314  *      %ebx: Feature bits.
 315  *      %ecx: Feature bits.
 316  */
 317
 318 /* %ebx */
 319 #define CPUID_SEF_FSGSBASE      __BIT(0)
 320 #define CPUID_SEF_TSC_ADJUST    __BIT(1)
 321 #define CPUID_SEF_BMI1          __BIT(3)
 322 #define CPUID_SEF_HLE           __BIT(4)
 323 #define CPUID_SEF_AVX2          __BIT(5)
 324 #define CPUID_SEF_SMEP          __BIT(7)
 325 #define CPUID_SEF_BMI2          __BIT(8)
 326 #define CPUID_SEF_ERMS          __BIT(9)
 327 #define CPUID_SEF_INVPCID       __BIT(10)
 328 #define CPUID_SEF_RTM           __BIT(11)
 329 #define CPUID_SEF_QM            __BIT(12)
 330 #define CPUID_SEF_FPUCSDS       __BIT(13)
 331 #define CPUID_SEF_MPX           __BIT(14)
 332 #define CPUID_SEF_PQE           __BIT(15)
 333 #define CPUID_SEF_AVX512F       __BIT(16)
 334 #define CPUID_SEF_RDSEED        __BIT(18)
 335 #define CPUID_SEF_ADX           __BIT(19)
 336 #define CPUID_SEF_SMAP          __BIT(20)
 337 #define CPUID_SEF_PT            __BIT(25)
 338 #define CPUID_SEF_AVX512PF      __BIT(26)
 339 #define CPUID_SEF_AVX512ER      __BIT(27)
 340 #define CPUID_SEF_AVX512CD      __BIT(28)
 341 #define CPUID_SEF_SHA           __BIT(29)
 342
 343 #define CPUID_SEF_FLAGS "\20" \
 344         "\1" "FSGSBASE" "\2" "TSCADJUST"                "\4" "BMI1"     \
 345         "\5" "HLE"      "\6" "AVX2"                     "\10" "SMEP"    \
 346         "\11" "BMI2"    "\12" "ERMS"    "\13" "INVPCID" "\14" "RTM"     \
 347         "\15" "QM"      "\16" "FPUCSDS" "\17" "MPX"     "\20" "PQE"     \
 348         "\21" "AVX512F"                 "\23" "RDSEED"  "\24" "ADX"     \
 349         "\25" "SMAP"                                                    \
 350                         "\32" "PT"      "\33" "AVX512PF""\34" "AVX512ER"\
 351         "\35" "AVX512CD""\36" "SHA"
 352
 353 /* %ecx */
 354 #define CPUID_SEF_PREFETCHWT1   __BIT(0)
 355 #define CPUID_SEF_PKU           __BIT(3)
 356 #define CPUID_SEF_OSPKE         __BIT(4)
 357
 358 #define CPUID_SEF_FLAGS1        "\20" \
 359         "\1" "PREFETCHWT1"                              "\4" "PKU"      \
 360         "\5" "OSPKE"
 361
 362 /*
 363  * CPUID Processor extended state Enumeration Fn0000000d
 364  *
 365  * %ecx == 0: supported features info:
 366  *      %eax: Valid bits of lower 32bits of XCR0
 367  *      %ebx: Maximum save area size for features enabled in XCR0
 368  *      %ecx: Maximim save area size for all cpu features
 369  *      %edx: Valid bits of upper 32bits of XCR0
 370  *
 371  * %ecx == 1:
 372  *      %eax: Bit 0 => xsaveopt instruction avalaible (sandy bridge onwards)
 373  *      %ebx: Save area size for features enabled by XCR0 | IA32_XSS
 374  *      %ecx: Valid bits of lower 32bits of IA32_XSS
 375  *      %edx: Valid bits of upper 32bits of IA32_XSS
 376  *
 377  * %ecx >= 2: Save area details for XCR0 bit n
 378  *      %eax: size of save area for this feature
 379  *      %ebx: offset of save area for this feature
 380  *      %ecx, %edx: reserved
 381  *      All of %eax, %ebx, %ecx and %edx are zero for unsupported features.
 382  */
 383
 384 /* %ecx=1 %eax */
 385 #define CPUID_PES1_XSAVEOPT     0x00000001      /* xsaveopt instruction */
 386 #define CPUID_PES1_XSAVEC       0x00000002      /* xsavec & compacted XRSTOR */
 387 #define CPUID_PES1_XGETBV       0x00000004      /* xgetbv with ECX = 1 */
 388 #define CPUID_PES1_XSAVES       0x00000008      /* xsaves/xrstors, IA32_XSS */
 389
 390 #define CPUID_PES1_FLAGS        "\20" \
 391         "\1" "XSAVEOPT" "\2" "XSAVEC"   "\3" "XGETBV"   "\4" "XSAVES"
 392
 393 /* Intel Fn80000001 extended features - %edx */
 394 #define CPUID_SYSCALL   0x00000800      /* SYSCALL/SYSRET */
 395 #define CPUID_XD        0x00100000      /* Execute Disable (like CPUID_NOX) */
 396 #define CPUID_P1GB      0x04000000      /* 1GB Large Page Support */
 397 #define CPUID_RDTSCP    0x08000000      /* Read TSC Pair Instruction */
 398 #define CPUID_EM64T     0x20000000      /* Intel EM64T */
 399
 400 #define CPUID_INTEL_EXT_FLAGS   "\20" \
 401         "\14" "SYSCALL/SYSRET"  "\25" "XD"      "\33" "P1GB" \
 402         "\34" "RDTSCP"  "\36" "EM64T"
 403
 404 /* Intel Fn80000001 extended features - %ecx */
 405 #define CPUID_LAHF      0x00000001      /* LAHF/SAHF in IA-32e mode, 64bit sub*/
 406                 /*      0x00000020 */   /* LZCNT. Same as AMD's CPUID_LZCNT */
 407 #define CPUID_PREFETCHW 0x00000100      /* PREFETCHW */
 408
 409 #define CPUID_INTEL_FLAGS4      "\20"                           \
 410         "\1" "LAHF"     "\02" "B01"     "\03" "B02"             \
 411                         "\06" "LZCNT"                           \
 412         "\11" "PREFETCHW"
 413
 414 /* AMD/VIA Fn80000001 extended features - %edx */
 415 /*      CPUID_SYSCALL                      SYSCALL/SYSRET */
 416 #define CPUID_MPC       0x00080000      /* Multiprocessing Capable */
 417 #define CPUID_NOX       0x00100000      /* No Execute Page Protection */
 418 #define CPUID_MMXX      0x00400000      /* AMD MMX Extensions */
 419 #define CPUID_FFXSR     0x02000000      /* FXSAVE/FXSTOR Extensions */
 420 /*      CPUID_P1GB                         1GB Large Page Support */
 421 /*      CPUID_RDTSCP                       Read TSC Pair Instruction */
 422 /*      CPUID_EM64T                        Long mode */
 423 #define CPUID_3DNOW2    0x40000000      /* 3DNow! Instruction Extension */
 424 #define CPUID_3DNOW     0x80000000      /* 3DNow! Instructions */
 425
 426 #define CPUID_EXT_FLAGS "\20" \
 427         "\14" "SYSCALL/SYSRET"          "\24" "MPC"     "\25" "NOX" \
 428         "\27" "MMXX"    "\32" "FFXSR"   "\33" "P1GB"    "\34" "RDTSCP" \
 429         "\36" "LONG"    "\37" "3DNOW2"  "\40" "3DNOW"
 430
 431 /* AMD Fn80000001 extended features - %ecx */
 432 /*      CPUID_LAHF                         LAHF/SAHF instruction */
 433 #define CPUID_CMPLEGACY 0x00000002      /* Compare Legacy */
 434 #define CPUID_SVM       0x00000004      /* Secure Virtual Machine */
 435 #define CPUID_EAPIC     0x00000008      /* Extended APIC space */
 436 #define CPUID_ALTMOVCR0 0x00000010      /* Lock Mov Cr0 */
 437 #define CPUID_LZCNT     0x00000020      /* LZCNT instruction */
 438 #define CPUID_SSE4A     0x00000040      /* SSE4A instruction set */
 439 #define CPUID_MISALIGNSSE 0x00000080    /* Misaligned SSE */
 440 #define CPUID_3DNOWPF   0x00000100      /* 3DNow Prefetch */
 441 #define CPUID_OSVW      0x00000200      /* OS visible workarounds */
 442 #define CPUID_IBS       0x00000400      /* Instruction Based Sampling */
 443 #define CPUID_XOP       0x00000800      /* XOP instruction set */
 444 #define CPUID_SKINIT    0x00001000      /* SKINIT */
 445 #define CPUID_WDT       0x00002000      /* watchdog timer support */
 446 #define CPUID_LWP       0x00008000      /* Light Weight Profiling */
 447 #define CPUID_FMA4      0x00010000      /* FMA4 instructions */
 448 #define CPUID_NODEID    0x00080000      /* NodeID MSR available*/
 449 #define CPUID_TBM       0x00200000      /* TBM instructions */
 450 #define CPUID_TOPOEXT   0x00400000      /* cpuid Topology Extension */
 451 #define CPUID_PCEC      0x00800000      /* Perf Ctr Ext Core */
 452 #define CPUID_PCENB     0x01000000      /* Perf Ctr Ext NB */
 453 #define CPUID_SPM       0x02000000      /* Stream Perf Mon */
 454 #define CPUID_DBE       0x04000000      /* Data Breakpoint Extension */
 455 #define CPUID_PTSC      0x08000000      /* PerfTsc */
 456
 457 #define CPUID_AMD_FLAGS4        "\20" \
 458         "\1" "LAHF"     "\2" "CMPLEGACY" "\3" "SVM"     "\4" "EAPIC" \
 459         "\5" "ALTMOVCR0" "\6" "LZCNT"   "\7" "SSE4A"    "\10" "MISALIGNSSE" \
 460         "\11" "3DNOWPREFETCH" \
 461                         "\12" "OSVW"    "\13" "IBS"     "\14" "XOP" \
 462         "\15" "SKINIT"  "\16" "WDT"     "\17" "B14"     "\20" "LWP" \
 463         "\21" "FMA4"    "\22" "B17"     "\23" "B18"     "\24" "NodeID" \
 464         "\25" "B20"     "\26" "TBM"     "\27" "TopoExt" "\30" "PCExtC" \
 465         "\31" "PCExtNB" "\32" "StrmPM"  "\33" "DBExt"   "\34" "PerfTsc" \
 466         "\35" "B28"     "\36" "B29"     "\37" "B30"     "\40" "B31"
 467
 468 /*
 469  * AMD Advanced Power Management
 470  * CPUID Fn8000_0007 %edx
 471  */
 472 #define CPUID_APM_TS    0x00000001      /* Temperature Sensor */
 473 #define CPUID_APM_FID   0x00000002      /* Frequency ID control */
 474 #define CPUID_APM_VID   0x00000004      /* Voltage ID control */
 475 #define CPUID_APM_TTP   0x00000008      /* THERMTRIP (PCI F3xE4 register) */
 476 #define CPUID_APM_HTC   0x00000010      /* Hardware thermal control (HTC) */
 477 #define CPUID_APM_STC   0x00000020      /* Software thermal control (STC) */
 478 #define CPUID_APM_100   0x00000040      /* 100MHz multiplier control */
 479 #define CPUID_APM_HWP   0x00000080      /* HW P-State control */
 480 #define CPUID_APM_TSC   0x00000100      /* TSC invariant */
 481 #define CPUID_APM_CPB   0x00000200      /* Core performance boost */
 482 #define CPUID_APM_EFF   0x00000400      /* Effective Frequency (read-only) */
 483
 484 #define CPUID_APM_FLAGS         "\20" \
 485         "\1" "TS"       "\2" "FID"      "\3" "VID"      "\4" "TTP" \
 486         "\5" "HTC"      "\6" "STC"      "\7" "100"      "\10" "HWP" \
 487         "\11" "TSC"     "\12" "CPB"     "\13" "EffFreq" "\14" "B11" \
 488         "\15" "B12"
 489
 490 /* AMD Fn8000000a %edx features (SVM features) */
 491 #define CPUID_AMD_SVM_NP                0x00000001
 492 #define CPUID_AMD_SVM_LbrVirt           0x00000002
 493 #define CPUID_AMD_SVM_SVML              0x00000004
 494 #define CPUID_AMD_SVM_NRIPS             0x00000008
 495 #define CPUID_AMD_SVM_TSCRateCtrl       0x00000010
 496 #define CPUID_AMD_SVM_VMCBCleanBits     0x00000020
 497 #define CPUID_AMD_SVM_FlushByASID       0x00000040
 498 #define CPUID_AMD_SVM_DecodeAssist      0x00000080
 499 #define CPUID_AMD_SVM_PauseFilter       0x00000400
 500 #define CPUID_AMD_SVM_FLAGS      "\20" \
 501         "\1" "NP"       "\2" "LbrVirt"  "\3" "SVML"     "\4" "NRIPS" \
 502         "\5" "TSCRate"  "\6" "VMCBCleanBits" \
 503                 "\7" "FlushByASID"      "\10" "DecodeAssist" \
 504         "\11" "B08"     "\12" "B09"     "\13" "PauseFilter" "\14" "B11" \
 505         "\15" "B12"     "\16" "B13"     "\17" "B17"     "\20" "B18" \
 506         "\21" "B19"
 507
 508 /*
 509  * Centaur Extended Feature flags
 510  */
 511 #define CPUID_VIA_HAS_RNG       0x00000004      /* Random number generator */
 512 #define CPUID_VIA_DO_RNG        0x00000008
 513 #define CPUID_VIA_HAS_ACE       0x00000040      /* AES Encryption */
 514 #define CPUID_VIA_DO_ACE        0x00000080
 515 #define CPUID_VIA_HAS_ACE2      0x00000100      /* AES+CTR instructions */
 516 #define CPUID_VIA_DO_ACE2       0x00000200
 517 #define CPUID_VIA_HAS_PHE       0x00000400      /* SHA1+SHA256 HMAC */
 518 #define CPUID_VIA_DO_PHE        0x00000800
 519 #define CPUID_VIA_HAS_PMM       0x00001000      /* RSA Instructions */
 520 #define CPUID_VIA_DO_PMM        0x00002000
 521
 522 #define CPUID_FLAGS_PADLOCK     "\20" \
 523         "\3" "RNG"      "\7" "AES"      "\11" "AES/CTR" "\13" "SHA1/SHA256" \
 524         "\15" "RSA"
 525
 526 /*
 527  * Model-specific registers for the i386 family
 528  */
 529 #define MSR_P5_MC_ADDR          0x000   /* P5 only */
 530 #define MSR_P5_MC_TYPE          0x001   /* P5 only */
 531 #define MSR_TSC                 0x010
 532 #define MSR_CESR                0x011   /* P5 only (trap on P6) */
 533 #define MSR_CTR0                0x012   /* P5 only (trap on P6) */
 534 #define MSR_CTR1                0x013   /* P5 only (trap on P6) */
 535 #define MSR_IA32_PLATFORM_ID    0x017
 536 #define MSR_APICBASE            0x01b
 537 #define MSR_EBL_CR_POWERON      0x02a
 538 #define MSR_EBC_FREQUENCY_ID    0x02c   /* PIV only */
 539 #define MSR_TEST_CTL            0x033
 540 #define MSR_BIOS_UPDT_TRIG      0x079
 541 #define MSR_BBL_CR_D0           0x088   /* PII+ only */
 542 #define MSR_BBL_CR_D1           0x089   /* PII+ only */
 543 #define MSR_BBL_CR_D2           0x08a   /* PII+ only */
 544 #define MSR_BIOS_SIGN           0x08b
 545 #define MSR_PERFCTR0            0x0c1
 546 #define MSR_PERFCTR1            0x0c2
 547 #define MSR_FSB_FREQ            0x0cd   /* Core Duo/Solo only */
 548 #define MSR_MPERF               0x0e7
 549 #define MSR_APERF               0x0e8
 550 #define MSR_IA32_EXT_CONFIG     0x0ee   /* Undocumented. Core Solo/Duo only */
 551 #define MSR_MTRRcap             0x0fe
 552 #define MSR_BBL_CR_ADDR         0x116   /* PII+ only */
 553 #define MSR_BBL_CR_DECC         0x118   /* PII+ only */
 554 #define MSR_BBL_CR_CTL          0x119   /* PII+ only */
 555 #define MSR_BBL_CR_TRIG         0x11a   /* PII+ only */
 556 #define MSR_BBL_CR_BUSY         0x11b   /* PII+ only */
 557 #define MSR_BBL_CR_CTR3         0x11e   /* PII+ only */
 558 #define MSR_SYSENTER_CS         0x174   /* PII+ only */
 559 #define MSR_SYSENTER_ESP        0x175   /* PII+ only */
 560 #define MSR_SYSENTER_EIP        0x176   /* PII+ only */
 561 #define MSR_MCG_CAP             0x179
 562 #define MSR_MCG_STATUS          0x17a
 563 #define MSR_MCG_CTL             0x17b
 564 #define MSR_EVNTSEL0            0x186
 565 #define MSR_EVNTSEL1            0x187
 566 #define MSR_PERF_STATUS         0x198   /* Pentium M */
 567 #define MSR_PERF_CTL            0x199   /* Pentium M */
 568 #define MSR_THERM_CONTROL       0x19a
 569 #define MSR_THERM_INTERRUPT     0x19b
 570 #define MSR_THERM_STATUS        0x19c
 571 #define MSR_THERM2_CTL          0x19d   /* Pentium M */
 572 #define MSR_MISC_ENABLE         0x1a0
 573 #define MSR_TEMPERATURE_TARGET  0x1a2
 574 #define MSR_DEBUGCTLMSR         0x1d9
 575 #define MSR_LASTBRANCHFROMIP    0x1db
 576 #define MSR_LASTBRANCHTOIP      0x1dc
 577 #define MSR_LASTINTFROMIP       0x1dd
 578 #define MSR_LASTINTTOIP         0x1de
 579 #define MSR_ROB_CR_BKUPTMPDR6   0x1e0
 580 #define MSR_MTRRphysBase0       0x200
 581 #define MSR_MTRRphysMask0       0x201
 582 #define MSR_MTRRphysBase1       0x202
 583 #define MSR_MTRRphysMask1       0x203
 584 #define MSR_MTRRphysBase2       0x204
 585 #define MSR_MTRRphysMask2       0x205
 586 #define MSR_MTRRphysBase3       0x206
 587 #define MSR_MTRRphysMask3       0x207
 588 #define MSR_MTRRphysBase4       0x208
 589 #define MSR_MTRRphysMask4       0x209
 590 #define MSR_MTRRphysBase5       0x20a
 591 #define MSR_MTRRphysMask5       0x20b
 592 #define MSR_MTRRphysBase6       0x20c
 593 #define MSR_MTRRphysMask6       0x20d
 594 #define MSR_MTRRphysBase7       0x20e
 595 #define MSR_MTRRphysMask7       0x20f
 596 #define MSR_MTRRphysBase8       0x210
 597 #define MSR_MTRRphysMask8       0x211
 598 #define MSR_MTRRphysBase9       0x212
 599 #define MSR_MTRRphysMask9       0x213
 600 #define MSR_MTRRphysBase10      0x214
 601 #define MSR_MTRRphysMask10      0x215
 602 #define MSR_MTRRphysBase11      0x216
 603 #define MSR_MTRRphysMask11      0x217
 604 #define MSR_MTRRphysBase12      0x218
 605 #define MSR_MTRRphysMask12      0x219
 606 #define MSR_MTRRphysBase13      0x21a
 607 #define MSR_MTRRphysMask13      0x21b
 608 #define MSR_MTRRphysBase14      0x21c
 609 #define MSR_MTRRphysMask14      0x21d
 610 #define MSR_MTRRphysBase15      0x21e
 611 #define MSR_MTRRphysMask15      0x21f
 612 #define MSR_MTRRfix64K_00000    0x250
 613 #define MSR_MTRRfix16K_80000    0x258
 614 #define MSR_MTRRfix16K_A0000    0x259
 615 #define MSR_MTRRfix4K_C0000     0x268
 616 #define MSR_MTRRfix4K_C8000     0x269
 617 #define MSR_MTRRfix4K_D0000     0x26a
 618 #define MSR_MTRRfix4K_D8000     0x26b
 619 #define MSR_MTRRfix4K_E0000     0x26c
 620 #define MSR_MTRRfix4K_E8000     0x26d
 621 #define MSR_MTRRfix4K_F0000     0x26e
 622 #define MSR_MTRRfix4K_F8000     0x26f
 623 #define MSR_CR_PAT              0x277
 624 #define MSR_MTRRdefType         0x2ff
 625 #define MSR_MC0_CTL             0x400
 626 #define MSR_MC0_STATUS          0x401
 627 #define MSR_MC0_ADDR            0x402
 628 #define MSR_MC0_MISC            0x403
 629 #define MSR_MC1_CTL             0x404
 630 #define MSR_MC1_STATUS          0x405
 631 #define MSR_MC1_ADDR            0x406
 632 #define MSR_MC1_MISC            0x407
 633 #define MSR_MC2_CTL             0x408
 634 #define MSR_MC2_STATUS          0x409
 635 #define MSR_MC2_ADDR            0x40a
 636 #define MSR_MC2_MISC            0x40b
 637 #define MSR_MC4_CTL             0x40c
 638 #define MSR_MC4_STATUS          0x40d
 639 #define MSR_MC4_ADDR            0x40e
 640 #define MSR_MC4_MISC            0x40f
 641 #define MSR_MC3_CTL             0x410
 642 #define MSR_MC3_STATUS          0x411
 643 #define MSR_MC3_ADDR            0x412
 644 #define MSR_MC3_MISC            0x413
 645                                 /* 0x480 - 0x490 VMX */
 646
 647 /*
 648  * VIA "Nehemiah" MSRs
 649  */
 650 #define MSR_VIA_RNG             0x0000110b
 651 #define MSR_VIA_RNG_ENABLE      0x00000040
 652 #define MSR_VIA_RNG_NOISE_MASK  0x00000300
 653 #define MSR_VIA_RNG_NOISE_A     0x00000000
 654 #define MSR_VIA_RNG_NOISE_B     0x00000100
 655 #define MSR_VIA_RNG_2NOISE      0x00000300
 656 #define MSR_VIA_ACE             0x00001107
 657 #define MSR_VIA_ACE_ENABLE      0x10000000
 658
 659 /*
 660  * VIA "Eden" MSRs
 661  */
 662 #define MSR_VIA_FCR             MSR_VIA_ACE
 663
 664 /*
 665  * AMD K6/K7 MSRs.
 666  */
 667 #define MSR_K6_UWCCR            0xc0000085
 668 #define MSR_K7_EVNTSEL0         0xc0010000
 669 #define MSR_K7_EVNTSEL1         0xc0010001
 670 #define MSR_K7_EVNTSEL2         0xc0010002
 671 #define MSR_K7_EVNTSEL3         0xc0010003
 672 #define MSR_K7_PERFCTR0         0xc0010004
 673 #define MSR_K7_PERFCTR1         0xc0010005
 674 #define MSR_K7_PERFCTR2         0xc0010006
 675 #define MSR_K7_PERFCTR3         0xc0010007
 676
 677 /*
 678  * AMD K8 (Opteron) MSRs.
 679  */
 680 #define MSR_SYSCFG      0xc0000010
 681
 682 #define MSR_EFER        0xc0000080              /* Extended feature enable */
 683 #define         EFER_SCE                0x00000001      /* SYSCALL extension */
 684 #define         EFER_LME                0x00000100      /* Long Mode Active */
 685 #define         EFER_LMA                0x00000400      /* Long Mode Enabled */
 686 #define         EFER_NXE                0x00000800      /* No-Execute Enabled */
 687
 688 #define MSR_STAR        0xc0000081              /* 32 bit syscall gate addr */
 689 #define MSR_LSTAR       0xc0000082              /* 64 bit syscall gate addr */
 690 #define MSR_CSTAR       0xc0000083              /* compat syscall gate addr */
 691 #define MSR_SFMASK      0xc0000084              /* flags to clear on syscall */
 692
 693 #define MSR_FSBASE      0xc0000100              /* 64bit offset for fs: */
 694 #define MSR_GSBASE      0xc0000101              /* 64bit offset for gs: */
 695 #define MSR_KERNELGSBASE 0xc0000102             /* storage for swapgs ins */
 696
 697 #define MSR_VMCR        0xc0010114      /* Virtual Machine Control Register */
 698 #define         VMCR_DPD        0x00000001      /* Debug port disable */
 699 #define         VMCR_RINIT      0x00000002      /* intercept init */
 700 #define         VMCR_DISA20     0x00000004      /* Disable A20 masking */
 701 #define         VMCR_LOCK       0x00000008      /* SVM Lock */
 702 #define         VMCR_SVMED      0x00000010      /* SVME Disable */
 703 #define MSR_SVMLOCK     0xc0010118      /* SVM Lock key */
 704
 705 /*
 706  * These require a 'passcode' for access.  See cpufunc.h.
 707  */
 708 #define MSR_HWCR        0xc0010015
 709 #define         HWCR_TLBCACHEDIS        0x00000008
 710 #define         HWCR_FFDIS              0x00000040
 711
 712 #define MSR_NB_CFG      0xc001001f
 713 #define         NB_CFG_DISIOREQLOCK     0x0000000000000008ULL
 714 #define         NB_CFG_DISDATMSK        0x0000001000000000ULL
 715 #define         NB_CFG_INITAPICCPUIDLO  (1ULL << 54)
 716
 717 #define MSR_LS_CFG      0xc0011020
 718 #define         LS_CFG_DIS_LS2_SQUISH   0x02000000
 719
 720 #define MSR_IC_CFG      0xc0011021
 721 #define         IC_CFG_DIS_SEQ_PREFETCH 0x00000800
 722
 723 #define MSR_DC_CFG      0xc0011022
 724 #define         DC_CFG_DIS_CNV_WC_SSO   0x00000008
 725 #define         DC_CFG_DIS_SMC_CHK_BUF  0x00000400
 726 #define         DC_CFG_ERRATA_261       0x01000000
 727
 728 #define MSR_BU_CFG      0xc0011023
 729 #define         BU_CFG_ERRATA_298       0x0000000000000002ULL
 730 #define         BU_CFG_ERRATA_254       0x0000000000200000ULL
 731 #define         BU_CFG_ERRATA_309       0x0000000000800000ULL
 732 #define         BU_CFG_THRL2IDXCMPDIS   0x0000080000000000ULL
 733 #define         BU_CFG_WBPFSMCCHKDIS    0x0000200000000000ULL
 734 #define         BU_CFG_WBENHWSBDIS      0x0001000000000000ULL
 735
 736 #define MSR_DE_CFG      0xc0011029
 737 #define         DE_CFG_ERRATA_721       0x00000001
 738
 739 /* AMD Family10h MSRs */
 740 #define MSR_OSVW_ID_LENGTH              0xc0010140
 741 #define MSR_OSVW_STATUS                 0xc0010141
 742 #define MSR_UCODE_AMD_PATCHLEVEL        0x0000008b
 743 #define MSR_UCODE_AMD_PATCHLOADER       0xc0010020
 744
 745 /* X86 MSRs */
 746 #define MSR_RDTSCP_AUX                  0xc0000103
 747
 748 /*
 749  * Constants related to MTRRs
 750  */
 751 #define MTRR_N64K               8       /* numbers of fixed-size entries */
 752 #define MTRR_N16K               16
 753 #define MTRR_N4K                64
 754
 755 /*
 756  * the following four 3-byte registers control the non-cacheable regions.
 757  * These registers must be written as three separate bytes.
 758  *
 759  * NCRx+0: A31-A24 of starting address
 760  * NCRx+1: A23-A16 of starting address
 761  * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
 762  *
 763  * The non-cacheable region's starting address must be aligned to the
 764  * size indicated by the NCR_SIZE_xx field.
 765  */
 766 #define NCR1    0xc4
 767 #define NCR2    0xc7
 768 #define NCR3    0xca
 769 #define NCR4    0xcd
 770
 771 #define NCR_SIZE_0K     0
 772 #define NCR_SIZE_4K     1
 773 #define NCR_SIZE_8K     2
 774 #define NCR_SIZE_16K    3
 775 #define NCR_SIZE_32K    4
 776 #define NCR_SIZE_64K    5
 777 #define NCR_SIZE_128K   6
 778 #define NCR_SIZE_256K   7
 779 #define NCR_SIZE_512K   8
 780 #define NCR_SIZE_1M     9
 781 #define NCR_SIZE_2M     10
 782 #define NCR_SIZE_4M     11
 783 #define NCR_SIZE_8M     12
 784 #define NCR_SIZE_16M    13
 785 #define NCR_SIZE_32M    14
 786 #define NCR_SIZE_4G     15
 787
 788 /*
 789  * Performance monitor events.
 790  *
 791  * Note that 586-class and 686-class CPUs have different performance
 792  * monitors available, and they are accessed differently:
 793  *
 794  *      686-class: `rdpmc' instruction
 795  *      586-class: `rdmsr' instruction, CESR MSR
 796  *
 797  * The descriptions of these events are too lenghy to include here.
 798  * See Appendix A of "Intel Architecture Software Developer's
 799  * Manual, Volume 3: System Programming" for more information.
 800  */
 801
 802 /*
 803  * 586-class CESR MSR format.  Lower 16 bits is CTR0, upper 16 bits
 804  * is CTR1.
 805  */
 806
 807 #define PMC5_CESR_EVENT                 0x003f
 808 #define PMC5_CESR_OS                    0x0040
 809 #define PMC5_CESR_USR                   0x0080
 810 #define PMC5_CESR_E                     0x0100
 811 #define PMC5_CESR_P                     0x0200
 812
 813 #define PMC5_DATA_READ                  0x00
 814 #define PMC5_DATA_WRITE                 0x01
 815 #define PMC5_DATA_TLB_MISS              0x02
 816 #define PMC5_DATA_READ_MISS             0x03
 817 #define PMC5_DATA_WRITE_MISS            0x04
 818 #define PMC5_WRITE_M_E                  0x05
 819 #define PMC5_DATA_LINES_WBACK           0x06
 820 #define PMC5_DATA_CACHE_SNOOP           0x07
 821 #define PMC5_DATA_CACHE_SNOOP_HIT       0x08
 822 #define PMC5_MEM_ACCESS_BOTH_PIPES      0x09
 823 #define PMC5_BANK_CONFLICTS             0x0a
 824 #define PMC5_MISALIGNED_DATA            0x0b
 825 #define PMC5_INST_READ                  0x0c
 826 #define PMC5_INST_TLB_MISS              0x0d
 827 #define PMC5_INST_CACHE_MISS            0x0e
 828 #define PMC5_SEGMENT_REG_LOAD           0x0f
 829 #define PMC5_BRANCHES                   0x12
 830 #define PMC5_BTB_HITS                   0x13
 831 #define PMC5_BRANCH_TAKEN               0x14
 832 #define PMC5_PIPELINE_FLUSH             0x15
 833 #define PMC5_INST_EXECUTED              0x16
 834 #define PMC5_INST_EXECUTED_V_PIPE       0x17
 835 #define PMC5_BUS_UTILIZATION            0x18
 836 #define PMC5_WRITE_BACKUP_STALL         0x19
 837 #define PMC5_DATA_READ_STALL            0x1a
 838 #define PMC5_WRITE_E_M_STALL            0x1b
 839 #define PMC5_LOCKED_BUS                 0x1c
 840 #define PMC5_IO_CYCLE                   0x1d
 841 #define PMC5_NONCACHE_MEM_READ          0x1e
 842 #define PMC5_AGI_STALL                  0x1f
 843 #define PMC5_FLOPS                      0x22
 844 #define PMC5_BP0_MATCH                  0x23
 845 #define PMC5_BP1_MATCH                  0x24
 846 #define PMC5_BP2_MATCH                  0x25
 847 #define PMC5_BP3_MATCH                  0x26
 848 #define PMC5_HARDWARE_INTR              0x27
 849 #define PMC5_DATA_RW                    0x28
 850 #define PMC5_DATA_RW_MISS               0x29
 851
 852 /*
 853  * 686-class Event Selector MSR format.
 854  */
 855
 856 #define PMC6_EVTSEL_EVENT               0x000000ff
 857 #define PMC6_EVTSEL_UNIT                0x0000ff00
 858 #define PMC6_EVTSEL_UNIT_SHIFT          8
 859 #define PMC6_EVTSEL_USR                 (1 << 16)
 860 #define PMC6_EVTSEL_OS                  (1 << 17)
 861 #define PMC6_EVTSEL_E                   (1 << 18)
 862 #define PMC6_EVTSEL_PC                  (1 << 19)
 863 #define PMC6_EVTSEL_INT                 (1 << 20)
 864 #define PMC6_EVTSEL_EN                  (1 << 22)       /* PerfEvtSel0 only */
 865 #define PMC6_EVTSEL_INV                 (1 << 23)
 866 #define PMC6_EVTSEL_COUNTER_MASK        0xff000000
 867 #define PMC6_EVTSEL_COUNTER_MASK_SHIFT  24
 868
 869 /* Data Cache Unit */
 870 #define PMC6_DATA_MEM_REFS              0x43
 871 #define PMC6_DCU_LINES_IN               0x45
 872 #define PMC6_DCU_M_LINES_IN             0x46
 873 #define PMC6_DCU_M_LINES_OUT            0x47
 874 #define PMC6_DCU_MISS_OUTSTANDING       0x48
 875
 876 /* Instruction Fetch Unit */
 877 #define PMC6_IFU_IFETCH                 0x80
 878 #define PMC6_IFU_IFETCH_MISS            0x81
 879 #define PMC6_ITLB_MISS                  0x85
 880 #define PMC6_IFU_MEM_STALL              0x86
 881 #define PMC6_ILD_STALL                  0x87
 882
 883 /* L2 Cache */
 884 #define PMC6_L2_IFETCH                  0x28
 885 #define PMC6_L2_LD                      0x29
 886 #define PMC6_L2_ST                      0x2a
 887 #define PMC6_L2_LINES_IN                0x24
 888 #define PMC6_L2_LINES_OUT               0x26
 889 #define PMC6_L2_M_LINES_INM             0x25
 890 #define PMC6_L2_M_LINES_OUTM            0x27
 891 #define PMC6_L2_RQSTS                   0x2e
 892 #define PMC6_L2_ADS                     0x21
 893 #define PMC6_L2_DBUS_BUSY               0x22
 894 #define PMC6_L2_DBUS_BUSY_RD            0x23
 895
 896 /* External Bus Logic */
 897 #define PMC6_BUS_DRDY_CLOCKS            0x62
 898 #define PMC6_BUS_LOCK_CLOCKS            0x63
 899 #define PMC6_BUS_REQ_OUTSTANDING        0x60
 900 #define PMC6_BUS_TRAN_BRD               0x65
 901 #define PMC6_BUS_TRAN_RFO               0x66
 902 #define PMC6_BUS_TRANS_WB               0x67
 903 #define PMC6_BUS_TRAN_IFETCH            0x68
 904 #define PMC6_BUS_TRAN_INVAL             0x69
 905 #define PMC6_BUS_TRAN_PWR               0x6a
 906 #define PMC6_BUS_TRANS_P                0x6b
 907 #define PMC6_BUS_TRANS_IO               0x6c
 908 #define PMC6_BUS_TRAN_DEF               0x6d
 909 #define PMC6_BUS_TRAN_BURST             0x6e
 910 #define PMC6_BUS_TRAN_ANY               0x70
 911 #define PMC6_BUS_TRAN_MEM               0x6f
 912 #define PMC6_BUS_DATA_RCV               0x64
 913 #define PMC6_BUS_BNR_DRV                0x61
 914 #define PMC6_BUS_HIT_DRV                0x7a
 915 #define PMC6_BUS_HITM_DRDV              0x7b
 916 #define PMC6_BUS_SNOOP_STALL            0x7e
 917
 918 /* Floating Point Unit */
 919 #define PMC6_FLOPS                      0xc1
 920 #define PMC6_FP_COMP_OPS_EXE            0x10
 921 #define PMC6_FP_ASSIST                  0x11
 922 #define PMC6_MUL                        0x12
 923 #define PMC6_DIV                        0x12
 924 #define PMC6_CYCLES_DIV_BUSY            0x14
 925
 926 /* Memory Ordering */
 927 #define PMC6_LD_BLOCKS                  0x03
 928 #define PMC6_SB_DRAINS                  0x04
 929 #define PMC6_MISALIGN_MEM_REF           0x05
 930 #define PMC6_EMON_KNI_PREF_DISPATCHED   0x07    /* P-III only */
 931 #define PMC6_EMON_KNI_PREF_MISS         0x4b    /* P-III only */
 932
 933 /* Instruction Decoding and Retirement */
 934 #define PMC6_INST_RETIRED               0xc0
 935 #define PMC6_UOPS_RETIRED               0xc2
 936 #define PMC6_INST_DECODED               0xd0
 937 #define PMC6_EMON_KNI_INST_RETIRED      0xd8
 938 #define PMC6_EMON_KNI_COMP_INST_RET     0xd9
 939
 940 /* Interrupts */
 941 #define PMC6_HW_INT_RX                  0xc8
 942 #define PMC6_CYCLES_INT_MASKED          0xc6
 943 #define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7
 944
 945 /* Branches */
 946 #define PMC6_BR_INST_RETIRED            0xc4
 947 #define PMC6_BR_MISS_PRED_RETIRED       0xc5
 948 #define PMC6_BR_TAKEN_RETIRED           0xc9
 949 #define PMC6_BR_MISS_PRED_TAKEN_RET     0xca
 950 #define PMC6_BR_INST_DECODED            0xe0
 951 #define PMC6_BTB_MISSES                 0xe2
 952 #define PMC6_BR_BOGUS                   0xe4
 953 #define PMC6_BACLEARS                   0xe6
 954
 955 /* Stalls */
 956 #define PMC6_RESOURCE_STALLS            0xa2
 957 #define PMC6_PARTIAL_RAT_STALLS         0xd2
 958
 959 /* Segment Register Loads */
 960 #define PMC6_SEGMENT_REG_LOADS          0x06
 961
 962 /* Clocks */
 963 #define PMC6_CPU_CLK_UNHALTED           0x79
 964
 965 /* MMX Unit */
 966 #define PMC6_MMX_INSTR_EXEC             0xb0    /* Celeron, P-II, P-IIX only */
 967 #define PMC6_MMX_SAT_INSTR_EXEC         0xb1    /* P-II and P-III only */
 968 #define PMC6_MMX_UOPS_EXEC              0xb2    /* P-II and P-III only */
 969 #define PMC6_MMX_INSTR_TYPE_EXEC        0xb3    /* P-II and P-III only */
 970 #define PMC6_FP_MMX_TRANS               0xcc    /* P-II and P-III only */
 971 #define PMC6_MMX_ASSIST                 0xcd    /* P-II and P-III only */
 972 #define PMC6_MMX_INSTR_RET              0xc3    /* P-II only */
 973
 974 /* Segment Register Renaming */
 975 #define PMC6_SEG_RENAME_STALLS          0xd4    /* P-II and P-III only */
 976 #define PMC6_SEG_REG_RENAMES            0xd5    /* P-II and P-III only */
 977 #define PMC6_RET_SEG_RENAMES            0xd6    /* P-II and P-III only */
 978
 979 /*
 980  * AMD K7 Event Selector MSR format.
 981  */
 982
 983 #define K7_EVTSEL_EVENT                 0x000000ff
 984 #define K7_EVTSEL_UNIT                  0x0000ff00
 985 #define K7_EVTSEL_UNIT_SHIFT            8
 986 #define K7_EVTSEL_USR                   (1 << 16)
 987 #define K7_EVTSEL_OS                    (1 << 17)
 988 #define K7_EVTSEL_E                     (1 << 18)
 989 #define K7_EVTSEL_PC                    (1 << 19)
 990 #define K7_EVTSEL_INT                   (1 << 20)
 991 #define K7_EVTSEL_EN                    (1 << 22)
 992 #define K7_EVTSEL_INV                   (1 << 23)
 993 #define K7_EVTSEL_COUNTER_MASK          0xff000000
 994 #define K7_EVTSEL_COUNTER_MASK_SHIFT    24
 995
 996 /* Segment Register Loads */
 997 #define K7_SEGMENT_REG_LOADS            0x20
 998
 999 #define K7_STORES_TO_ACTIVE_INST_STREAM 0x21
1000
1001 /* Data Cache Unit */
1002 #define K7_DATA_CACHE_ACCESS            0x40
1003 #define K7_DATA_CACHE_MISS              0x41
1004 #define K7_DATA_CACHE_REFILL            0x42
1005 #define K7_DATA_CACHE_REFILL_SYSTEM     0x43
1006 #define K7_DATA_CACHE_WBACK             0x44
1007 #define K7_L2_DTLB_HIT                  0x45
1008 #define K7_L2_DTLB_MISS                 0x46
1009 #define K7_MISALIGNED_DATA_REF          0x47
1010 #define K7_SYSTEM_REQUEST               0x64
1011 #define K7_SYSTEM_REQUEST_TYPE          0x65
1012
1013 #define K7_SNOOP_HIT                    0x73
1014 #define K7_SINGLE_BIT_ECC_ERROR         0x74
1015 #define K7_CACHE_LINE_INVAL             0x75
1016 #define K7_CYCLES_PROCESSOR_IS_RUNNING  0x76
1017 #define K7_L2_REQUEST                   0x79
1018 #define K7_L2_REQUEST_BUSY              0x7a
1019
1020 /* Instruction Fetch Unit */
1021 #define K7_IFU_IFETCH                   0x80
1022 #define K7_IFU_IFETCH_MISS              0x81
1023 #define K7_IFU_REFILL_FROM_L2           0x82
1024 #define K7_IFU_REFILL_FROM_SYSTEM       0x83
1025 #define K7_ITLB_L1_MISS                 0x84
1026 #define K7_ITLB_L2_MISS                 0x85
1027 #define K7_SNOOP_RESYNC                 0x86
1028 #define K7_IFU_STALL                    0x87
1029
1030 #define K7_RETURN_STACK_HITS            0x88
1031 #define K7_RETURN_STACK_OVERFLOW        0x89
1032
1033 /* Retired */
1034 #define K7_RETIRED_INST                 0xc0
1035 #define K7_RETIRED_OPS                  0xc1
1036 #define K7_RETIRED_BRANCHES             0xc2
1037 #define K7_RETIRED_BRANCH_MISPREDICTED  0xc3
1038 #define K7_RETIRED_TAKEN_BRANCH         0xc4
1039 #define K7_RETIRED_TAKEN_BRANCH_MISPREDICTED    0xc5
1040 #define K7_RETIRED_FAR_CONTROL_TRANSFER 0xc6
1041 #define K7_RETIRED_RESYNC_BRANCH        0xc7
1042 #define K7_RETIRED_NEAR_RETURNS         0xc8
1043 #define K7_RETIRED_NEAR_RETURNS_MISPREDICTED    0xc9
1044 #define K7_RETIRED_INDIRECT_MISPREDICTED        0xca
1045
1046 /* Interrupts */
1047 #define K7_CYCLES_INT_MASKED            0xcd
1048 #define K7_CYCLES_INT_PENDING_AND_MASKED        0xce
1049 #define K7_HW_INTR_RECV                 0xcf
1050
1051 #define K7_INSTRUCTION_DECODER_EMPTY    0xd0
1052 #define K7_DISPATCH_STALLS              0xd1
1053 #define K7_BRANCH_ABORTS_TO_RETIRE      0xd2
1054 #define K7_SERIALIZE                    0xd3
1055 #define K7_SEGMENT_LOAD_STALL           0xd4
1056 #define K7_ICU_FULL                     0xd5
1057 #define K7_RESERVATION_STATIONS_FULL    0xd6
1058 #define K7_FPU_FULL                     0xd7
1059 #define K7_LS_FULL                      0xd8
1060 #define K7_ALL_QUIET_STALL              0xd9
1061 #define K7_FAR_TRANSFER_OR_RESYNC_BRANCH_PENDING        0xda
1062
1063 #define K7_BP0_MATCH                    0xdc
1064 #define K7_BP1_MATCH                    0xdd
1065 #define K7_BP2_MATCH                    0xde
1066 #define K7_BP3_MATCH                    0xdf