sys/dev/ic/comreg.h

   1 /*      $NetBSD: comreg.h,v 1.24 2015/03/07 15:49:20 macallan Exp $     */
   2
   3 /*-
   4  * Copyright (c) 1991 The Regents of the University of California.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. Neither the name of the University nor the names of its contributors
  16  *    may be used to endorse or promote products derived from this software
  17  *    without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  * SUCH DAMAGE.
  30  *
  31  *      @(#)comreg.h    7.2 (Berkeley) 5/9/91
  32  */
  33
  34 #include <dev/ic/ns16550reg.h>
  35
  36 #ifdef _KERNEL_OPT
  37 #include "opt_com.h"
  38 #endif
  39
  40 #define COM_FREQ        1843200 /* 16-bit baud rate divisor */
  41 #ifndef COM_TOLERANCE
  42 #define COM_TOLERANCE   30      /* baud rate tolerance, in 0.1% units */
  43 #endif
  44
  45 /* interrupt enable register */
  46 #define IER_ERXRDY      0x1     /* Enable receiver interrupt */
  47 #define IER_ETXRDY      0x2     /* Enable transmitter empty interrupt */
  48 #define IER_ERLS        0x4     /* Enable line status interrupt */
  49 #define IER_EMSC        0x8     /* Enable modem status interrupt */
  50 #define IER_ERTS        0x40    /* Enable RTS interrupt */
  51 #define IER_ECTS        0x80    /* Enable CTS interrupt */
  52 /* PXA2X0's ns16550 ports have extra bits in this register */
  53 /* Ingenic's got this one too */
  54 #define IER_ERXTOUT     0x10    /* Enable rx timeout interrupt */
  55 #define IER_EUART       0x40    /* Enable UART */
  56
  57 /* interrupt identification register */
  58 #define IIR_IMASK       0xf
  59 #define IIR_RXTOUT      0xc
  60 #define IIR_RLS         0x6     /* Line status change */
  61 #define IIR_RXRDY       0x4     /* Receiver ready */
  62 #define IIR_TXRDY       0x2     /* Transmitter ready */
  63 #define IIR_MLSC        0x0     /* Modem status */
  64 #define IIR_NOPEND      0x1     /* No pending interrupts */
  65 #define IIR_64B_FIFO    0x20    /* 64byte FIFO Enabled (16750) */
  66 #define IIR_FIFO_MASK   0xc0    /* set if FIFOs are enabled */
  67 #ifdef COM_16750
  68 #define IIR_BUSY        0x7     /* Busy indicator */
  69 #endif
  70
  71 /* fifo control register */
  72 #define FIFO_ENABLE     0x01    /* Turn the FIFO on */
  73 #define FIFO_RCV_RST    0x02    /* Reset RX FIFO */
  74 #define FIFO_XMT_RST    0x04    /* Reset TX FIFO */
  75 #define FIFO_DMA_MODE   0x08
  76 #define FIFO_UART_ON    0x10    /* JZ47xx only */
  77 #define FIFO_64B_ENABLE 0x20    /* 64byte FIFO Enable (16750) */
  78 #define FIFO_TRIGGER_1  0x00    /* Trigger RXRDY intr on 1 character */
  79 #define FIFO_TRIGGER_4  0x40    /* ibid 4 */
  80 #define FIFO_TRIGGER_8  0x80    /* ibid 8 */
  81 #define FIFO_TRIGGER_14 0xc0    /* ibid 14 */
  82
  83 /* enhanced feature register */
  84 #define EFR_AUTOCTS     0x80    /* Automatic CTS flow control */
  85 #define EFR_AUTORTS     0x40    /* Automatic RTS flow control */
  86 #define EFR_SPECIAL     0x20    /* Special char detect */
  87 #define EFR_EFCR        0x10    /* Enhanced function control bit */
  88 #define EFR_TXFLOWBOTH  0x0c    /* Automatic transmit XON/XOFF 1 and 2 */
  89 #define EFR_TXFLOW1     0x08    /* Automatic transmit XON/XOFF 1 */
  90 #define EFR_TXFLOW2     0x04    /* Automatic transmit XON/XOFF 2 */
  91 #define EFR_TXFLOWNONE  0x00    /* No automatic XON/XOFF transmit */
  92 #define EFR_RXFLOWBOTH  0x03    /* Automatic receive XON/XOFF 1 and 2 */
  93 #define EFR_RXFLOW1     0x02    /* Automatic receive XON/XOFF 1 */
  94 #define EFR_RXFLOW2     0x01    /* Automatic receive XON/XOFF 2 */
  95 #define EFR_RXFLOWNONE  0x00    /* No automatic XON/XOFF receive */
  96
  97 /* line control register */
  98 #define LCR_EERS        0xBF    /* Enable access to Enhanced Register Set */
  99 #define LCR_DLAB        0x80    /* Divisor latch access enable */
 100 #define LCR_SBREAK      0x40    /* Break Control */
 101 #define LCR_PZERO       0x38    /* Space parity */
 102 #define LCR_PONE        0x28    /* Mark parity */
 103 #define LCR_PEVEN       0x18    /* Even parity */
 104 #define LCR_PODD        0x08    /* Odd parity */
 105 #define LCR_PNONE       0x00    /* No parity */
 106 #define LCR_PENAB       0x08    /* XXX - low order bit of all parity */
 107 #define LCR_STOPB       0x04    /* 2 stop bits per serial word */
 108 #define LCR_8BITS       0x03    /* 8 bits per serial word */
 109 #define LCR_7BITS       0x02    /* 7 bits */
 110 #define LCR_6BITS       0x01    /* 6 bits */
 111 #define LCR_5BITS       0x00    /* 5 bits */
 112
 113 /* modem control register */
 114 #define MCR_PRESCALE    0x80    /* 16650/16950: Baud rate prescaler select */
 115 #define MCR_MDCE        0x80    /* Ingenic: modem control enable */
 116 #define MCR_TCR_TLR     0x40    /* OMAP: enables access to the TCR & TLR regs */
 117 #define MCR_FCM         0x40    /* Ingenic: 1 - hardware flow control */
 118 #define MCR_XONENABLE   0x20    /* OMAP XON_EN */
 119 #define MCR_AFE         0x20    /* tl16c750: Flow Control Enable */
 120 #define MCR_LOOPBACK    0x10    /* Loop test: echos from TX to RX */
 121 #define MCR_IENABLE     0x08    /* Out2: enables UART interrupts */
 122 #define MCR_DRS         0x04    /* Out1: resets some internal modems */
 123 #define MCR_RTS         0x02    /* Request To Send */
 124 #define MCR_DTR         0x01    /* Data Terminal Ready */
 125
 126 /* line status register */
 127 #define LSR_RCV_FIFO    0x80
 128 #define LSR_TSRE        0x40    /* Transmitter empty: byte sent */
 129 #define LSR_TXRDY       0x20    /* Transmitter buffer empty */
 130 #define LSR_BI          0x10    /* Break detected */
 131 #define LSR_FE          0x08    /* Framing error: bad stop bit */
 132 #define LSR_PE          0x04    /* Parity error */
 133 #define LSR_OE          0x02    /* Overrun, lost incoming byte */
 134 #define LSR_RXRDY       0x01    /* Byte ready in Receive Buffer */
 135 #define LSR_RCV_MASK    0x1f    /* Mask for incoming data or error */
 136
 137 /* modem status register */
 138 /* All deltas are from the last read of the MSR. */
 139 #define MSR_DCD         0x80    /* Current Data Carrier Detect */
 140 #define MSR_RI          0x40    /* Current Ring Indicator */
 141 #define MSR_DSR         0x20    /* Current Data Set Ready */
 142 #define MSR_CTS         0x10    /* Current Clear to Send */
 143 #define MSR_DDCD        0x08    /* DCD has changed state */
 144 #define MSR_TERI        0x04    /* RI has toggled low to high */
 145 #define MSR_DDSR        0x02    /* DSR has changed state */
 146 #define MSR_DCTS        0x01    /* CTS has changed state */
 147
 148 /* OMAP mode definition register 1 */
 149 #define MDR1_FRAME_END_MODE             0x80
 150 #define MDR1_SIP_MODE                   0x40
 151 #define MDR1_SCT                        0x20
 152 #define MDR1_SET_TXIR                   0x10
 153 #define MDR1_IR_SLEEP                   0x08
 154 #define MDR1_MODE_DISABLE               0x07
 155 #define MDR1_MODE_FIR                   0x05
 156 #define MDR1_MODE_MIR                   0x04
 157 #define MDR1_MODE_UART_13X              0x03
 158 #define MDR1_MODE_UART_16X_AUTOBAUD     0x02
 159 #define MDR1_MODE_SIR                   0x01
 160 #define MDR1_MODE_UART_16X              0x00
 161 #define MDR1_MODE_MASK                  0x07
 162
 163
 164 /* XXX ISA-specific. */
 165 #define COM_NPORTS      8