drivers/atl2/atl2.h

   1 /* Attansic/Atheros L2 FastEthernet driver, by D.C. van Moolenbroek */
   2
   3 #define ATL2_MMAP_SIZE                  0x40000 /* memory-mapped registers */
   4
   5 /* The first three are configurable to a certain extent; the last is not. */
   6 #define ATL2_TXD_BUFSIZE                8192    /* TxD ring buffer size */
   7 #define ATL2_TXS_COUNT                  64      /* Tx status ring array size */
   8 #define ATL2_RXD_COUNT                  64      /* Rx descriptors */
   9 #define ATL2_RXD_SIZE                   1536    /* Rx element size */
  10
  11 #define ATL2_MASTER_REG                 0x1400  /* master register */
  12 #       define ATL2_MASTER_SOFT_RESET   0x00000001      /* soft reset */
  13 #       define ATL2_MASTER_IMT_EN       0x00000004      /* IMT enabled */
  14
  15 #define ATL2_RESET_NTRIES               100     /* #tries to wait for reset */
  16 #define ATL2_RESET_DELAY                10      /* delay (us) between tries */
  17
  18 #define ATL2_PHY_ENABLE_REG             0x140c  /* PHY enable register */
  19 #       define ATL2_PHY_ENABLE          1               /* enable PHY */
  20
  21 #define ATL2_IDLE_REG                   0x1410  /* idle status register */
  22
  23 #define ATL2_IDLE_NTRIES                100     /* #tries to wait for idle */
  24 #define ATL2_IDLE_DELAY                 100     /* delay (us) between tries */
  25
  26 #define ATL2_HWADDR0_REG                0x1488  /* Hardware address (part 0) */
  27 #define ATL2_HWADDR1_REG                0x148c  /* Hardware address (part 1) */
  28
  29 #define ATL2_ISR_REG                    0x1600  /* interrupt status register */
  30 #       define ATL2_ISR_RXF_OVERFLOW    0x00000004      /* RxF overflow */
  31 #       define ATL2_ISR_TXF_UNDERRUN    0x00000008      /* TxF underrun */
  32 #       define ATL2_ISR_TXS_OVERFLOW    0x00000010      /* TxS overflow */
  33 #       define ATL2_ISR_RXS_OVERFLOW    0x00000020      /* RxS overflow */
  34 #       define ATL2_ISR_TXD_UNDERRUN    0x00000080      /* TxD underrun */
  35 #       define ATL2_ISR_RXD_OVERFLOW    0x00000100      /* RxD overflow */
  36 #       define ATL2_ISR_DMAR_TIMEOUT    0x00000200      /* DMA read timeout */
  37 #       define ATL2_ISR_DMAW_TIMEOUT    0x00000400      /* DMA write timeout */
  38 #       define ATL2_ISR_TXS_UPDATED     0x00010000      /* Tx status updated */
  39 #       define ATL2_ISR_RXD_UPDATED     0x00020000      /* Rx status updated */
  40 #       define ATL2_ISR_TX_EARLY        0x00040000      /* Tx started xmit */
  41 #       define ATL2_ISR_PHY_LINKDOWN    0x10000000      /* PHY link down */
  42 #       define ATL2_ISR_DISABLE         0x80000000      /* disable intrs */
  43 #       define ATL2_ISR_TX_EVENT        (ATL2_ISR_TXF_UNDERRUN | \
  44                                          ATL2_ISR_TXS_OVERFLOW | \
  45                                          ATL2_ISR_TXD_UNDERRUN | \
  46                                          ATL2_ISR_TXS_UPDATED | \
  47                                          ATL2_ISR_TX_EARLY)
  48 #       define ATL2_ISR_RX_EVENT        (ATL2_ISR_RXF_OVERFLOW | \
  49                                          ATL2_ISR_RXS_OVERFLOW | \
  50                                          ATL2_ISR_RXD_OVERFLOW | \
  51                                          ATL2_ISR_RXD_UPDATED)
  52
  53 #define ATL2_IMR_REG                    0x1604  /* interrupt mask register */
  54 #       define ATL2_IMR_DEFAULT         (ATL2_ISR_DMAR_TIMEOUT | \
  55                                          ATL2_ISR_DMAW_TIMEOUT | \
  56                                          ATL2_ISR_TXS_UPDATED | \
  57                                          ATL2_ISR_RXD_UPDATED | \
  58                                          ATL2_ISR_PHY_LINKDOWN)
  59
  60 #define ATL2_MAC_REG                    0x1480  /* MAC config register */
  61 #       define ATL2_MAC_TX_EN           0x00000001      /* enable transmit */
  62 #       define ATL2_MAC_RX_EN           0x00000002      /* enable receive */
  63 #       define ATL2_MAC_PROMISC_EN      0x00008000      /* promiscuous */
  64 #       define ATL2_MAC_MCAST_EN        0x02000000      /* multicast */
  65 #       define ATL2_MAC_BCAST_EN        0x04000000      /* broadcast */
  66 #       define ATL2_MAC_DEFAULT         0x28001cec      /* (magic) */
  67
  68 #define ATL2_MHT0_REG                   0x1490  /* multicast hash table bits */
  69 #define ATL2_MHT1_REG                   0x1494  /* 64 slots in total */
  70
  71 #define ATL2_DMAREAD_REG                0x1580  /* read DMA config register */
  72 #       define ATL2_DMAREAD_EN          1               /* read DMA enabled */
  73 #define ATL2_DMAWRITE_REG               0x15a0  /* write DMA config register */
  74 #       define ATL2_DMAWRITE_EN         1               /* write DMA enabled */
  75
  76 #define ATL2_DESC_ADDR_HI_REG           0x1540  /* high 32 bits of addresses */
  77 #define ATL2_TXD_ADDR_LO_REG            0x1544  /* low 32 bits of TxD base */
  78 #define ATL2_TXD_BUFSIZE_REG            0x1548  /* size of TxD ring buffer */
  79 #define ATL2_TXS_ADDR_LO_REG            0x154c  /* low 32 bits of TxS base */
  80 #define ATL2_TXS_COUNT_REG              0x1550  /* number of TxS descriptors */
  81 #define ATL2_RXD_ADDR_LO_REG            0x1554  /* low 32 bits of RxD base */
  82 #define ATL2_RXD_COUNT_REG              0x1558  /* number of RxD descriptors */
  83
  84 #define ATL2_IFG_REG                    0x1484  /* inter-frame gap config */
  85 #       define ATL2_IFG_DEFAULT         0x60405060      /* (magic) */
  86
  87 #define ATL2_HDPX_REG                   0x1498  /* half-duplex mode config */
  88 #       define ATL2_HDPX_DEFAULT        0x07a1f037      /* (magic) */
  89
  90 #define ATL2_IMT_REG                    0x1408  /* intr moderation timer */
  91 #       define ATL2_IMT_DEFAULT         100             /* 200 us */
  92
  93 #define ATL2_ICT_REG                    0x140e  /* intr clearing timer */
  94 #       define ATL2_ICT_DEFAULT         50000           /* 100 ms */
  95
  96 #define ATL2_MTU_REG                    0x149c  /* MTU config */
  97 #       define ATL2_MTU_DEFAULT         ETH_MAX_PACK_SIZE_TAGGED
  98
  99 #define ATL2_CUT_THRESH_REG             0x1590  /* cut-through config */
 100 #       define ATL2_CUT_THRESH_DEFAULT  0x177           /* (magic) */
 101
 102 #define ATL2_FLOW_THRESH_HI_REG         0x15a8  /* RxD overflow hi watermark */
 103 #define ATL2_FLOW_THRESH_LO_REG         0x15aa  /* RxD overflow lo watermark */
 104
 105 #define ATL2_TXD_IDX_REG                0x15f0  /* TxD read index */
 106 #define ATL2_RXD_IDX_REG                0x15f4  /* RxD write index */
 107
 108 #define ATL2_LTSSM_TESTMODE_REG         0x12fc  /* PCIE configuration */
 109 #define ATL2_LTSSM_TESTMODE_DEFAULT     0x6500          /* (magic) */
 110 #define ATL2_DLL_TX_CTRL_REG            0x1104  /* PCIE configuration */
 111 #define ATL2_DLL_TX_CTRL_DEFAULT        0x0568          /* (magic) */
 112
 113 #define ATL2_VPD_CAP_REG                0x6c    /* VPD command register */
 114 #       define ATL2_VPD_CAP_ADDR_SHIFT  16
 115 #       define ATL2_VPD_CAP_ADDR_MASK   0x7fff0000
 116 #       define ATL2_VPD_CAP_DONE        0x80000000
 117 #define ATL2_VPD_DATA_REG               0x70    /* VPD data register */
 118
 119 #define ATL2_SPICTL_REG                 0x200   /* SPI control register */
 120 #       define ATL2_SPICTL_VPD_EN       0x2000          /* enable VPD */
 121
 122 #define ATL2_VPD_REGBASE                0x100   /* VPD register base */
 123 #define ATL2_VPD_NREGS                  64      /* number of VPD registers */
 124 #define ATL2_VPD_SIG_MASK               0xff    /* signature mask */
 125 #define ATL2_VPD_SIG                    0x5a    /* VPD entry signature */
 126 #define ATL2_VPD_REG_SHIFT              16      /* key shift */
 127
 128 #define ATL2_VPD_NTRIES                 10      /* #tries to read from VPD */
 129 #define ATL2_VPD_DELAY                  2000    /* delay (us) between tries */
 130
 131 #define ATL2_MDIO_REG                   0x1414  /* Management Data I/O reg */
 132 #       define ATL2_MDIO_ADDR_SHIFT     16              /* register address */
 133 #       define ATL2_MDIO_ADDR_MASK      0x001f0000      /* (shift and mask) */
 134 #       define ATL2_MDIO_READ           0x00200000      /* read operation */
 135 #       define ATL2_MDIO_SUP_PREAMBLE   0x00400000      /* suppress preamble */
 136 #       define ATL2_MDIO_START          0x00800000      /* initiate xfer */
 137 #       define ATL2_MDIO_CLK_25_4       0x00000000      /* 25MHz, 4bit */
 138 #       define ATL2_MDIO_BUSY           0x08000000      /* in progress */
 139 #       define ATL2_MDIO_DATA_MASK      0x0000ffff      /* result data mask */
 140
 141 #define ATL2_MDIO_NTRIES                10      /* #tries to access MDIO */
 142 #define ATL2_MDIO_DELAY                 2       /* delay (us) between tries */
 143
 144 #define ATL2_MII_BMSR                   1       /* basic mode status reg */
 145 #       define ATL2_MII_BMSR_LSTATUS    0x0004          /* link status */
 146 #define ATL2_MII_PSSR                   17      /* PHY specific status reg */
 147 #       define ATL2_MII_PSSR_RESOLVED   0x0800          /* speed/duplex OK */
 148 #       define ATL2_MII_PSSR_DUPLEX     0x2000          /* full duplex */
 149 #       define ATL2_MII_PSSR_SPEED      0xc000          /* link speed */
 150 #       define ATL2_MII_PSSR_10         0x0000                  /* 10Mbps */
 151 #       define ATL2_MII_PSSR_100        0x4000                  /* 100Mbps */
 152 #       define ATL2_MII_PSSR_1000       0x8000                  /* 1000Mbps */
 153
 154 #define ATL2_RXD_SIZE_MASK              0x000007ff      /* packet size mask */
 155 #define ATL2_RXD_SUCCESS                0x00010000      /* successful receipt */
 156 #define ATL2_RXD_BCAST                  0x00020000      /* broadcast frame */
 157 #define ATL2_RXD_MCAST                  0x00040000      /* multicast frame */
 158 #define ATL2_RXD_PAUSE                  0x00080000      /* pause frame */
 159 #define ATL2_RXD_CTRL                   0x00100000      /* control frame */
 160 #define ATL2_RXD_CRCERR                 0x00200000      /* invalid frame CRC */
 161 #define ATL2_RXD_CODEERR                0x00400000      /* invalid opcode */
 162 #define ATL2_RXD_RUNT                   0x00800000      /* short frame */
 163 #define ATL2_RXD_FRAG                   0x01000000      /* collision fragment */
 164 #define ATL2_RXD_TRUNC                  0x02000000      /* frame truncated */
 165 #define ATL2_RXD_ALIGN                  0x04000000      /* frame align error */
 166 #define ATL2_RXD_UPDATE                 0x80000000      /* updated by device */
 167
 168 #define ATL2_TXS_SIZE_MASK              0x000007ff      /* packet size mask */
 169 #define ATL2_TXS_SUCCESS                0x00010000      /* successful xmit */
 170 #define ATL2_TXS_BCAST                  0x00020000      /* broadcast frame */
 171 #define ATL2_TXS_MCAST                  0x00040000      /* multicast frame */
 172 #define ATL2_TXS_PAUSE                  0x00080000      /* pause frame */
 173 #define ATL2_TXS_CTRL                   0x00100000      /* control frame */
 174 #define ATL2_TXS_DEFER                  0x00200000      /* deferred transmit */
 175 #define ATL2_TXS_EXCDEFER               0x00400000      /* excess defer */
 176 #define ATL2_TXS_SINGLECOL              0x00800000      /* single collision */
 177 #define ATL2_TXS_MULTICOL               0x01000000      /* multi collisions */
 178 #define ATL2_TXS_LATECOL                0x02000000      /* late collision */
 179 #define ATL2_TXS_ABORTCOL               0x04000000      /* collision abort */
 180 #define ATL2_TXS_UNDERRUN               0x08000000      /* buffer underrun */
 181 #define ATL2_TXS_UPDATE                 0x80000000      /* updated by device */
 182
 183