drivers/fxp/fxp.h

   1 /*
   2 ibm/fxp.h
   3
   4 Registers and datastructures of the Intel 82557, 82558, 82559, 82550,
   5 and 82562 fast ethernet controllers.
   6
   7 Created:        Nov 2004 by Philip Homburg <philip@f-mnx.phicoh.com>
   8 */
   9
  10 #ifndef _FXP_FXP_H
  11 #define _FXP_FXP_H
  12
  13 #define VERBOSE         0       /* display output during intialization */
  14
  15 /* Revisions in PCI_REV */
  16 #define FXP_REV_82557A          0x01
  17 #define FXP_REV_82557B          0x02
  18 #define FXP_REV_82557C          0x03
  19 #define FXP_REV_82558A          0x04
  20 #define FXP_REV_82558B          0x05
  21 #define FXP_REV_82559A          0x06
  22 #define FXP_REV_82559B          0x07
  23 #define FXP_REV_82559C          0x08
  24 #define FXP_REV_82559ERA        0x09
  25 #define FXP_REV_82550_1         0x0C
  26 #define FXP_REV_82550_2         0x0D
  27 #define FXP_REV_82550_3         0x0E
  28 #define FXP_REV_82551_1         0x0F
  29 #define FXP_REV_82551_2         0x10
  30 #define FXP_REV_82801CAM        0x42
  31 #define FXP_REV_82801DB         0x81
  32
  33 /* Control/Status Registers (CSR). The first 8 bytes are called
  34  * System Control Block (SCB)
  35  */
  36 #define SCB_STATUS      0x00    /* Lower half of the SCB status word. CU and
  37                                  * RU status.
  38                                  */
  39 #define     SS_CUS_MASK         0xC0    /* CU Status */
  40 #define         SS_CU_IDLE              0x00    /* Idle */
  41 #define         SS_CU_SUSP              0x40    /* Suspended */
  42 #define         SS_CU_LPQA              0x80    /* LPQ Active */
  43 #define         SS_CU_HQPA              0xC0    /* HQP Active */
  44 #define     SS_RUS_MASK         0x3C    /* RU Status */
  45 #define         SS_RU_IDLE              0x00    /* Idle */
  46 #define         SS_RU_SUSP              0x04    /* Suspended */
  47 #define         SS_RU_NORES             0x08    /* No Resources */
  48 #define         SS_RU_READY             0x10    /* Ready */
  49                                                 /* Other values are reserved */
  50 #define     SS_RESERVED         0x03    /* Reserved */
  51 #define SCB_INT_STAT    0x01    /* Upper half of the SCB status word.
  52                                  * Interrupt status. Also used to acknoledge
  53                                  * interrupts.
  54                                  */
  55 #define         SIS_CX  0x80    /* CU command with interrupt bit set. On
  56                                  * 82557 also TNO Interrupt.
  57                                  */
  58 #define         SIS_FR  0x40    /* Frame Received */
  59 #define         SIS_CNA 0x20    /* CU Not Active */
  60 #define         SIS_RNR 0x10    /* RU Not Ready */
  61 #define         SIS_MDI 0x08    /* MDI read/write cycle completed */
  62 #define         SIS_SWI 0x04    /* Software Interrupt */
  63 #define         SIS_RES 0x02    /* Reserved */
  64 #define         SIS_FCP 0x01    /* Flow Control Pause Interrupt (82558 and
  65                                  * later, reserved on 82557)
  66                                  */
  67 #define SCB_CMD         0x02    /* Lower half of the SCB command word. CU and
  68                                  * RU commands.
  69                                  */
  70 #define     SC_CUC_MASK         0xF0
  71 #define         SC_CU_NOP               0x00    /* NOP */
  72 #define         SC_CU_START             0x10    /* Start CU */
  73 #define         SC_CU_RESUME            0x20    /* Resume CU */
  74 #define         SC_CU_LOAD_DCA          0x40    /* Load Dump Counters Address */
  75 #define         SC_CU_DUMP_SC           0x50    /* Dump Statistical Counters */
  76 #define         SC_CU_LOAD_BASE         0x60    /* Load CU Base */
  77 #define         SC_CU_DUMP_RSET_SC      0x70    /* Dump and Reset Counters */
  78 #define         SC_CU_STATIC_RESUME     0xA0    /* Static Resume, 82558 and
  79                                                  * above
  80                                                  */
  81 #define     SC_RESERVED         0x08    /* Reserved */
  82 #define     SC_RUC_MASK         0x07    /* RU Command Mask */
  83 #define         SC_RU_NOP               0x00    /* NOP */
  84 #define         SC_RU_START             0x01    /* Start RU */
  85 #define         SC_RU_RESUME            0x02    /* Resume RU */
  86 #define         SC_RU_DMA_REDIR         0x03    /* DMA Redirect */
  87 #define         SC_RU_ABORT             0x04    /* Abort RU */
  88 #define         SC_RU_LOAD_HDR          0x05    /* Load Header Data Size */
  89 #define         SC_RU_LOAD_BASE         0x06    /* Load RU Base */
  90 #define SCB_INT_MASK    0x03    /* Upper half of the SCB command word.
  91                                  * Interrupt mask. Can also be used to
  92                                  * generate a 'software' interrupt.
  93                                  */
  94                                 /* The following 6 mask bits are not valid on
  95                                  * the 82557.
  96                                  */
  97 #define     SIM_CX      0x80    /* Mask CX */
  98 #define     SIM_FR      0x40    /* Mask FR */
  99 #define     SIM_CNA     0x20    /* Mask CNA */
 100 #define     SIM_RNR     0x10    /* Mask RNR */
 101 #define     SIM_ER      0x08    /* Mask ER */
 102 #define     SIM_FCP     0x04    /* Mask FCP */
 103 #define     SIM_SI      0x02    /* Generate Software Interrupt */
 104 #define     SIM_M       0x01    /* Mask all interrupts */
 105 #define SCB_POINTER     0x04    /* A 32-bit (pointer) argument for CU and RU
 106                                  * commands.
 107                                  */
 108 #define CSR_PORT        0x08    /* Control functions that bypass the SCB */
 109 #define     CP_PTR_MASK         0xFFFFFFF0      /* Argument pointer */
 110 #define     CP_CMD_MASK         0x0000000F      /* Commands bits */
 111 #define         CP_CMD_SOFT_RESET       0x00000000      /* Software reset */
 112 #define             CSR_PORT_RESET_DELAY        10      /* Wait for reset to
 113                                                          * complete. In micro
 114                                                          * seconds.
 115                                                          */
 116 #define         CP_CMD_SELF_TEST        0x00000001      /* Self test */
 117 #define         CP_CMD_SEL_RESET        0x00000002      /* Selective reset */
 118 #define         CP_CMD_DUMP             0x00000003      /* Dump */
 119 #define         CP_CMD_DUMP_WAKEUP      0x00000007      /* Dump and wake-up,
 120                                                          * 82559 and later.
 121                                                          */
 122 #define CSR_RESERVED    0x0C    /* reserved, 16-bits */
 123 #define CSR_EEPROM      0x0E    /* EEPROM Control Register */
 124 #define     CE_RESERVED 0xF0    /* Reserved */
 125 #define     CE_EEDO     0x08    /* Serial Data Out  (of the EEPROM) */
 126 #define     CE_EEDI     0x04    /* Serial Data In (to the EEPROM) */
 127 #define     CE_EECS     0x02    /* Chip Select */
 128 #define     CE_EESK     0x01    /* Serial Clock */
 129 #define CSR_RESERVED1   0x0F    /* Reserved */
 130 #define CSR_MDI_CTL     0x10    /* MDI Control Register, 32-bits */
 131 #define     CM_RESERVED         0xC0000000      /* Reserved */
 132 #define     CM_IE               0x20000000      /* Enable Interrupt */
 133 #define     CM_READY            0x10000000      /* Command completed */
 134 #define     CM_OPCODE_MASK      0x0C000000      /* Opcode */
 135 #define         CM_WRITE                0x04000000      /* Write */
 136 #define         CM_READ                 0x08000000      /* Read */
 137 #define     CM_PHYADDR_MASK     0x03E00000      /* Which PHY */
 138 #define         CM_PHYADDR_SHIFT 21
 139 #define     CM_REG_MASK         0x001F0000      /* Which register in the PHY */
 140 #define         CM_REG_SHIFT    16
 141 #define     CM_DATA_MASK        0x0000FFFF      /* Data to be read or written */
 142
 143 /* Control Block List (CBL) commands */
 144 #define CBL_NOP         0       /* No-operation */
 145 #define CBL_AIS         1       /* Individual Address Setup */
 146 #define CBL_CONF        2       /* Configure NIC */
 147 #define CBL_MAS         3       /* Multicast Address Setup */
 148 #define CBL_XMIT        4       /* Transmit */
 149 #define CBL_LM          5       /* Load Microcode */
 150 #define CBL_DUMP        6       /* Dump Internal Registers */
 151 #define CBL_DIAG        7       /* Diagnose Command */
 152
 153 /* Common command fields */
 154 #define CBL_C_CMD_MASK  0x0007  /* Command bits */
 155 #define CBL_C_EL        0x8000  /* End of CBL */
 156 #define CBL_C_S         0x4000  /* Suspend after the completion of the CB */
 157 #define CBL_C_I         0x2000  /* Request CX Interrupt */
 158 #define CBL_C_RES       0x1FF8  /* Reserved */
 159
 160 /* Command flags */
 161 #define CBL_F_C         0x8000  /* Command has completed */
 162 #define CBL_F_RES1      0x4000  /* Reserved */
 163 #define CBL_F_OK        0x2000  /* Command was executed without errors */
 164 #define CBL_F_RES0      0x1FFF  /* Reserved */
 165
 166 /* Individual Address Setup (1) */
 167 struct ias
 168 {
 169         u16_t ias_status;
 170         u16_t ias_command;
 171         u32_t ias_linkaddr;
 172         u8_t ias_ethaddr[6];
 173         u8_t ias_reserved[2];
 174 };
 175
 176 /* Configure (2) */
 177 #define CC_BYTES_NR     22      /* Number of configuration bytes */
 178 struct cbl_conf
 179 {
 180         u16_t cc_status;
 181         u16_t cc_command;
 182         u32_t cc_linkaddr;
 183         u8_t cc_bytes[CC_BYTES_NR];
 184 };
 185
 186 /* Byte 0 */
 187 #define CCB0_RES        0xC0    /* Reserved (0) */
 188 #define CCB0_BYTECOUNT  0x3F    /* Byte Count (typically either 8 or 22) */
 189
 190 /* Byte 1 */
 191 #define CCB1_RES        0x80    /* Reserved (0) */
 192 #define CCB1_TXFIFO_LIM 0x70    /* Transmit FIFO Limit, in DWORDS */
 193 #define         CTL_DEFAULT     0x00    /* 0 bytes */
 194 #define CCB1_RXFIFO_LIM 0x0F    /* Receive FIFO Limit */
 195 #define         CRL_DEFAULT     0x08    /* 32 bytes on 82557, 64 bytes on
 196                                          * 82558/82559.
 197                                          */
 198
 199 /* Byte 2 */
 200 #define CCB2_AIFS       0xFF    /* Adaptive IFS */
 201 #define         CAI_DEFAULT     0
 202
 203 /* Byte 3 */
 204                                 /* Reserved (must be 0) on 82557 */
 205 #define CCB3_RES        0xF0    /* Reserved (0) */
 206 #define CCB3_TWCL       0x08    /* Terminate Write on Cache Line */
 207 #define CCB3_RAE        0x04    /* Read Alignment Enable */
 208 #define CCB3_TE         0x02    /* Type Enable??? */
 209 #define CCB3_MWIE       0x01    /* Memory Write and Invalidate (MWI) Enable
 210                                  * Additionally the MWI bit in the PCI
 211                                  * command register has to be set.
 212                                  * Recommended by Intel.
 213                                  */
 214
 215 /* Byte 4 */
 216 #define CCB4_RES        0x80    /* Reserved (0) */
 217 #define CCB4_RXDMA_MAX  0x7F    /* Receive DMA Maximum Byte Count */
 218
 219 /* Byte 5 */
 220 #define CCB5_DMBCE      0x80    /* DMA Maximum Byte Count Enable */
 221 #define CCB5_TXDMA_MAX  0x7F    /* Transmit DMA Maximum Byte Count */
 222
 223 /* Byte 6 */
 224 #define CCB6_SBF        0x80    /* Save Bad Frames */
 225 #define CCB6_DORF       0x40    /* (Do not) Discard Overrun Receive Frame,
 226                                  * Set this bit to keep them.
 227                                  */
 228 #define CCB6_ESC        0x20    /* Extended Statistical Counter. Reserved
 229                                  * on 82557, must be set to 1.
 230                                  * Clear this bit to get more counters.
 231                                  */
 232 #define CCB6_ETCB       0x10    /* Extended Transmit CB. Reserved on 82557,
 233                                  * must be set to 1.
 234                                  * Clear this bit to use Extended TxCBs.
 235                                  */
 236 #define CCB6_CI_INT     0x08    /* CPU Idle (CI) Interrupt. Generate a
 237                                  * CI Int (bit set) or a CNA Int (bit clear)
 238                                  * when the CU goes to the idle state (or
 239                                  * to suspended for CNA).
 240                                  */
 241 #define CCB6_TNO_INT    0x04    /* Enable TNO Interrupt (82557 only) */
 242 #define CCB6_TCOSC      0x04    /* TCO Statistical Counter (82559 only) */
 243 #define CCB6_RES        0x02    /* Reserved, must be set to 1. Called "disable
 244                                  * direct rcv dma mode" by the FreeBSD
 245                                  * driver.
 246                                  */
 247 #define CCB6_LSCB       0x01    /* Late SCB Update. Only on 82557. */
 248
 249 /* Byte 7 */
 250 #define CCB7_DTBD       0x80    /* Dynamic TBD. Reserved on 82557, should be
 251                                  * be set to 0.
 252                                  */
 253 #define CCB7_2FFIFO     0x40    /* (At Most) Two Frames in FIFO. Reserved on
 254                                  * 82557, should be set to 0.
 255                                  */
 256 #define CCB7_RES        0x38    /* Reserved (0) */
 257 #define CCB7_UR         0x06    /* Underrun Retry */
 258 #define     CUR_0               0x00    /* No re-transmission */
 259 #define     CUR_1               0x02    /* One re-transmission */
 260 #define     CUR_2               0x04    /* Two re-transmissions, 1st retry with
 261                                          * 512 bytes.
 262                                          */
 263 #define     CUR_3               0x06    /* Tree re-transmissions, 1st retry
 264                                          * with 512 bytes, 2nd retry with 1024.
 265                                          */
 266 #define CCB7_DSRF       0x01    /* Discard Short Receive Frames. */
 267
 268 /* Byte 8 */
 269 #define CCB8_CSMAD      0x80    /* CSMA Disable. Reserved on 82557, should be
 270                                  * set to zero.
 271                                  */
 272 #define CCB8_RES        0x7E    /* Reserved (0) */
 273 #define CCB8_503_MII    0x01    /* 503 mode or MII mode. Reserved on 82558
 274                                  * and 82559, should be set to 1.
 275                                  */
 276
 277 /* Byte 9 */
 278 #define CCB9_MMWE       0x80    /* Multicast Match Wake Enable. 82558 B-step
 279                                  * only, should be set to zero on other
 280                                  * devices.
 281                                  */
 282 #define CCB9_AWE        0x40    /* ARP Wake-up Enable. 82558 B-step only,
 283                                  * should be set to zero on other devices.
 284                                  */
 285 #define CCB9_LSCWE      0x20    /* Link Status Change Wake Enable. Available
 286                                  * on 82558 B-step and 82559. Should be
 287                                  * set to zero on 82557 and 82558 A-step
 288                                  */
 289 #define CCB9_VARP       0x10    /* VLAN ARP (82558 B-step) or VLAN TCO (82559).
 290                                  * Should be zero on 82557 and 82558 A-step
 291                                  */
 292 #define CCB9_RES        0x0E    /* Reserved (0) */
 293 #define CCB9_TUC        0x01    /* TCP/UDP Checksum. 82559 only, should be
 294                                  * zero on other devices.
 295                                  */
 296
 297 /* Byte 10 */
 298 #define CCB10_LOOPBACK  0xC0    /* Loopback mode */
 299 #define     CLB_NORMAL          0x00    /* Normal operation */
 300 #define     CLB_INTERNAL        0x40    /* Internal loopback */
 301 #define     CLB_RESERVED        0x80    /* Reserved */
 302 #define     CLB_EXTERNAL        0xC0    /* External loopback */
 303 #define CCB10_PAL       0x30    /* Pre-amble length */
 304 #define     CPAL_1              0x00    /* 1 byte */
 305 #define     CPAL_3              0x10    /* 3 bytes */
 306 #define     CPAL_7              0x20    /* 7 bytes */
 307 #define     CPAL_15             0x30    /* 15 bytes */
 308 #define     CPAL_DEFAULT        CPAL_7
 309 #define CCB10_NSAI              0x08    /* No Source Address Insertion */
 310 #define CCB10_RES1              0x06    /* Reserved, should be set to 1 */
 311 #define CCB10_RES0              0x01    /* Reserved (0) */
 312
 313 /* Byte 11 */
 314 #define CCB11_RES               0xF8    /* Reserved (0) */
 315 #define CCB11_LINPRIO           0x07    /* Linear Priority. 82557 only,
 316                                          * should be zero on other devices.
 317                                          */
 318
 319 /* Byte 12 */
 320 #define CCB12_IS                0xF0    /* Interframe spacing in multiples of
 321                                          * 16 bit times.
 322                                          */
 323 #define     CIS_DEFAULT                 0x60    /* 96 (6 in register) */
 324 #define CCB12_RES               0x0E    /* Reserved (0) */
 325 #define CCB12_LPM               0x01    /* Linear Priority Mode. 82557 only,
 326                                          * should be zero on other devices.
 327                                          */
 328
 329 /* Byte 13, 4th byte of IP address for ARP frame filtering. Only valid on
 330  * 82558 B-step. Should be 0 on other devices.
 331  */
 332 #define CCB13_DEFAULT           0x00
 333 /* Byte 14, 3rd byte of IP address for ARP fram efiltering. Only valid on
 334  * 82558 B-step. Should be 0xF2 on other devices.
 335  */
 336 #define CCB14_DEFAULT           0xF2
 337
 338 /* Byte 15 */
 339 #define CCB15_CRSCDT            0x80    /* CRS or CDT. */
 340 #define CCB15_RES1              0x40    /* Reserved, should be set to one. */
 341 #define CCB15_CRC16             0x20    /* 16-bit CRC. Only on 82559,
 342                                          * should be zero on other devices
 343                                          */
 344 #define CCB15_IUL               0x10    /* Ignore U/L. Reserved on 82557 and
 345                                          * should be set to zero.
 346                                          */
 347 #define CCB15_RES2              0x08    /* Reserved, should be set to one. */
 348 #define CCB15_WAW               0x04    /* Wait After Win. Reserved on 82557,
 349                                          * should be set to zero.
 350                                          */
 351 #define CCB15_BD                0x02    /* Broadcast disable */
 352 #define CCB15_PM                0x01    /* Promiscuous mode */
 353
 354 /* Byte 16. FC Delay Least Significant Byte. Reserved on the 82557 and
 355  * should be set to zero.
 356  */
 357 #define CCB16_DEFAULT           0x00
 358
 359 /* Byte 17. FC Delay Most Significant Byte. This byte is reserved on the
 360  * 82557 and should be set to 0x40.
 361  */
 362 #define CCB17_DEFAULT           0x40
 363
 364 /* Byte 18 */
 365 #define CCB18_RES1              0x80    /* Reserved, should be set to 1 */
 366 #define CCB18_PFCT              0x70    /* Priority Flow Control Threshold.
 367                                          * Reserved on the 82557 and should
 368                                          * be set to 1. All bits 1 (disabled)
 369                                          * is the recommended default.
 370                                          */
 371 #define CCB18_LROK              0x08    /* Long Receive OK. Reserved on the
 372                                          * 82557 and should be set to zero.
 373                                          * Required for VLANs.
 374                                          */
 375 #define CCB18_RCRCT             0x04    /* Receive CRC Transfer */
 376 #define CCB18_PE                0x02    /* Padding Enable */
 377 #define CCB18_SE                0x01    /* Stripping Enable */
 378
 379 /* Byte 19 */
 380 #define CCB19_FDPE              0x80    /* Full Duplex Pin Enable */
 381 #define CCB19_FFD               0x40    /* Force Full Duplex */
 382 #define CCB19_RFC               0x20    /* Reject FC. Reserved on the 82557
 383                                          * and should be set to zero.
 384                                          */
 385 #define CCB19_FDRSTAFC          0x10    /* Full Duplex Restart Flow Control.
 386                                          * Reserved on the 82557 and should be
 387                                          * set to zero.
 388                                          */
 389 #define CCB19_FDRSTOFC          0x08    /* Full Duplex Restop Flow Control.
 390                                          * Reserved on the 82557 and should be
 391                                          * set to zero.
 392                                          */
 393 #define CCB19_FDTFCD            0x04    /* Full Duplex Transmit Flow Control
 394                                          * Disable. Reserved on the 82557 and
 395                                          * should be set to zero.
 396                                          */
 397 #define CCB19_MPWD              0x02    /* Magic Packet Wake-up Disable.
 398                                          * Reserved on the 82557 and 82559ER
 399                                          * and should be set to zero.
 400                                          */
 401 #define CCB19_AW                0x01    /* Address Wake-up (82558 A-step) and
 402                                          * IA Match Wake Enable (82558 B-step)
 403                                          * Reserved on the 82557 and 82559 and
 404                                          * should be set to zero.
 405                                          */
 406
 407 /* Byte 20 */
 408 #define CCB20_RES               0x80    /* Reserved (0) */
 409 #define CCB20_MIA               0x40    /* Multiple IA */
 410 #define CCB20_PFCL              0x20    /* Priority FC Location. Reserved on
 411                                          * the 82557 and should be set to 1.
 412                                          */
 413 #define CCB20_RES1              0x1F    /* Reserved, should be set to 1 */
 414
 415 /* Byte 21 */
 416 #define CCB21_RES               0xF0    /* Reserved (0) */
 417 #define CCB21_MA                0x08    /* Multicast All */
 418 #define CCB21_RES1_MASK         0x07    /* Reserved, should be set to 5 */
 419 #define     CCB21_RES21                 0x05
 420
 421 /* Transmit (4) */
 422 struct tx
 423 {
 424         u16_t tx_status;
 425         u16_t tx_command;
 426         u32_t tx_linkaddr;
 427         u32_t tx_tbda;
 428         u16_t tx_size;
 429         u8_t tx_tthresh;
 430         u8_t tx_ntbd;
 431         u8_t tx_buf[ETH_MAX_PACK_SIZE_TAGGED];
 432 };
 433
 434 #define TXS_C           0x8000  /* Transmit DMA has completed */
 435 #define TXS_RES         0x4000  /* Reserved */
 436 #define TXS_OK          0x2000  /* Command was executed without error */
 437 #define TXS_U           0x1000  /* This or previous frame encoutered underrun */
 438 #define TXS_RES1        0x0FFF  /* Reserved (0) */
 439
 440 #define TXC_EL          0x8000  /* End of List */
 441 #define TXC_S           0x4000  /* Suspend after this CB */
 442 #define TXC_I           0x2000  /* Interrupt after this CB */
 443 #define TXC_CID_MASK    0x1F00  /* CNA Interrupt Delay */
 444 #define TXC_RES         0x00E0  /* Reserved (0) */
 445 #define TXC_NC          0x0010  /* No CRC and Source Address Insertion */
 446 #define TXC_SF          0x0008  /* Not in Simplified Mode */
 447 #define TXC_CMD         0x0007  /* Command */
 448
 449 #define TXSZ_EOF        0x8000  /* End of Frame */
 450 #define TXSZ_RES        0x4000  /* Reserved (0) */
 451 #define TXSZ_COUNT      0x3FFF  /* Transmit Byte Count */
 452
 453 #define TX_TBDA_NIL     0xFFFFFFFF      /* Null Pointer for TBD Array */
 454
 455 #define TXTT_MIN        0x01    /* Minimum for Transmit Threshold */
 456 #define TXTT_MAX        0xE0    /* Maximum for Transmit Threshold */
 457
 458 /* Statistical Counters */
 459 struct sc
 460 {
 461         u32_t sc_tx_good;       /* Transmit Good Frames */
 462         u32_t sc_tx_maxcol;     /* Transmit Maximum Collisions errors */
 463         u32_t sc_tx_latecol;    /* Transmit Late Collisions errors */
 464         u32_t sc_tx_underrun;   /* Transmit Underrun errors */
 465         u32_t sc_tx_crs;        /* Transmit Lost Carrier Sense */
 466         u32_t sc_tx_defered;    /* Transmit Defered */
 467         u32_t sc_tx_scol;       /* Transmit Single Collision */
 468         u32_t sc_tx_mcol;       /* Transmit Multiple Collisions */
 469         u32_t sc_tx_totcol;     /* Transmit Total Collisions */
 470         u32_t sc_rx_good;       /* Receive Good Frames */
 471         u32_t sc_rx_crc;        /* Receive CRC errors */
 472         u32_t sc_rx_align;      /* Receive Alignment errors */
 473         u32_t sc_rx_resource;   /* Receive Resource errors */
 474         u32_t sc_rx_overrun;    /* Receive Overrun errors */
 475         u32_t sc_rx_cd;         /* Receive Collision Detect errors */
 476         u32_t sc_rx_short;      /* Receive Short Frame errors */
 477
 478                                 /* Short form ends here. The magic number will
 479                                  * be stored in the next field.
 480                                  */
 481
 482         u32_t sc_tx_fcp;        /* Transmit Flow Control Pause */
 483         u32_t sc_rx_fcp;        /* Receive Flow Control Pause */
 484         u32_t sc_rx_fcu;        /* Receive Flow Control Unsupported */
 485
 486                                 /* Longer form (82558 and later) ends here.
 487                                  * The magic number will be stored in the
 488                                  * next field.
 489                                  */
 490
 491         u32_t sc_tx_tco;        /* Transmit TCO frames */
 492         u32_t sc_rx_tco;        /* Receive TCO frames */
 493         u32_t sc_magic;         /* Dump of counters completed */
 494 };
 495
 496 #define SCM_DSC         0x0000A005      /* Magic for SC_CU_DUMP_SC command */
 497 #define SCM_DRSC        0x0000A007      /* Magic for SC_CU_DUMP_RSET_SC cmd */
 498
 499 /* Receive Frame Descriptor (RFD) */
 500 struct rfd
 501 {
 502         u16_t rfd_status;
 503         u16_t rfd_command;
 504         u32_t rfd_linkaddr;
 505         u32_t rfd_reserved;
 506         u16_t rfd_res;
 507         u16_t rfd_size;
 508         u8_t rfd_buf[ETH_MAX_PACK_SIZE_TAGGED];
 509 };
 510
 511 #define RFDS_C          0x8000  /* Frame Reception Completed */
 512 #define RFDS_RES        0x4000  /* Reserved (0) */
 513 #define RFDS_OK         0x2000  /* Frame received without any errors */
 514 #define RFDS_RES1       0x1000  /* Reserved */
 515 #define RFDS_CRCERR     0x0800  /* CRC error */
 516 #define RFDS_ALIGNERR   0x0400  /* Alignment error */
 517 #define RFDS_OUTOFBUF   0x0200  /* Ran out of buffer space (frame is frager
 518                                  * than supplied buffer).
 519                                  */
 520 #define RFDS_DMAOVR     0x0100  /* DMA overrun failure */
 521 #define RFDS_TOOSHORT   0x0080  /* Frame Too Short */
 522 #define RFDS_RES2       0x0040  /* Reserved */
 523 #define RFDS_TYPED      0x0020  /* Frame Is Typed (Type/Length field is 0 or
 524                                  * >1500)
 525                                  */
 526 #define RFDS_RXERR      0x0010  /* Receive Error */
 527 #define RFDS_RES3       0x0008  /* Reserved */
 528 #define RFDS_NOAM       0x0004  /* No Address Match */
 529 #define RFDS_NOAIAM     0x0002  /* No IA Address Match */
 530 #define RFDS_RXCOL      0x0001  /* Collition Detected During Reception (82557
 531                                  * and 82558 only)
 532                                  */
 533 #define RFDS_TCO        0x0001  /* TCO Packet (82559 and later) */
 534
 535 #define RFDC_EL         0x8000  /* End of List */
 536 #define RFDC_S          0x4000  /* Suspend */
 537 #define RFDC_RES        0x3FE0  /* Reserved (0) */
 538 #define RFDC_H          0x0010  /* Header RFD */
 539 #define RFDC_SF         0x0008  /* (Not) Simplified Mode */
 540 #define RFDC_RES1       0x0007  /* Reserved (0) */
 541
 542 #define RFDR_EOF        0x8000  /* End of Frame (all data is in the buffer) */
 543 #define RFDR_F          0x4000  /* Finished updating the count field */
 544 #define RFDR_COUNT      0x3FFF  /* Actual Count */
 545
 546 #define RFDSZ_RES       0xC000  /* Reserved (0) */
 547 #define RFDSZ_SIZE      0x3FFF  /* Buffer Size */
 548
 549 /* EEPROM commands */
 550 #define EEPROM_READ_PREFIX      0x6     /* Read command */
 551 #define EEPROM_PREFIX_LEN       3       /* Start bit and two command bits */
 552
 553 /* EEPROM timing parameters */
 554 #define EECS_DELAY      1       /* Keep EECS low for at least EECS_DELAY
 555                                  * microseconds
 556                                  */
 557 #define EESK_PERIOD     4       /* A cycle of driving EESK high followed by
 558                                  * driving EESK low should take at least
 559                                  * EESK_PERIOD microseconds
 560                                  */
 561
 562 /* Special registers in the 82555 (and compatible) PHYs. Should be moved
 563  * to a separate file if other drivers need this too.
 564  */
 565 #define MII_SCR         0x10    /* Status and Control Register */
 566 #define     MII_SCR_FC          0x8000  /* Flow Control */
 567 #define     MII_SCR_T4E         0x4000  /* Enable T4 unless auto-negotiation */
 568 #define     MII_SCR_CRSDC       0x2000  /* RX100 CRS Disconnect */
 569 #define     MII_SCR_RES         0x1000  /* Reserved */
 570 #define     MII_SCR_RCVSYNC     0x0800  /* RCV De-Serializer in sync */
 571 #define     MII_SCR_100DOWN     0x0400  /* 100Base-T Power Down */
 572 #define     MII_SCR_10DOWN      0x0200  /* 10Base-T Power Down */
 573 #define     MII_SCR_POLARITY    0x0100  /* 10Base-T Polarity */
 574 #define     MII_SCR_RES_1       0x00F8  /* Reserved */
 575 #define     MII_SCR_T4          0x0004  /* 100Base-T4 negotiated */
 576 #define     MII_SCR_100         0x0002  /* 100 Mbps negotiated */
 577 #define     MII_SCR_FD          0x0001  /* Full Duplex negotiated */
 578
 579 /*
 580  * $PchId: fxp.h,v 1.1 2004/11/23 14:34:03 philip Exp $
 581  */
 582
 583 #endif