drivers/e1000/e1000_hw.h

   1 /**
   2  * @file e1000.h
   3  *
   4  * @brief Hardware specific datastructures of the Intel
   5  *        Pro/1000 Gigabit Ethernet card(s).
   6  *
   7  * Parts of this code is based on the DragonflyBSD (FreeBSD)
   8  * implementation, and the fxp driver for Minix 3.
   9  *
  10  * @see http://svn.freebsd.org/viewvc/base/head/sys/dev/e1000/
  11  * @see fxp.c
  12  *
  13  * @author Niek Linnenbank <nieklinnenbank@gmail.com>
  14  * @date September 2009
  15  *
  16  */
  17
  18 #ifndef __E1000_HW_H
  19 #define __E1000_HW_H
  20
  21 #include <stdint.h>
  22
  23 /**
  24  * @name Datastructures.
  25  * @{
  26  */
  27
  28 /**
  29  * @brief Receive Descriptor Format.
  30  */
  31 typedef struct e1000_rx_desc
  32 {
  33     u32_t buffer;       /**< Address of the receive data buffer (64-bit). */
  34     u32_t buffer_h;     /**< High 32-bits of the receive data buffer (unused). */
  35     u16_t length;       /**< Size of the receive buffer. */
  36     u16_t checksum;     /**< Packet checksum. */
  37     u8_t  status;       /**< Descriptor status. */
  38     u8_t  errors;       /**< Descriptor errors. */
  39     u16_t special;      /**< VLAN information. */
  40 }
  41 e1000_rx_desc_t;
  42
  43 /**
  44  * @brief Transmit Descriptor Format.
  45  */
  46 typedef struct e1000_tx_desc
  47 {
  48     u32_t buffer;       /**< Address of the transmit buffer (64-bit). */
  49     u32_t buffer_h;     /**< High 32-bits of the transmit buffer (unused). */
  50     u16_t length;       /**< Size of the transmit buffer contents. */
  51     u8_t  checksum_off; /**< Checksum Offset. */
  52     u8_t  command;      /**< Command field. */
  53     u8_t  status;       /**< Status field. */
  54     u8_t  checksum_st;  /**< Checksum Start. */
  55     u16_t special;      /**< Optional special bits. */
  56 }
  57 e1000_tx_desc_t;
  58
  59 /**
  60  * @brief ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown.
  61  * @see http://gitweb.dragonflybsd.org
  62  */
  63 union ich8_hws_flash_status
  64 {
  65     struct ich8_hsfsts
  66     {
  67         unsigned flcdone    :1; /**< bit 0 Flash Cycle Done */
  68         unsigned flcerr     :1; /**< bit 1 Flash Cycle Error */
  69         unsigned dael       :1; /**< bit 2 Direct Access error Log */
  70         unsigned berasesz   :2; /**< bit 4:3 Sector Erase Size */
  71         unsigned flcinprog  :1; /**< bit 5 flash cycle in Progress */
  72         unsigned reserved1  :2; /**< bit 13:6 Reserved */
  73         unsigned reserved2  :6; /**< bit 13:6 Reserved */
  74         unsigned fldesvalid :1; /**< bit 14 Flash Descriptor Valid */
  75         unsigned flockdn    :1; /**< bit 15 Flash Config Lock-Down */
  76     } hsf_status;
  77     u16_t regval;
  78 };
  79
  80 /**
  81  * @brief ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown.
  82  * @see http://gitweb.dragonflybsd.org
  83  */
  84 union ich8_hws_flash_ctrl
  85 {
  86     struct ich8_hsflctl
  87     {
  88         unsigned flcgo      :1;   /**< 0 Flash Cycle Go */
  89         unsigned flcycle    :2;   /**< 2:1 Flash Cycle */
  90         unsigned reserved   :5;   /**< 7:3 Reserved  */
  91         unsigned fldbcount  :2;   /**< 9:8 Flash Data Byte Count */
  92         unsigned flockdn    :6;   /**< 15:10 Reserved */
  93     } hsf_ctrl;
  94     u16_t regval;
  95 };
  96
  97 /**
  98  * @brief ICH Flash Region Access Permissions.
  99  * @see http://gitweb.dragonflybsd.org
 100  */
 101 union ich8_hws_flash_regacc
 102 {
 103     struct ich8_flracc
 104     {
 105         unsigned grra      :8; /**< 0:7 GbE region Read Access */
 106         unsigned grwa      :8; /**< 8:15 GbE region Write Access */
 107         unsigned gmrag     :8; /**< 23:16 GbE Master Read Access Grant */
 108         unsigned gmwag     :8; /**< 31:24 GbE Master Write Access Grant */
 109     } hsf_flregacc;
 110     u16_t regval;
 111 };
 112
 113 /**
 114  * @}
 115  */
 116
 117 /**
 118  * @name Receive Status Field Bits.
 119  * @{
 120  */
 121
 122 /** Passed In-exact Filter. */
 123 #define E1000_RX_STATUS_PIF     (1 << 7)
 124
 125 /** End of Packet. */
 126 #define E1000_RX_STATUS_EOP     (1 << 1)
 127
 128 /** Descriptor Done. */
 129 #define E1000_RX_STATUS_DONE    (1 << 0)
 130
 131 /**
 132  * @}
 133  */
 134
 135 /**
 136  * @name Receive Errors Field Bits.
 137  * @{
 138  */
 139
 140 /** RX Data Error. */
 141 #define E1000_RX_ERROR_RXE      (1 << 7)
 142
 143 /** Carrier Extension Error. */
 144 #define E1000_RX_ERROR_CXE      (1 << 4)
 145
 146 /** Sequence/Framing Error. */
 147 #define E1000_RX_ERROR_SEQ      (1 << 2)
 148
 149 /** CRC/Alignment Error. */
 150 #define E1000_RX_ERROR_CE       (1 << 0)
 151
 152 /**
 153  * @}
 154  */
 155
 156 /**
 157  * @name Transmit Command Field Bits.
 158  * @{
 159  */
 160
 161 /** End of Packet. */
 162 #define E1000_TX_CMD_EOP        (1 << 0)
 163
 164 /** Insert FCS/CRC. */
 165 #define E1000_TX_CMD_FCS        (1 << 1)
 166
 167 /** Report Status. */
 168 #define E1000_TX_CMD_RS         (1 << 3)
 169
 170 /**
 171  * @}
 172  */
 173
 174 #endif /* __E1000_HW_H */