sys/arch/x86/include/intr.h

   1 /*      $NetBSD: intr.h,v 1.43 2011/08/01 10:42:23 drochner Exp $       */
   2
   3 /*-
   4  * Copyright (c) 1998, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Charles M. Hannum, and by Jason R. Thorpe.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #ifndef _X86_INTR_H_
  33 #define _X86_INTR_H_
  34
  35 #define __HAVE_FAST_SOFTINTS
  36 #define __HAVE_PREEMPTION
  37
  38 #ifdef _KERNEL
  39 #include <sys/types.h>
  40 #else
  41 #include <stdbool.h>
  42 #endif
  43
  44 #include <sys/evcnt.h>
  45 #include <machine/intrdefs.h>
  46
  47 #ifndef _LOCORE
  48 #include <machine/pic.h>
  49
  50 /*
  51  * Struct describing an interrupt source for a CPU. struct cpu_info
  52  * has an array of MAX_INTR_SOURCES of these. The index in the array
  53  * is equal to the stub number of the stubcode as present in vector.s
  54  *
  55  * The primary CPU's array of interrupt sources has its first 16
  56  * entries reserved for legacy ISA irq handlers. This means that
  57  * they have a 1:1 mapping for arrayindex:irq_num. This is not
  58  * true for interrupts that come in through IO APICs, to find
  59  * their source, go through ci->ci_isources[index].is_pic
  60  *
  61  * It's possible to always maintain a 1:1 mapping, but that means
  62  * limiting the total number of interrupt sources to MAX_INTR_SOURCES
  63  * (32), instead of 32 per CPU. It also would mean that having multiple
  64  * IO APICs which deliver interrupts from an equal pin number would
  65  * overlap if they were to be sent to the same CPU.
  66  */
  67
  68 struct intrstub {
  69         void *ist_entry;
  70         void *ist_recurse;
  71         void *ist_resume;
  72 };
  73
  74 struct intrsource {
  75         int is_maxlevel;                /* max. IPL for this source */
  76         int is_pin;                     /* IRQ for legacy; pin for IO APIC,
  77                                            -1 for MSI */
  78         struct intrhand *is_handlers;   /* handler chain */
  79         struct pic *is_pic;             /* originating PIC */
  80         void *is_recurse;               /* entry for spllower */
  81         void *is_resume;                /* entry for doreti */
  82         lwp_t *is_lwp;                  /* for soft interrupts */
  83         struct evcnt is_evcnt;          /* interrupt counter */
  84         int is_flags;                   /* see below */
  85         int is_type;                    /* level, edge */
  86         int is_idtvec;
  87         int is_minlevel;
  88         char is_evname[32];             /* event counter name */
  89 };
  90
  91 #define IS_LEGACY       0x0001          /* legacy ISA irq source */
  92 #define IS_IPI          0x0002
  93 #define IS_LOG          0x0004
  94
  95 /*
  96  * Interrupt handler chains.  *_intr_establish() insert a handler into
  97  * the list.  The handler is called with its (single) argument.
  98  */
  99
 100 struct intrhand {
 101         int     (*ih_fun)(void *);
 102         void    *ih_arg;
 103         int     ih_level;
 104         int     (*ih_realfun)(void *);
 105         void    *ih_realarg;
 106         struct  intrhand *ih_next;
 107         struct  intrhand **ih_prevp;
 108         int     ih_pin;
 109         int     ih_slot;
 110         struct cpu_info *ih_cpu;
 111 };
 112
 113 #define IMASK(ci,level) (ci)->ci_imask[(level)]
 114 #define IUNMASK(ci,level) (ci)->ci_iunmask[(level)]
 115
 116 #ifdef _KERNEL
 117
 118 void Xspllower(int);
 119 void spllower(int);
 120 int splraise(int);
 121 void softintr(int);
 122
 123 /*
 124  * Convert spl level to local APIC level
 125  */
 126
 127 #define APIC_LEVEL(l)   ((l) << 4)
 128
 129 /*
 130  * Miscellaneous
 131  */
 132
 133 #define SPL_ASSERT_BELOW(x) KDASSERT(curcpu()->ci_ilevel < (x))
 134 #define spl0()          spllower(IPL_NONE)
 135 #define splx(x)         spllower(x)
 136
 137 typedef uint8_t ipl_t;
 138 typedef struct {
 139         ipl_t _ipl;
 140 } ipl_cookie_t;
 141
 142 static inline ipl_cookie_t
 143 makeiplcookie(ipl_t ipl)
 144 {
 145
 146         return (ipl_cookie_t){._ipl = ipl};
 147 }
 148
 149 static inline int
 150 splraiseipl(ipl_cookie_t icookie)
 151 {
 152
 153         return splraise(icookie._ipl);
 154 }
 155
 156 #include <sys/spl.h>
 157
 158 /*
 159  * Stub declarations.
 160  */
 161
 162 void Xsoftintr(void);
 163 void Xpreemptrecurse(void);
 164 void Xpreemptresume(void);
 165
 166 extern struct intrstub i8259_stubs[];
 167 extern struct intrstub ioapic_edge_stubs[];
 168 extern struct intrstub ioapic_level_stubs[];
 169
 170 struct cpu_info;
 171
 172 struct pcibus_attach_args;
 173
 174 void intr_default_setup(void);
 175 void x86_nmi(void);
 176 void *intr_establish(int, struct pic *, int, int, int, int (*)(void *), void *, bool);
 177 void intr_disestablish(struct intrhand *);
 178 void intr_add_pcibus(struct pcibus_attach_args *);
 179 const char *intr_string(int);
 180 void cpu_intr_init(struct cpu_info *);
 181 int intr_find_mpmapping(int, int, int *);
 182 struct pic *intr_findpic(int);
 183 void intr_printconfig(void);
 184
 185 int x86_send_ipi(struct cpu_info *, int);
 186 void x86_broadcast_ipi(int);
 187 void x86_ipi_handler(void);
 188
 189 extern void (*ipifunc[X86_NIPI])(struct cpu_info *);
 190
 191 #endif /* _KERNEL */
 192
 193 #endif /* !_LOCORE */
 194
 195 #endif /* !_X86_INTR_H_ */