drivers/dec21140A/dec21140A.h

   1 #ifndef INCL_DEC21041_H_GUARD
   2 #define INCL_DEC21041_H_GUARD
   3 /*
   4 de.h
   5
   6 Header for the driver of the DEC 21140A ethernet card as emulated
   7 by VirtualPC 2007
   8
   9 Created: 09/01/2009   Nicolas Tittley (first.last @ gmail DOT com)
  10 */
  11
  12 #include <sys/null.h>
  13
  14 #define DE_FKEY 7  /* Shift+ this value will dump info on console */
  15
  16 #define NOT(x) (~(x))
  17
  18 #if debug == 1
  19 #       define DEBUG(statm) statm
  20 #else
  21 #       define DEBUG(statm)
  22 #endif
  23
  24
  25 #define SA_ADDR_LEN     sizeof(ether_addr_t)
  26
  27 #define DE_NB_SEND_DESCR    32
  28 #define DE_SEND_BUF_SIZE    (ETH_MAX_PACK_SIZE+2)
  29 #define DE_NB_RECV_DESCR    32
  30 #define DE_RECV_BUF_SIZE    (ETH_MAX_PACK_SIZE+2)
  31 #define IOVEC_NR            16
  32 #define DE_MIN_BASE_ADDR    0x0400
  33 #define DE_SROM_EA_OFFSET   20
  34 #define DE_SETUP_FRAME_SIZE 192
  35
  36
  37 typedef struct iovec_dat_s {
  38   iovec_s_t iod_iovec[IOVEC_NR];
  39   int iod_iovec_s;
  40   endpoint_t iod_proc_nr;
  41   cp_grant_id_t iod_grant;
  42   vir_bytes iod_iovec_offset;
  43 } iovec_dat_s_t;
  44
  45 typedef struct de_descr {
  46   u32_t des[4];
  47 } de_descr_t;
  48
  49 typedef struct de_local_descr {
  50   de_descr_t *descr;
  51   u8_t *buf1;
  52   u8_t *buf2;
  53 } de_loc_descr_t;
  54
  55 typedef struct dpeth {
  56
  57   message rx_return_msg;        /* Holds VREAD message until int */
  58   message tx_return_msg;        /* Holds VWRITE message until int */
  59   char de_name[32];              /* Name of this interface */
  60   port_t de_base_port;          /* Base port, for multiple card instance */
  61   int de_irq;                   /* IRQ line number */
  62   int de_hook;                  /* interrupt hook at kernel */
  63
  64   int de_type;                  /* What kind of hardware */
  65
  66   ether_addr_t de_address;      /* Ethernet Address */
  67   eth_stat_t de_stat;           /* Stats */
  68   unsigned long bytes_tx;       /* Number of bytes sent */
  69   unsigned long bytes_rx;       /* Number of bytes recv */
  70
  71   /* Space reservation. We will allocate all structures later in the code.
  72      here we just make sure we have the space we need at compile time */
  73   u8_t sendrecv_descr_buf[(DE_NB_SEND_DESCR+DE_NB_RECV_DESCR)*
  74                           sizeof(de_descr_t)];
  75   u8_t sendrecv_buf[DE_NB_SEND_DESCR*DE_SEND_BUF_SIZE +
  76                     DE_NB_RECV_DESCR*DE_RECV_BUF_SIZE];
  77   phys_bytes sendrecv_descr_phys_addr[2];
  78   de_loc_descr_t descr[2][MAX(DE_NB_RECV_DESCR, DE_NB_SEND_DESCR)];
  79   int cur_descr[2];
  80
  81 #define DESCR_RECV 0
  82 #define DESCR_TRAN 1
  83
  84   int de_flags;                 /* Send/Receive mode (Configuration) */
  85
  86 #define DEF_EMPTY       0x0000
  87 #define DEF_READING     0x0001
  88 #define DEF_RECV_BUSY   0x0002
  89 #define DEF_ACK_RECV    0x0004
  90 #define DEF_SENDING     0x0010
  91 #define DEF_XMIT_BUSY   0x0020
  92 #define DEF_ACK_SEND    0x0040
  93 #define DEF_PROMISC     0x0100
  94 #define DEF_MULTI       0x0200
  95 #define DEF_BROAD       0x0400
  96 #define DEF_ENABLED     0x2000
  97 #define DEF_STOPPED     0x4000
  98
  99   int de_mode;                  /* Status of the Interface */
 100
 101 #define DEM_DISABLED    0x0000
 102 #define DEM_SINK        0x0001
 103 #define DEM_ENABLED     0x0002
 104
 105
 106   /* Serial ROM */
 107 #define SROM_BITWIDTH 6
 108
 109   u8_t srom[((1<<SROM_BITWIDTH)-1)*2];    /* Space to read in
 110                                              all the configuration ROM */
 111
 112
 113   /* Temporary storage for RECV/SEND requests */
 114   iovec_dat_s_t de_read_iovec;
 115   iovec_dat_s_t de_write_iovec;
 116   vir_bytes de_read_s;
 117   vir_bytes de_send_s;
 118   endpoint_t de_client;
 119
 120 } dpeth_t;
 121
 122
 123 /************/
 124 /* Revisons */
 125 /************/
 126
 127 #define DEC_21140A 0x20
 128 #define DE_TYPE_UNKNOWN 0x0
 129 /* #define CSR_ADDR(x, i) csraddr2(x->de_base_port + i) */
 130 #define CSR_ADDR(x, i) (x->de_base_port + i)
 131
 132 /* CSRs */
 133 #define CSR0 0x00
 134 #define     CSR0_SWR   0x00000001 /* sw reset */
 135 #define     CSR0_BAR   0x00000002 /* bus arbitration */
 136 #define     CSR0_CAL_8 0x00004000 /* cache align 8 long word */
 137 #define     CSR0_TAP   0x00080000 /* trans auto polling */
 138 #define CSR1 0x08 /* transmit poll demand */
 139 #define CSR2 0x10 /* receive poll demand */
 140 #define CSR3 0x18 /* receive list address */
 141 #define CSR4 0x20 /* transmit list address */
 142 #define CSR5 0x28              /* status register */
 143 #define     CSR5_EB  0x03800000 /* error bits */
 144 #define     CSR5_TS  0x00700000 /* Transmit proc state */
 145 #define     CSR5_RS  0x000E0000 /* Receive proc state */
 146 #define     CSR5_NIS 0x00010000 /* Norm Int summ */
 147 #define     CSR5_AIS 0x00008000 /* Abnorm Int sum */
 148 #define     CSR5_FBE 0x00002000 /* Fatal bit error */
 149 #define     CSR5_GTE 0x00000800 /* Gen-purp timer exp */
 150 #define     CSR5_ETI 0x00000400 /* Early Trans int */
 151 #define     CSR5_RWT 0x00000200 /* Recv watchdog timeout */
 152 #define     CSR5_RPS 0x00000100 /* Recv proc stop */
 153 #define     CSR5_RU  0x00000080 /* Recv buf unavail */
 154 #define     CSR5_RI  0x00000040 /* Recv interrupt */
 155 #define     CSR5_UNF 0x00000020 /* Trans underflow */
 156 #define     CSR5_TJT 0x00000008 /* Trans Jabber Timeout */
 157 #define     CSR5_TU  0x00000004 /* Trans buf unavail */
 158 #define     CSR5_TPS 0x00000002 /* Trans proc stopped */
 159 #define     CSR5_TI  0x00000001 /* Trans interrupt */
 160 #define CSR6 0x30 /* Operation mode */
 161 #define     CSR6_SC  0x80000000 /* Special capt effect ena 31 */
 162 #define     CSR6_RA  0x40000000 /* receive all 30 */
 163 #define     CSR6_MBO 0x02000000 /* must be one 25 */
 164 #define     CSR6_SCR 0x01000000 /* Scrambler mode 24 */
 165 #define     CSR6_PCS 0x00800000 /* PCS function 23 */
 166 #define     CSR6_TTM 0x00400000 /* Trans threshold mode 22 */
 167 #define     CSR6_SF  0x00200000 /* store and forward 21 */
 168 #define     CSR6_HBD 0x00080000 /* Heartbeat disable 19 */
 169 #define     CSR6_PS  0x00040000 /* port select 18 */
 170 #define     CSR6_CA  0x00020000 /* Capt effect ena 17 */
 171 #define     CSR6_TR_00 0x00000000 /* Trans thresh 15:14 */
 172 #define     CSR6_TR_01 0x00004000 /* Trans thresh 15:14 */
 173 #define     CSR6_TR_10 0x00008000 /* Trans thresh 15:14 */
 174 #define     CSR6_TR_11 0x0000C000 /* Trans thresh 15:14 */
 175 #define     CSR6_ST  0x00002000 /* start/stop trans 13 */
 176 #define     CSR6_FD  0x00000200 /* Full Duplex 9 */
 177 #define     CSR6_PM  0x00000080 /* Pass all multicast 7 */
 178 #define     CSR6_PR  0x00000040 /* Promisc mode 6 */
 179 #define     CSR6_IF  0x00000010 /* Inv filtering 4 */
 180 #define     CSR6_HO  0x00000004 /* Hash-only filtering 2 */
 181 #define     CSR6_SR  0x00000002 /* start/stop recv 1 */
 182 #define     CSR6_HP  0x00000001 /* Hash/perfect recv filt mode 0 */
 183 #define CSR7 0x38 /* Interrupt enable */
 184 #define     CSR7_NI  0x00010000 /* Normal interrupt ena */
 185 #define     CSR7_AI  0x00008000 /* Abnormal int ena */
 186 #define     CSR7_TI  0x00000001 /* trans int ena */
 187 #define     CSR7_TU  0x00000004 /* trans buf unavail ena */
 188 #define     CSR7_RI  0x00000040 /* recv interp ena */
 189 #define     CSR7_GPT 0x00000800 /* gen purpose timer ena */
 190 #define CSR9 0x48 /* Boot Rom, serial ROM, MII */
 191 #define     CSR9_SR  0x0800 /* serial ROM select */
 192 #define     CSR9_RD  0x4000 /* read */
 193 #define     CSR9_DO  0x0008 /* data out */
 194 #define     CSR9_DI  0x0004 /* data in */
 195 #define     CSR9_SRC 0x0002 /* serial clock */
 196 #define     CSR9_CS  0x0001 /* serial rom chip select */
 197 /* Send/Recv Descriptors */
 198
 199 #define DES0 0
 200 #define  DES0_OWN 0x80000000 /* descr ownership. 1=211140A */
 201 #define  DES0_FL  0x3FFF0000 /* frame length */
 202 #define   DES0_FL_SHIFT 16   /* shift to fix frame length */
 203 #define   DES0_ES 0x00008000 /* Error sum */
 204 #define   DES0_TO 0x00004000 /* Trans jabber timeout */
 205 #define   DES0_LO 0x00000800 /* Loss of carrier */
 206 #define   DES0_NC 0x00000400 /* no carrier */
 207 #define   DES0_LC 0x00000200 /* Late coll */
 208 #define   DES0_EC 0x00000100 /* Excessive coll */
 209 #define   DES0_UF 0x00000002 /* Underflow error */
 210 #define   DES0_RE 0x00000008 /* MII error */
 211 #define   DES0_FS 0x00000200 /* first descr */
 212 #define   DES0_LS 0x00000100 /* last descr */
 213 #define DES1 1
 214 #define  DES1_ER  0x02000000 /* end of ring */
 215 #define  DES1_SAC 0x01000000 /* 2nd address chained */
 216 #define  DES1_BS2 0x003FF800 /* 2nd buffer size */
 217 #define  DES1_BS2_SHFT 11    /* shift to obtain 2nd buffer size */
 218 #define  DES1_BS1 0x000007FF /* 1nd buffer size */
 219 #define  DES1_IC  0x80000000 /* Interrupt on completion 31 */
 220 #define  DES1_LS  0x40000000 /* Last Segment 30 */
 221 #define  DES1_FS  0x20000000 /* First Segment 29 */
 222 #define  DES1_FT1 0x10000000 /* Filtering type 28 */
 223 #define  DES1_SET 0x08000000 /* Setup frame 27 */
 224 #define  DES1_AC  0x04000000 /* Add CRC disable 26 */
 225 #define  DES1_DPD 0x00800000 /* Disabled padding 23 */
 226 #define  DES1_FT0 0x00400000 /* Filtering type 22 */
 227 #define DES2 2 /* 1st buffer addr */
 228 #define DES3 3 /* 2nd buffer addr */
 229
 230 #define DES_BUF1 DES2
 231 #define DES_BUF2 DES3
 232
 233 #endif /* Include Guard */