sys/arch/i386/stand/lib/netif/3c509.h

   1 /*      $NetBSD: 3c509.h,v 1.6 2006/11/24 22:52:16 wiz Exp $    */
   2
   3 /*
   4  * Copyright (c) 1993 Herb Peyerl
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. The name of the author may not be used to endorse or promote products
  13  *    derived from this software without specific prior written permission.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  20  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  21  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  22  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  23  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * if_epreg.h,v 1.4 1994/11/13 10:12:37 gibbs Exp Modified by:
  28  *
  29  October 2, 1994
  30
  31  Modified by: Andres Vega Garcia
  32
  33  INRIA - Sophia Antipolis, France
  34  e-mail: avega@sophia.inria.fr
  35  finger: avega@pax.inria.fr
  36
  37  */
  38
  39 /*
  40  * Ethernet software status per interface.
  41  */
  42 /*
  43  * Some global constants
  44  */
  45 #define ETHER_MIN_LEN        64
  46 #define ETHER_MAX_LEN      1518
  47 #define ETHER_ADDR_LEN        6
  48
  49 #define TX_INIT_RATE         16
  50 #define TX_INIT_MAX_RATE     64
  51 #define RX_INIT_LATENCY      64
  52 #define RX_INIT_EARLY_THRESH 64
  53 #define MIN_RX_EARLY_THRESHF   16 /* not less than ether_header */
  54 #define MIN_RX_EARLY_THRESHL   4
  55
  56 #define EEPROMSIZE      0x40
  57 #define MAX_EEPROMBUSY  1000
  58 #define EP_LAST_TAG     0xd7
  59 #define EP_MAX_BOARDS   16
  60 #define EP_ID_PORT      0x100
  61
  62 /*
  63  * some macros to acces long named fields
  64  */
  65 #define IS_BASE (eth_base)
  66 #define BASE    (eth_base)
  67
  68 /*
  69  * Commands to read/write EEPROM through EEPROM command register (Window 0,
  70  * Offset 0xa)
  71  */
  72 #define EEPROM_CMD_RD    0x0080 /* Read:  Address required (5 bits) */
  73 #define EEPROM_CMD_WR    0x0040 /* Write: Address required (5 bits) */
  74 #define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */
  75 #define EEPROM_CMD_EWEN  0x0030 /* Erase/Write Enable: No data required */
  76
  77 #define EEPROM_BUSY             (1<<15)
  78 #define EEPROM_TST_MODE         (1<<14)
  79
  80 /*
  81  * Some short functions, worth to let them be a macro
  82  */
  83 #define is_eeprom_busy(b) (inw((b)+EP_W0_EEPROM_COMMAND)&EEPROM_BUSY)
  84 #define GO_WINDOW(x)      outw(BASE+EP_COMMAND, WINDOW_SELECT|(x))
  85
  86 /**************************************************************************
  87  *                                                                        *
  88  * These define the EEPROM data structure.  They are used in the probe
  89  * function to verify the existence of the adapter after having sent
  90  * the ID_Sequence.
  91  *
  92  * There are others but only the ones we use are defined here.
  93  *
  94  **************************************************************************/
  95
  96 #define EEPROM_NODE_ADDR_0      0x0     /* Word */
  97 #define EEPROM_NODE_ADDR_1      0x1     /* Word */
  98 #define EEPROM_NODE_ADDR_2      0x2     /* Word */
  99 #define EEPROM_PROD_ID          0x3     /* 0x9[0-f]50 */
 100 #define EEPROM_MFG_ID           0x7     /* 0x6d50 */
 101 #define EEPROM_ADDR_CFG         0x8     /* Base addr */
 102 #define EEPROM_RESOURCE_CFG     0x9     /* IRQ. Bits 12-15 */
 103
 104 /**************************************************************************
 105  *                                                                                *
 106  * These are the registers for the 3Com 3c509 and their bit patterns when *
 107  * applicable.  They have been taken out of the "EtherLink III Parallel   *
 108  * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual *
 109  * from 3com.                                                             *
 110  *                                                                                *
 111  **************************************************************************/
 112
 113 #define EP_COMMAND              0x0e    /* Write. BASE+0x0e is always a
 114                                          * command reg. */
 115 #define EP_STATUS               0x0e    /* Read. BASE+0x0e is always status
 116                                          * reg. */
 117 #define EP_WINDOW               0x0f    /* Read. BASE+0x0f is always window
 118                                          * reg. */
 119 /*
 120  * Window 0 registers. Setup.
 121  */
 122 /* Write */
 123 #define EP_W0_EEPROM_DATA       0x0c
 124 #define EP_W0_EEPROM_COMMAND    0x0a
 125 #define EP_W0_RESOURCE_CFG      0x08
 126 #define EP_W0_ADDRESS_CFG       0x06
 127 #define EP_W0_CONFIG_CTRL       0x04
 128 /* Read */
 129 #define EP_W0_PRODUCT_ID        0x02
 130 #define EP_W0_MFG_ID            0x00
 131
 132 /*
 133  * Window 1 registers. Operating Set.
 134  */
 135 /* Write */
 136 #define EP_W1_TX_PIO_WR_2       0x02
 137 #define EP_W1_TX_PIO_WR_1       0x00
 138 /* Read */
 139 #define EP_W1_FREE_TX           0x0c
 140 #define EP_W1_TX_STATUS         0x0b    /* byte */
 141 #define EP_W1_TIMER             0x0a    /* byte */
 142 #define EP_W1_RX_STATUS         0x08
 143 #define EP_W1_RX_PIO_RD_2       0x02
 144 #define EP_W1_RX_PIO_RD_1       0x00
 145
 146 /*
 147  * Window 2 registers. Station Address Setup/Read
 148  */
 149 /* Read/Write */
 150 #define EP_W2_ADDR_5            0x05
 151 #define EP_W2_ADDR_4            0x04
 152 #define EP_W2_ADDR_3            0x03
 153 #define EP_W2_ADDR_2            0x02
 154 #define EP_W2_ADDR_1            0x01
 155 #define EP_W2_ADDR_0            0x00
 156
 157 /*
 158  * Window 3 registers.  FIFO Management.
 159  */
 160 /* Read */
 161 #define EP_W3_FREE_TX           0x0c
 162 #define EP_W3_FREE_RX           0x0a
 163
 164 /*
 165  * Window 4 registers. Diagnostics.
 166  */
 167 /* Read/Write */
 168 #define EP_W4_MEDIA_TYPE        0x0a
 169 #define EP_W4_CTRLR_STATUS      0x08
 170 #define EP_W4_NET_DIAG          0x06
 171 #define EP_W4_FIFO_DIAG         0x04
 172 #define EP_W4_HOST_DIAG         0x02
 173 #define EP_W4_TX_DIAG           0x00
 174
 175 /*
 176  * Window 5 Registers.  Results and Internal status.
 177  */
 178 /* Read */
 179 #define EP_W5_READ_0_MASK       0x0c
 180 #define EP_W5_INTR_MASK         0x0a
 181 #define EP_W5_RX_FILTER         0x08
 182 #define EP_W5_RX_EARLY_THRESH   0x06
 183 #define EP_W5_TX_AVAIL_THRESH   0x02
 184 #define EP_W5_TX_START_THRESH   0x00
 185
 186 /*
 187  * Window 6 registers. Statistics.
 188  */
 189 /* Read/Write */
 190 #define TX_TOTAL_OK             0x0c
 191 #define RX_TOTAL_OK             0x0a
 192 #define TX_DEFERRALS            0x08
 193 #define RX_FRAMES_OK            0x07
 194 #define TX_FRAMES_OK            0x06
 195 #define RX_OVERRUNS             0x05
 196 #define TX_COLLISIONS           0x04
 197 #define TX_AFTER_1_COLLISION    0x03
 198 #define TX_AFTER_X_COLLISIONS   0x02
 199 #define TX_NO_SQE               0x01
 200 #define TX_CD_LOST              0x00
 201
 202 /****************************************
 203  *
 204  * Register definitions.
 205  *
 206  ****************************************/
 207
 208 /*
 209  * Command register. All windows.
 210  *
 211  * 16 bit register.
 212  *     15-11:  5-bit code for command to be executed.
 213  *     10-0:   11-bit arg if any. For commands with no args;
 214  *            this can be set to anything.
 215  */
 216 #define GLOBAL_RESET            (u_short) 0x0000        /* Wait at least 1ms
 217                                                          * after issuing */
 218 #define WINDOW_SELECT           (u_short) (0x1<<11)
 219 #define START_TRANSCEIVER       (u_short) (0x2<<11)     /* Read ADDR_CFG reg to
 220                                                          * determine whether
 221                                                          * this is needed. If
 222                                                          * so; wait 800 uSec
 223                                                          * before using trans-
 224                                                          * ceiver. */
 225 #define RX_DISABLE              (u_short) (0x3<<11)     /* state disabled on
 226                                                          * power-up */
 227 #define RX_ENABLE               (u_short) (0x4<<11)
 228 #define RX_RESET                (u_short) (0x5<<11)
 229 #define RX_DISCARD_TOP_PACK     (u_short) (0x8<<11)
 230 #define TX_ENABLE               (u_short) (0x9<<11)
 231 #define TX_DISABLE              (u_short) (0xa<<11)
 232 #define TX_RESET                (u_short) (0xb<<11)
 233 #define REQ_INTR                (u_short) (0xc<<11)
 234 #define SET_INTR_MASK           (u_short) (0xe<<11)
 235 #define SET_RD_0_MASK           (u_short) (0xf<<11)
 236 #define SET_RX_FILTER           (u_short) (0x10<<11)
 237 #define FIL_INDIVIDUAL  (u_short) (0x1)
 238 #define FIL_GROUP               (u_short) (0x2)
 239 #define FIL_BRDCST      (u_short) (0x4)
 240 #define FIL_ALL         (u_short) (0x8)
 241 #define SET_RX_EARLY_THRESH     (u_short) (0x11<<11)
 242 #define SET_TX_AVAIL_THRESH     (u_short) (0x12<<11)
 243 #define SET_TX_START_THRESH     (u_short) (0x13<<11)
 244 #define STATS_ENABLE            (u_short) (0x15<<11)
 245 #define STATS_DISABLE           (u_short) (0x16<<11)
 246 #define STOP_TRANSCEIVER        (u_short) (0x17<<11)
 247 /*
 248  * The following C_* acknowledge the various interrupts. Some of them don't
 249  * do anything.  See the manual.
 250  */
 251 #define ACK_INTR                (u_short) (0x6800)
 252 #define C_INTR_LATCH    (u_short) (ACK_INTR|0x1)
 253 #define C_CARD_FAILURE  (u_short) (ACK_INTR|0x2)
 254 #define C_TX_COMPLETE   (u_short) (ACK_INTR|0x4)
 255 #define C_TX_AVAIL      (u_short) (ACK_INTR|0x8)
 256 #define C_RX_COMPLETE   (u_short) (ACK_INTR|0x10)
 257 #define C_RX_EARLY      (u_short) (ACK_INTR|0x20)
 258 #define C_INT_RQD               (u_short) (ACK_INTR|0x40)
 259 #define C_UPD_STATS     (u_short) (ACK_INTR|0x80)
 260
 261 /*
 262  * Status register. All windows.
 263  *
 264  *     15-13:  Window number(0-7).
 265  *     12:     Command_in_progress.
 266  *     11:     reserved.
 267  *     10:     reserved.
 268  *     9:      reserved.
 269  *     8:      reserved.
 270  *     7:      Update Statistics.
 271  *     6:      Interrupt Requested.
 272  *     5:      RX Early.
 273  *     4:      RX Complete.
 274  *     3:      TX Available.
 275  *     2:      TX Complete.
 276  *     1:      Adapter Failure.
 277  *     0:      Interrupt Latch.
 278  */
 279 #define S_INTR_LATCH            (u_short) (0x1)
 280 #define S_CARD_FAILURE          (u_short) (0x2)
 281 #define S_TX_COMPLETE           (u_short) (0x4)
 282 #define S_TX_AVAIL              (u_short) (0x8)
 283 #define S_RX_COMPLETE           (u_short) (0x10)
 284 #define S_RX_EARLY              (u_short) (0x20)
 285 #define S_INT_RQD               (u_short) (0x40)
 286 #define S_UPD_STATS             (u_short) (0x80)
 287 #define S_5_INTS                (S_CARD_FAILURE|S_TX_COMPLETE|\
 288                                  S_TX_AVAIL|S_RX_COMPLETE|S_RX_EARLY)
 289 #define S_COMMAND_IN_PROGRESS   (u_short) (0x1000)
 290
 291 /*
 292  * FIFO Registers.
 293  * RX Status. Window 1/Port 08
 294  *
 295  *     15:     Incomplete or FIFO empty.
 296  *     14:     1: Error in RX Packet   0: Incomplete or no error.
 297  *     13-11:  Type of error.
 298  *            1000 = Overrun.
 299  *            1011 = Run Packet Error.
 300  *            1100 = Alignment Error.
 301  *            1101 = CRC Error.
 302  *            1001 = Oversize Packet Error (>1514 bytes)
 303  *            0010 = Dribble Bits.
 304  *            (all other error codes, no errors.)
 305  *
 306  *     10-0:   RX Bytes (0-1514)
 307  */
 308 #define ERR_RX_INCOMPLETE  (u_short) (0x1<<15)
 309 #define ERR_RX             (u_short) (0x1<<14)
 310 #define ERR_RX_OVERRUN     (u_short) (0x8<<11)
 311 #define ERR_RX_RUN_PKT     (u_short) (0xb<<11)
 312 #define ERR_RX_ALIGN       (u_short) (0xc<<11)
 313 #define ERR_RX_CRC         (u_short) (0xd<<11)
 314 #define ERR_RX_OVERSIZE    (u_short) (0x9<<11)
 315 #define ERR_RX_DRIBBLE     (u_short) (0x2<<11)
 316
 317 /*
 318  * FIFO Registers.
 319  * TX Status. Window 1/Port 0B
 320  *
 321  *   Reports the transmit status of a completed transmission. Writing this
 322  *   register pops the transmit completion stack.
 323  *
 324  *   Window 1/Port 0x0b.
 325  *
 326  *     7:      Complete
 327  *     6:      Interrupt on successful transmission requested.
 328  *     5:      Jabber Error (TP Only, TX Reset required. )
 329  *     4:      Underrun (TX Reset required. )
 330  *     3:      Maximum Collisions.
 331  *     2:      TX Status Overflow.
 332  *     1-0:    Undefined.
 333  *
 334  */
 335 #define TXS_COMPLETE            0x80
 336 #define TXS_SUCCES_INTR_REQ             0x40
 337 #define TXS_JABBER              0x20
 338 #define TXS_UNDERRUN            0x10
 339 #define TXS_MAX_COLLISION       0x8
 340 #define TXS_STATUS_OVERFLOW     0x4
 341
 342 /*
 343  * Configuration control register.
 344  * Window 0/Port 04
 345  */
 346 /* Read */
 347 #define IS_AUI                          (1<<13)
 348 #define IS_BNC                          (1<<12)
 349 #define IS_UTP                          (1<<9)
 350 /* Write */
 351 #define ENABLE_DRQ_IRQ                  0x0001
 352 #define W0_P4_CMD_RESET_ADAPTER       0x4
 353 #define W0_P4_CMD_ENABLE_ADAPTER      0x1
 354 /*
 355  * Media type and status.
 356  * Window 4/Port 0A
 357  */
 358 #define ENABLE_UTP                      0xc0
 359 #define DISABLE_UTP                     0x0
 360
 361 /*
 362  * Resource control register
 363  */
 364
 365 #define SET_IRQ(i)      ( ((i)<<12) | 0xF00) /* set IRQ i */
 366
 367 /*
 368  * Receive status register
 369  */
 370
 371 #define RX_BYTES_MASK                   (u_short) (0x07ff)
 372 #define RX_ERROR        0x4000
 373 #define RX_INCOMPLETE   0x8000
 374
 375
 376 /*
 377  * Misc defines for various things.
 378  */
 379 #define ACTIVATE_ADAPTER_TO_CONFIG      0xff /* to the id_port */
 380 #define MFG_ID                          0x6d50 /* in EEPROM and W0 ADDR_CONFIG */
 381 #define PROD_ID                         0x9150
 382
 383 #define AUI                             0x1
 384 #define BNC                             0x2
 385 #define UTP                             0x4
 386
 387 #define ETHER_ADDR_LEN                  6
 388 #define ETHER_MAX                       1536
 389 #define RX_BYTES_MASK                   (u_short) (0x07ff)
 390
 391  /* EISA support */
 392 #define EP_EISA_START                    0x1000
 393 #define EP_EISA_W0                       0x0c80