drivers/audio/es1370/es1370.c

   1 /* Best viewed with tabsize 4 */
   2
   3 /* Ensoniq ES1370 driver
   4  *
   5  * aka AudioPCI '97
   6  *
   7  * This is the main file of the ES1370 sound driver. There is no main function
   8  * over here, instead the main function is located in the generic dma driver.
   9  * All this driver does is implement the interface audio/audio_fw.h. All
  10  * functions having the prefix 'drv_' are dictated by audio/audio_fw.h. The
  11  * function prototypes you see below define a set of private helper functions.
  12  * Control over the AK4531 codec is delegated ak4531.c.
  13  *
  14  * September 2007    ES1370 driver (Pieter Hijma),
  15  * based on ES1371 driver by Laurens Bronwasser
  16  */
  17
  18 #include <machine/pci.h>
  19
  20 #include <minix/audio_fw.h>
  21 #include "es1370.h"
  22 #include "ak4531.h"
  23 #include "pci_helper.h"
  24
  25
  26 /* reg(n) will be the device specific addresses */
  27 #define reg(n) (dev.base + (n))
  28
  29
  30 /* prototypes of private functions */
  31 static int detect_hw(void);
  32 static int disable_int(int sub_dev);
  33 static int set_stereo(u32_t stereo, int sub_dev);
  34 static int set_bits(u32_t nr_of_bits, int sub_dev);
  35 static int set_sample_rate(u32_t rate, int sub_dev);
  36 static int set_sign(u32_t val, int sub_dev);
  37 static int get_max_frag_size(u32_t * val, int *len, int sub_dev);
  38 static int set_frag_size(u32_t fragment_size, int sub_dev);
  39 static int set_int_cnt(int sub_dev);
  40 static int free_buf(u32_t *val, int *len, int sub_dev);
  41 static int get_samples_in_buf(u32_t *val, int *len, int sub_dev);
  42 static int get_set_volume(struct volume_level *level, int *len, int
  43         sub_dev, int flag);
  44 static int reset(int sub_dev);
  45
  46
  47 DEV_STRUCT dev;
  48 aud_sub_dev_conf_t aud_conf[4];
  49
  50
  51 sub_dev_t sub_dev[4];
  52 special_file_t special_file[4];
  53 drv_t drv;
  54
  55
  56 int drv_init(void) {
  57         drv.DriverName = DRIVER_NAME;
  58         drv.NrOfSubDevices = 4;
  59         drv.NrOfSpecialFiles = 4;
  60
  61         sub_dev[DAC1_CHAN].readable = 0;
  62         sub_dev[DAC1_CHAN].writable = 1;
  63         sub_dev[DAC1_CHAN].DmaSize = 64 * 1024;
  64         sub_dev[DAC1_CHAN].NrOfDmaFragments = 2;
  65         sub_dev[DAC1_CHAN].MinFragmentSize = 1024;
  66         sub_dev[DAC1_CHAN].NrOfExtraBuffers = 4;
  67
  68         sub_dev[ADC1_CHAN].readable = 1;
  69         sub_dev[ADC1_CHAN].writable = 0;
  70         sub_dev[ADC1_CHAN].DmaSize = 64 * 1024;
  71         sub_dev[ADC1_CHAN].NrOfDmaFragments = 2;
  72         sub_dev[ADC1_CHAN].MinFragmentSize = 1024;
  73         sub_dev[ADC1_CHAN].NrOfExtraBuffers = 4;
  74
  75         sub_dev[MIXER].writable = 0;
  76         sub_dev[MIXER].readable = 0;
  77
  78         sub_dev[DAC2_CHAN].readable = 0;
  79         sub_dev[DAC2_CHAN].writable = 1;
  80         sub_dev[DAC2_CHAN].DmaSize = 64 * 1024;
  81         sub_dev[DAC2_CHAN].NrOfDmaFragments = 2;
  82         sub_dev[DAC2_CHAN].MinFragmentSize = 1024;
  83         sub_dev[DAC2_CHAN].NrOfExtraBuffers = 4;
  84
  85         special_file[0].minor_dev_nr = 0;
  86         special_file[0].write_chan = DAC1_CHAN;
  87         special_file[0].read_chan = NO_CHANNEL;
  88         special_file[0].io_ctl = DAC1_CHAN;
  89
  90         special_file[1].minor_dev_nr = 1;
  91         special_file[1].write_chan = NO_CHANNEL;
  92         special_file[1].read_chan = ADC1_CHAN;
  93         special_file[1].io_ctl = ADC1_CHAN;
  94
  95         special_file[2].minor_dev_nr = 2;
  96         special_file[2].write_chan = NO_CHANNEL;
  97         special_file[2].read_chan = NO_CHANNEL;
  98         special_file[2].io_ctl = MIXER;
  99
 100         special_file[3].minor_dev_nr = 3;
 101         special_file[3].write_chan = DAC2_CHAN;
 102         special_file[3].read_chan = NO_CHANNEL;
 103         special_file[3].io_ctl = DAC2_CHAN;
 104
 105         return OK;
 106 }
 107
 108
 109 int drv_init_hw (void) {
 110         u16_t i, j;
 111         u16_t chip_sel_ctrl_reg;
 112
 113         /* First, detect the hardware */
 114         if (detect_hw() != OK) {
 115                 return EIO;
 116         }
 117
 118         /* PCI command register
 119          * enable the SERR# driver, PCI bus mastering and I/O access
 120          */
 121         pci_attr_w16 (dev.devind, PCI_CR, SERR_EN|PCI_MASTER|IO_ACCESS);
 122
 123         /* turn everything off */
 124         pci_outl(reg(CHIP_SEL_CTRL),  0x0UL);
 125
 126         /* turn off legacy (legacy control is undocumented) */
 127         pci_outl(reg(LEGACY), 0x0UL);
 128         pci_outl(reg(LEGACY+4), 0x0UL);
 129
 130         /* turn off serial interface */
 131         pci_outl(reg(SERIAL_INTERFACE_CTRL), 0x0UL);
 132         /*pci_outl(reg(SERIAL_INTERFACE_CTRL), 0x3UL);*/
 133
 134
 135         /* enable the codec */
 136         chip_sel_ctrl_reg = pci_inw(reg(CHIP_SEL_CTRL));
 137         chip_sel_ctrl_reg |= XCTL0 | CDC_EN;
 138         pci_outw(reg(CHIP_SEL_CTRL), chip_sel_ctrl_reg);
 139
 140         /* initialize the codec */
 141         if (ak4531_init(reg(CODEC_WRITE_ADDRESS),
 142                                 reg(INTERRUPT_STATUS), CWRIP, reg(0)) < 0) {
 143                 return EINVAL;
 144         }
 145
 146         /* clear all the memory */
 147         for (i = 0; i < 0x10; ++i) {
 148                 pci_outb(reg(MEM_PAGE), i);
 149                 for (j = 0; j < 0x10; j += 4) {
 150                         pci_outl  (reg(MEMORY) + j, 0x0UL);
 151                 }
 152         }
 153
 154         /* initialize variables for each sub_device */
 155         for (i = 0; i < drv.NrOfSubDevices; i++) {
 156                 if(i != MIXER) {
 157                         aud_conf[i].busy = 0;
 158                         aud_conf[i].stereo = DEFAULT_STEREO;
 159                         aud_conf[i].sample_rate = DEFAULT_RATE;
 160                         aud_conf[i].nr_of_bits = DEFAULT_NR_OF_BITS;
 161                         aud_conf[i].sign = DEFAULT_SIGNED;
 162                         aud_conf[i].fragment_size =
 163                                 sub_dev[i].DmaSize / sub_dev[i].NrOfDmaFragments;
 164                 }
 165         }
 166         return OK;
 167 }
 168
 169
 170 static int detect_hw(void) {
 171         u32_t device;
 172         int devind;
 173         u16_t v_id, d_id;
 174
 175         /* detect_hw tries to find device and get IRQ and base address
 176            with a little (much) help from the PCI library.
 177            This code is quite device independent and you can copy it.
 178            (just make sure to get the bugs out first)*/
 179
 180         pci_init();
 181         /* get first device and then search through the list */
 182         device = pci_first_dev(&devind, &v_id, &d_id);
 183         while( device > 0 ) {
 184                 /* if we have a match...break */
 185                 if (v_id == VENDOR_ID && d_id == DEVICE_ID) break;
 186                 device = pci_next_dev(&devind, &v_id, &d_id);
 187         }
 188
 189         /* did we find anything? */
 190         if (v_id != VENDOR_ID || d_id != DEVICE_ID) {
 191                 return EIO;
 192         }
 193
 194         pci_reserve(devind);
 195
 196         dev.name = pci_dev_name(v_id, d_id);
 197
 198         /* get base address of our device, ignore least signif. bit
 199            this last bit thing could be device dependent, i don't know */
 200         dev.base = pci_attr_r32(devind, PCI_BAR) & 0xfffffffe;
 201
 202         /* get IRQ */
 203         dev.irq = pci_attr_r8(devind, PCI_ILR);
 204         dev.revision = pci_attr_r8(devind, PCI_REV);
 205         dev.d_id = d_id;
 206         dev.v_id = v_id;
 207         dev.devind = devind; /* pci device identifier */
 208
 209         return OK;
 210 }
 211
 212
 213 static int reset(int chan) {
 214         drv_stop(chan);
 215         sub_dev[chan].OutOfData = 1;
 216
 217         return OK;
 218 }
 219
 220
 221 int drv_reset() {
 222         return OK;
 223 }
 224
 225
 226 int drv_start(int sub_dev, int UNUSED(DmaMode)) {
 227         u32_t enable_bit, result = 0;
 228
 229         /* Write default values to device in case user failed to configure.
 230            If user did configure properly, everything is written twice.
 231            please raise your hand if you object against to this strategy...*/
 232         result |= set_sample_rate(aud_conf[sub_dev].sample_rate, sub_dev);
 233         result |= set_stereo(aud_conf[sub_dev].stereo, sub_dev);
 234         result |= set_bits(aud_conf[sub_dev].nr_of_bits, sub_dev);
 235         result |= set_sign(aud_conf[sub_dev].sign, sub_dev);
 236
 237         /* set the interrupt count */
 238         result |= set_int_cnt(sub_dev);
 239
 240         if (result) {
 241                 return EIO;
 242         }
 243
 244         /* if device currently paused, resume */
 245         drv_resume(sub_dev);
 246
 247         switch(sub_dev) {
 248                 case ADC1_CHAN: enable_bit = ADC1_EN;break;
 249                 case DAC1_CHAN: enable_bit = DAC1_EN;break;
 250                 case DAC2_CHAN: enable_bit = DAC2_EN;break;
 251                 default: return EINVAL;
 252         }
 253
 254         /* enable interrupts from 'sub device' */
 255         drv_reenable_int(sub_dev);
 256
 257         /* this means play!!! */
 258         pci_outw(reg(CHIP_SEL_CTRL), pci_inw(reg(CHIP_SEL_CTRL)) | enable_bit);
 259
 260         aud_conf[sub_dev].busy = 1;
 261
 262                 return OK;
 263 }
 264
 265
 266 int drv_stop(int sub_dev)
 267 {
 268         u32_t enable_bit;
 269         int status;
 270
 271         switch(sub_dev) {
 272                 case ADC1_CHAN: enable_bit = ADC1_EN;break;
 273                 case DAC1_CHAN: enable_bit = DAC1_EN;break;
 274                 case DAC2_CHAN: enable_bit = DAC2_EN;break;
 275                 default: return EINVAL;
 276         }
 277
 278         /* stop the specified channel */
 279         pci_outw(reg(CHIP_SEL_CTRL),
 280                         pci_inw(reg(CHIP_SEL_CTRL)) & ~enable_bit);
 281         aud_conf[sub_dev].busy = 0;
 282         status = disable_int(sub_dev);
 283
 284         return status;
 285 }
 286
 287
 288 /* all IO-ctl's sent to the upper driver are passed to this function */
 289 int drv_io_ctl(int request, void * val, int * len, int sub_dev) {
 290
 291         int status;
 292
 293         switch(request) {
 294                 case DSPIORATE:
 295                         status = set_sample_rate(*((u32_t *) val), sub_dev); break;
 296                 case DSPIOSTEREO:
 297                         status = set_stereo(*((u32_t *) val), sub_dev); break;
 298                 case DSPIOBITS:
 299                         status = set_bits(*((u32_t *) val), sub_dev); break;
 300                 case DSPIOSIZE:
 301                         status = set_frag_size(*((u32_t *) val), sub_dev); break;
 302                 case DSPIOSIGN:
 303                         status = set_sign(*((u32_t *) val), sub_dev); break;
 304                 case DSPIOMAX:
 305                         status = get_max_frag_size(val, len, sub_dev); break;
 306                 case DSPIORESET:
 307                         status = reset(sub_dev); break;
 308                 case DSPIOFREEBUF:
 309                         status = free_buf(val, len, sub_dev); break;
 310                 case DSPIOSAMPLESINBUF:
 311                         status = get_samples_in_buf(val, len, sub_dev); break;
 312                 case DSPIOPAUSE:
 313                         status = drv_pause(sub_dev); break;
 314                 case DSPIORESUME:
 315                         status = drv_resume(sub_dev); break;
 316                 case MIXIOGETVOLUME:
 317                         status = get_set_volume(val, len, sub_dev, 0); break;
 318                 case MIXIOSETVOLUME:
 319                         status = get_set_volume(val, len, sub_dev, 1); break;
 320                 default:
 321                         status = EINVAL; break;
 322         }
 323
 324         return status;
 325 }
 326
 327
 328 int drv_get_irq(char *irq) {
 329         *irq = dev.irq;
 330         return OK;
 331 }
 332
 333
 334 int drv_get_frag_size(u32_t *frag_size, int sub_dev) {
 335         *frag_size = aud_conf[sub_dev].fragment_size;
 336         return OK;
 337 }
 338
 339
 340 int drv_set_dma(u32_t dma, u32_t length, int chan) {
 341         /* dma length in bytes,
 342            max is 64k long words for es1370 = 256k bytes */
 343         u32_t page, frame_count_reg, dma_add_reg;
 344
 345         switch(chan) {
 346                 case ADC1_CHAN: page = ADC_MEM_PAGE;
 347                                                 frame_count_reg = ADC_BUFFER_SIZE;
 348                                                 dma_add_reg = ADC_PCI_ADDRESS;
 349                                                 break;
 350                 case DAC1_CHAN: page = DAC_MEM_PAGE;
 351                                                 frame_count_reg = DAC1_BUFFER_SIZE;
 352                                                 dma_add_reg = DAC1_PCI_ADDRESS;
 353                                                 break;
 354                 case DAC2_CHAN: page = DAC_MEM_PAGE;
 355                                                 frame_count_reg = DAC2_BUFFER_SIZE;
 356                                                 dma_add_reg = DAC2_PCI_ADDRESS;
 357                                                 break;
 358                 default: return EIO;
 359         }
 360         pci_outb(reg(MEM_PAGE), page);
 361         pci_outl(reg(dma_add_reg), dma);
 362
 363         /* device expects long word count in stead of bytes */
 364         length /= 4;
 365
 366         /* It seems that register _CURRENT_COUNT is overwritten, but this is
 367          * the way to go. The register frame_count_reg is only longword
 368          * addressable.
 369          * It expects length -1
 370          */
 371         pci_outl(reg(frame_count_reg), (u32_t) (length - 1));
 372
 373         return OK;
 374 }
 375
 376
 377 /* return status of the interrupt summary bit */
 378 int drv_int_sum(void) {
 379         return pci_inl(reg(INTERRUPT_STATUS)) & INTR;
 380 }
 381
 382
 383 int drv_int(int sub_dev) {
 384         u32_t int_status;
 385         u32_t bit;
 386
 387         /* return status of interrupt bit of specified channel*/
 388         switch (sub_dev) {
 389                 case DAC1_CHAN:  bit = DAC1; break;
 390                 case DAC2_CHAN:  bit = DAC2; break;
 391                 case ADC1_CHAN:  bit = ADC; break;
 392                 default: return EINVAL;
 393         }
 394
 395         int_status = pci_inl(reg(INTERRUPT_STATUS)) & bit;
 396
 397         return int_status;
 398 }
 399
 400
 401 int drv_reenable_int(int chan) {
 402         u16_t ser_interface, int_en_bit;
 403
 404         switch(chan) {
 405                 case ADC1_CHAN: int_en_bit = R1_INT_EN; break;
 406                 case DAC1_CHAN: int_en_bit = P1_INTR_EN; break;
 407                 case DAC2_CHAN: int_en_bit = P2_INTR_EN; break;
 408                 default: return EINVAL;
 409         }
 410
 411         /* clear and reenable an interrupt */
 412         ser_interface = pci_inw(reg(SERIAL_INTERFACE_CTRL));
 413         pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface & ~int_en_bit);
 414         pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface | int_en_bit);
 415
 416         return OK;
 417 }
 418
 419
 420 int drv_pause(int sub_dev) {
 421         u32_t pause_bit;
 422
 423         disable_int(sub_dev); /* don't send interrupts */
 424
 425         switch(sub_dev) {
 426                 case DAC1_CHAN: pause_bit = P1_PAUSE;break;
 427                 case DAC2_CHAN: pause_bit = P2_PAUSE;break;
 428                 default: return EINVAL;
 429         }
 430
 431         /* pause */
 432         pci_outl(reg(SERIAL_INTERFACE_CTRL),
 433                         pci_inl(reg(SERIAL_INTERFACE_CTRL)) | pause_bit);
 434
 435         return OK;
 436 }
 437
 438
 439 int drv_resume(int sub_dev) {
 440         u32_t pause_bit = 0;
 441
 442         drv_reenable_int(sub_dev); /* enable interrupts */
 443
 444         switch(sub_dev) {
 445                 case DAC1_CHAN: pause_bit = P1_PAUSE;break;
 446                 case DAC2_CHAN: pause_bit = P2_PAUSE;break;
 447                 default: return EINVAL;
 448         }
 449
 450         /* clear pause bit */
 451         pci_outl(reg(SERIAL_INTERFACE_CTRL),
 452                         pci_inl(reg(SERIAL_INTERFACE_CTRL)) & ~pause_bit);
 453
 454         return OK;
 455 }
 456
 457
 458 static int set_bits(u32_t nr_of_bits, int sub_dev) {
 459         /* set format bits for specified channel. */
 460         u16_t size_16_bit, ser_interface;
 461
 462         switch(sub_dev) {
 463                 case ADC1_CHAN: size_16_bit = R1_S_EB; break;
 464                 case DAC1_CHAN: size_16_bit = P1_S_EB; break;
 465                 case DAC2_CHAN: size_16_bit = P2_S_EB; break;
 466                 default: return EINVAL;
 467         }
 468
 469         ser_interface = pci_inw(reg(SERIAL_INTERFACE_CTRL));
 470         ser_interface &= ~size_16_bit;
 471         switch(nr_of_bits) {
 472                 case 16: ser_interface |= size_16_bit;break;
 473                 case  8: break;
 474                 default: return EINVAL;
 475         }
 476         pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface);
 477         aud_conf[sub_dev].nr_of_bits = nr_of_bits;
 478         return OK;
 479 }
 480
 481
 482 static int set_stereo(u32_t stereo, int sub_dev) {
 483         /* set format bits for specified channel. */
 484         u16_t stereo_bit, ser_interface;
 485
 486         switch(sub_dev) {
 487                 case ADC1_CHAN: stereo_bit = R1_S_MB; break;
 488                 case DAC1_CHAN: stereo_bit = P1_S_MB; break;
 489                 case DAC2_CHAN: stereo_bit = P2_S_MB; break;
 490                 default: return EINVAL;
 491         }
 492         ser_interface = pci_inw(reg(SERIAL_INTERFACE_CTRL));
 493         ser_interface &= ~stereo_bit;
 494         if (stereo) {
 495                 ser_interface |= stereo_bit;
 496         }
 497         pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface);
 498         aud_conf[sub_dev].stereo = stereo;
 499
 500         return OK;
 501 }
 502
 503
 504 static int set_sign(u32_t UNUSED(val), int UNUSED(sub_dev)) {
 505         return OK;
 506 }
 507
 508
 509 static int set_frag_size(u32_t fragment_size, int sub_dev_nr) {
 510         if (fragment_size > (sub_dev[sub_dev_nr].DmaSize /
 511                                 sub_dev[sub_dev_nr].NrOfDmaFragments) ||
 512                         fragment_size < sub_dev[sub_dev_nr].MinFragmentSize) {
 513                 return EINVAL;
 514         }
 515         aud_conf[sub_dev_nr].fragment_size = fragment_size;
 516
 517         return OK;
 518 }
 519
 520
 521 static int set_sample_rate(u32_t rate, int sub_dev) {
 522         /* currently only 44.1kHz */
 523         u32_t controlRegister;
 524
 525         if (rate > MAX_RATE || rate < MIN_RATE) {
 526                 return EINVAL;
 527         }
 528
 529         controlRegister = pci_inl(reg(CHIP_SEL_CTRL));
 530         controlRegister |= FREQ_44K100;
 531         pci_outl(reg(CHIP_SEL_CTRL), controlRegister);
 532
 533         aud_conf[sub_dev].sample_rate = rate;
 534
 535         return OK;
 536 }
 537
 538
 539 static int set_int_cnt(int chan) {
 540         /* Write interrupt count for specified channel.
 541            After <DspFragmentSize> bytes, an interrupt will be generated  */
 542
 543         int sample_count;
 544         u16_t int_cnt_reg;
 545
 546         if (aud_conf[chan].fragment_size >
 547                         (sub_dev[chan].DmaSize / sub_dev[chan].NrOfDmaFragments)
 548                         || aud_conf[chan].fragment_size < sub_dev[chan].MinFragmentSize) {
 549                 return EINVAL;
 550         }
 551
 552         switch(chan) {
 553                 case ADC1_CHAN: int_cnt_reg = ADC_SAMP_CT; break;
 554                 case DAC1_CHAN: int_cnt_reg = DAC1_SAMP_CT; break;
 555                 case DAC2_CHAN: int_cnt_reg = DAC2_SAMP_CT; break;
 556                 default: return EINVAL;
 557         }
 558
 559         sample_count = aud_conf[chan].fragment_size;
 560
 561         /* adjust sample count according to sample format */
 562         if( aud_conf[chan].stereo == TRUE ) sample_count >>= 1;
 563         switch(aud_conf[chan].nr_of_bits) {
 564                 case 16:   sample_count >>= 1;break;
 565                 case  8:   break;
 566                 default: return EINVAL;
 567         }
 568
 569         /* set the sample count - 1 for the specified channel. */
 570         pci_outw(reg(int_cnt_reg), sample_count - 1);
 571
 572         return OK;
 573 }
 574
 575
 576 static int get_max_frag_size(u32_t * val, int * len, int sub_dev_nr) {
 577         *len = sizeof(*val);
 578         *val = (sub_dev[sub_dev_nr].DmaSize /
 579                         sub_dev[sub_dev_nr].NrOfDmaFragments);
 580         return OK;
 581 }
 582
 583
 584 static int disable_int(int chan) {
 585         u16_t ser_interface, int_en_bit;
 586
 587         switch(chan) {
 588                 case ADC1_CHAN: int_en_bit = R1_INT_EN; break;
 589                 case DAC1_CHAN: int_en_bit = P1_INTR_EN; break;
 590                 case DAC2_CHAN: int_en_bit = P2_INTR_EN; break;
 591                 default: return EINVAL;
 592         }
 593         /* clear the interrupt */
 594         ser_interface = pci_inw(reg(SERIAL_INTERFACE_CTRL));
 595         pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface & ~int_en_bit);
 596         return OK;
 597 }
 598
 599
 600 static int get_samples_in_buf (u32_t *samples_in_buf, int *len, int chan) {
 601         u16_t samp_ct_reg;
 602         u16_t curr_samp_ct_reg;
 603         u16_t curr_samp_ct; /* counts back from SAMP_CT till 0 */
 604
 605         *len = sizeof(*samples_in_buf);
 606
 607         switch(chan) {
 608                 case ADC1_CHAN:
 609                         curr_samp_ct_reg = ADC_CURR_SAMP_CT;
 610                         samp_ct_reg = ADC_SAMP_CT; break;
 611                 case DAC1_CHAN:
 612                         curr_samp_ct_reg = DAC1_CURR_SAMP_CT;
 613                         samp_ct_reg = DAC1_SAMP_CT; break;
 614                 case DAC2_CHAN:
 615                         curr_samp_ct_reg = DAC2_CURR_SAMP_CT;
 616                         samp_ct_reg = DAC2_SAMP_CT; break;
 617                 default: return EINVAL;
 618         }
 619
 620         /* TODO: is this inw useful? */
 621         (void) pci_inw(reg(samp_ct_reg));
 622         curr_samp_ct = pci_inw(reg(curr_samp_ct_reg));
 623
 624         *samples_in_buf = (u32_t) (sub_dev[chan].BufLength * 8192) +
 625                 curr_samp_ct;
 626
 627         return OK;
 628 }
 629
 630
 631 /* returns 1 if there are free buffers */
 632 static int free_buf (u32_t *val, int *len, int sub_dev_nr) {
 633         *len = sizeof(*val);
 634         if (sub_dev[sub_dev_nr].BufLength ==
 635                         sub_dev[sub_dev_nr].NrOfExtraBuffers) {
 636                 *val = 0;
 637         }
 638         else {
 639                 *val = 1;
 640         }
 641         return OK;
 642 }
 643
 644
 645 static int get_set_volume(struct volume_level *level, int *len, int sub_dev,
 646                 int flag) {
 647         *len = sizeof(struct volume_level);
 648         if (sub_dev == MIXER) {
 649                 return ak4531_get_set_volume(level, flag);
 650         }
 651         else {
 652                 return EINVAL;
 653         }
 654 }