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add/re-enable at_wini debug output
[minix3.git] / drivers / at_wini / at_wini.c
bloba24c358e5e97b2e58d18212943a1034a21066e56
1 /* This file contains the device dependent part of a driver for the IBM-AT
2 * winchester controller. Written by Adri Koppes.
3 *
4 * The file contains one entry point:
5 *
6 * at_winchester_task: main entry when system is brought up
7 *
8 * Changes:
9 * Aug 19, 2005 ATA PCI support, supports SATA (Ben Gras)
10 * Nov 18, 2004 moved AT disk driver to user-space (Jorrit N. Herder)
11 * Aug 20, 2004 watchdogs replaced by sync alarms (Jorrit N. Herder)
12 * Mar 23, 2000 added ATAPI CDROM support (Michael Temari)
13 * May 14, 2000 d-d/i rewrite (Kees J. Bot)
14 * Apr 13, 1992 device dependent/independent split (Kees J. Bot)
15 */
16
17 #include "at_wini.h"
18
19 #include <minix/sysutil.h>
20 #include <minix/keymap.h>
21 #include <sys/ioc_disk.h>
22 #include <ibm/pci.h>
23
24 #define ATAPI_DEBUG 0 /* To debug ATAPI code. */
25
26 /* I/O Ports used by winchester disk controllers. */
27
28 /* Read and write registers */
29 #define REG_CMD_BASE0 0x1F0 /* command base register of controller 0 */
30 #define REG_CMD_BASE1 0x170 /* command base register of controller 1 */
31 #define REG_CTL_BASE0 0x3F6 /* control base register of controller 0 */
32 #define REG_CTL_BASE1 0x376 /* control base register of controller 1 */
33
34 #define PCI_CTL_OFF 2 /* Offset of control registers from BAR2 */
35 #define PCI_DMA_2ND_OFF 8 /* Offset of DMA registers from BAR4 for
36 * secondary channel
37 */
38
39 #define REG_DATA 0 /* data register (offset from the base reg.) */
40 #define REG_PRECOMP 1 /* start of write precompensation */
41 #define REG_COUNT 2 /* sectors to transfer */
42 #define REG_SECTOR 3 /* sector number */
43 #define REG_CYL_LO 4 /* low byte of cylinder number */
44 #define REG_CYL_HI 5 /* high byte of cylinder number */
45 #define REG_LDH 6 /* lba, drive and head */
46 #define LDH_DEFAULT 0xA0 /* ECC enable, 512 bytes per sector */
47 #define LDH_LBA 0x40 /* Use LBA addressing */
48 #define LDH_DEV 0x10 /* Drive 1 iff set */
49 #define ldh_init(drive) (LDH_DEFAULT | ((drive) << 4))
50
51 /* Read only registers */
52 #define REG_STATUS 7 /* status */
53 #define STATUS_BSY 0x80 /* controller busy */
54 #define STATUS_RDY 0x40 /* drive ready */
55 #define STATUS_WF 0x20 /* write fault */
56 #define STATUS_SC 0x10 /* seek complete (obsolete) */
57 #define STATUS_DRQ 0x08 /* data transfer request */
58 #define STATUS_CRD 0x04 /* corrected data */
59 #define STATUS_IDX 0x02 /* index pulse */
60 #define STATUS_ERR 0x01 /* error */
61 #define STATUS_ADMBSY 0x100 /* administratively busy (software) */
62 #define REG_ERROR 1 /* error code */
63 #define ERROR_BB 0x80 /* bad block */
64 #define ERROR_ECC 0x40 /* bad ecc bytes */
65 #define ERROR_ID 0x10 /* id not found */
66 #define ERROR_AC 0x04 /* aborted command */
67 #define ERROR_TK 0x02 /* track zero error */
68 #define ERROR_DM 0x01 /* no data address mark */
69
70 /* Write only registers */
71 #define REG_COMMAND 7 /* command */
72 #define CMD_IDLE 0x00 /* for w_command: drive idle */
73 #define CMD_RECALIBRATE 0x10 /* recalibrate drive */
74 #define CMD_READ 0x20 /* read data */
75 #define CMD_READ_EXT 0x24 /* read data (LBA48 addressed) */
76 #define CMD_READ_DMA_EXT 0x25 /* read data using DMA (w/ LBA48) */
77 #define CMD_WRITE 0x30 /* write data */
78 #define CMD_WRITE_EXT 0x34 /* write data (LBA48 addressed) */
79 #define CMD_WRITE_DMA_EXT 0x35 /* write data using DMA (w/ LBA48) */
80 #define CMD_READVERIFY 0x40 /* read verify */
81 #define CMD_FORMAT 0x50 /* format track */
82 #define CMD_SEEK 0x70 /* seek cylinder */
83 #define CMD_DIAG 0x90 /* execute device diagnostics */
84 #define CMD_SPECIFY 0x91 /* specify parameters */
85 #define CMD_READ_DMA 0xC8 /* read data using DMA */
86 #define CMD_WRITE_DMA 0xCA /* write data using DMA */
87 #define ATA_IDENTIFY 0xEC /* identify drive */
88 /* #define REG_CTL 0x206 */ /* control register */
89 #define REG_CTL 0 /* control register */
90 #define CTL_NORETRY 0x80 /* disable access retry */
91 #define CTL_NOECC 0x40 /* disable ecc retry */
92 #define CTL_EIGHTHEADS 0x08 /* more than eight heads */
93 #define CTL_RESET 0x04 /* reset controller */
94 #define CTL_INTDISABLE 0x02 /* disable interrupts */
95 #define REG_CTL_ALTSTAT 0 /* alternate status register */
96
97 /* Identify words */
98 #define ID_GENERAL 0x00 /* General configuration information */
99 #define ID_GEN_NOT_ATA 0x8000 /* Not an ATA device */
100 #define ID_CAPABILITIES 0x31 /* Capabilities (49)*/
101 #define ID_CAP_LBA 0x0200 /* LBA supported */
102 #define ID_CAP_DMA 0x0100 /* DMA supported */
103 #define ID_FIELD_VALIDITY 0x35 /* Field Validity (53) */
104 #define ID_FV_88 0x04 /* Word 88 is valid (UDMA) */
105 #define ID_MULTIWORD_DMA 0x3f /* Multiword DMA (63) */
106 #define ID_MWDMA_2_SEL 0x0400 /* Mode 2 is selected */
107 #define ID_MWDMA_1_SEL 0x0200 /* Mode 1 is selected */
108 #define ID_MWDMA_0_SEL 0x0100 /* Mode 0 is selected */
109 #define ID_MWDMA_2_SUP 0x0004 /* Mode 2 is supported */
110 #define ID_MWDMA_1_SUP 0x0002 /* Mode 1 is supported */
111 #define ID_MWDMA_0_SUP 0x0001 /* Mode 0 is supported */
112 #define ID_CSS 0x53 /* Command Sets Supported (83) */
113 #define ID_CSS_LBA48 0x0400
114 #define ID_ULTRA_DMA 0x58 /* Ultra DMA (88) */
115 #define ID_UDMA_5_SEL 0x2000 /* Mode 5 is selected */
116 #define ID_UDMA_4_SEL 0x1000 /* Mode 4 is selected */
117 #define ID_UDMA_3_SEL 0x0800 /* Mode 3 is selected */
118 #define ID_UDMA_2_SEL 0x0400 /* Mode 2 is selected */
119 #define ID_UDMA_1_SEL 0x0200 /* Mode 1 is selected */
120 #define ID_UDMA_0_SEL 0x0100 /* Mode 0 is selected */
121 #define ID_UDMA_5_SUP 0x0020 /* Mode 5 is supported */
122 #define ID_UDMA_4_SUP 0x0010 /* Mode 4 is supported */
123 #define ID_UDMA_3_SUP 0x0008 /* Mode 3 is supported */
124 #define ID_UDMA_2_SUP 0x0004 /* Mode 2 is supported */
125 #define ID_UDMA_1_SUP 0x0002 /* Mode 1 is supported */
126 #define ID_UDMA_0_SUP 0x0001 /* Mode 0 is supported */
127
128 /* DMA registers */
129 #define DMA_COMMAND 0 /* Command register */
130 #define DMA_CMD_WRITE 0x08 /* PCI bus master writes */
131 #define DMA_CMD_START 0x01 /* Start Bus Master */
132 #define DMA_STATUS 2 /* Status register */
133 #define DMA_ST_D1_DMACAP 0x40 /* Drive 1 is DMA capable */
134 #define DMA_ST_D0_DMACAP 0x20 /* Drive 0 is DMA capable */
135 #define DMA_ST_INT 0x04 /* Interrupt */
136 #define DMA_ST_ERROR 0x02 /* Error */
137 #define DMA_ST_BM_ACTIVE 0x01 /* Bus Master IDE Active */
138 #define DMA_PRDTP 4 /* PRD Table Pointer */
139
140 /* Check for the presence of LBA48 only on drives that are 'big'. */
141 #define LBA48_CHECK_SIZE 0x0f000000
142 #define LBA_MAX_SIZE 0x0fffffff /* Highest sector size for
143 * regular LBA.
144 */
145
146 #if ENABLE_ATAPI
147 #define ERROR_SENSE 0xF0 /* sense key mask */
148 #define SENSE_NONE 0x00 /* no sense key */
149 #define SENSE_RECERR 0x10 /* recovered error */
150 #define SENSE_NOTRDY 0x20 /* not ready */
151 #define SENSE_MEDERR 0x30 /* medium error */
152 #define SENSE_HRDERR 0x40 /* hardware error */
153 #define SENSE_ILRQST 0x50 /* illegal request */
154 #define SENSE_UATTN 0x60 /* unit attention */
155 #define SENSE_DPROT 0x70 /* data protect */
156 #define SENSE_ABRT 0xb0 /* aborted command */
157 #define SENSE_MISCOM 0xe0 /* miscompare */
158 #define ERROR_MCR 0x08 /* media change requested */
159 #define ERROR_ABRT 0x04 /* aborted command */
160 #define ERROR_EOM 0x02 /* end of media detected */
161 #define ERROR_ILI 0x01 /* illegal length indication */
162 #define REG_FEAT 1 /* features */
163 #define FEAT_OVERLAP 0x02 /* overlap */
164 #define FEAT_DMA 0x01 /* dma */
165 #define REG_IRR 2 /* interrupt reason register */
166 #define IRR_REL 0x04 /* release */
167 #define IRR_IO 0x02 /* direction for xfer */
168 #define IRR_COD 0x01 /* command or data */
169 #define REG_SAMTAG 3
170 #define REG_CNT_LO 4 /* low byte of cylinder number */
171 #define REG_CNT_HI 5 /* high byte of cylinder number */
172 #define REG_DRIVE 6 /* drive select */
173 #endif
174
175 #define REG_STATUS 7 /* status */
176 #define STATUS_BSY 0x80 /* controller busy */
177 #define STATUS_DRDY 0x40 /* drive ready */
178 #define STATUS_DMADF 0x20 /* dma ready/drive fault */
179 #define STATUS_SRVCDSC 0x10 /* service or dsc */
180 #define STATUS_DRQ 0x08 /* data transfer request */
181 #define STATUS_CORR 0x04 /* correctable error occurred */
182 #define STATUS_CHECK 0x01 /* check error */
183
184 #ifdef ENABLE_ATAPI
185 #define ATAPI_PACKETCMD 0xA0 /* packet command */
186 #define ATAPI_IDENTIFY 0xA1 /* identify drive */
187 #define SCSI_READ10 0x28 /* read from disk */
188 #define SCSI_SENSE 0x03 /* sense request */
189
190 #define CD_SECTOR_SIZE 2048 /* sector size of a CD-ROM */
191 #endif /* ATAPI */
192
193 /* Interrupt request lines. */
194 #define NO_IRQ 0 /* no IRQ set yet */
195
196 #define ATAPI_PACKETSIZE 12
197 #define SENSE_PACKETSIZE 18
198
199 /* Common command block */
200 struct command {
201 u8_t precomp; /* REG_PRECOMP, etc. */
202 u8_t count;
203 u8_t sector;
204 u8_t cyl_lo;
205 u8_t cyl_hi;
206 u8_t ldh;
207 u8_t command;
208
209 /* The following at for LBA48 */
210 u8_t count_prev;
211 u8_t sector_prev;
212 u8_t cyl_lo_prev;
213 u8_t cyl_hi_prev;
214 };
215
216 /* Error codes */
217 #define ERR (-1) /* general error */
218 #define ERR_BAD_SECTOR (-2) /* block marked bad detected */
219
220 /* Some controllers don't interrupt, the clock will wake us up. */
221 #define WAKEUP_SECS 32 /* drive may be out for 31 seconds max */
222 #define WAKEUP_TICKS (WAKEUP_SECS*HZ)
223
224 /* Miscellaneous. */
225 #define MAX_DRIVES 8
226 #define COMPAT_DRIVES 4
227 #if _WORD_SIZE > 2
228 #define MAX_SECS 256 /* controller can transfer this many sectors */
229 #else
230 #define MAX_SECS 127 /* but not to a 16 bit process */
231 #endif
232 #define MAX_ERRORS 4 /* how often to try rd/wt before quitting */
233 #define NR_MINORS (MAX_DRIVES * DEV_PER_DRIVE)
234 #define SUB_PER_DRIVE (NR_PARTITIONS * NR_PARTITIONS)
235 #define NR_SUBDEVS (MAX_DRIVES * SUB_PER_DRIVE)
236 #define DELAY_USECS 1000 /* controller timeout in microseconds */
237 #define DELAY_TICKS 1 /* controller timeout in ticks */
238 #define DEF_TIMEOUT_TICKS 300 /* controller timeout in ticks */
239 #define RECOVERY_USECS 500000 /* controller recovery time in microseconds */
240 #define RECOVERY_TICKS 30 /* controller recovery time in ticks */
241 #define INITIALIZED 0x01 /* drive is initialized */
242 #define DEAF 0x02 /* controller must be reset */
243 #define SMART 0x04 /* drive supports ATA commands */
244 #if ENABLE_ATAPI
245 #define ATAPI 0x08 /* it is an ATAPI device */
246 #else
247 #define ATAPI 0 /* don't bother with ATAPI; optimise out */
248 #endif
249 #define IDENTIFIED 0x10 /* w_identify done successfully */
250 #define IGNORING 0x20 /* w_identify failed once */
251
252 /* Timeouts and max retries. */
253 int timeout_ticks = DEF_TIMEOUT_TICKS, max_errors = MAX_ERRORS;
254 long w_standard_timeouts = 0, w_pci_debug = 0, w_instance = 0,
255 disable_dma = 0, atapi_debug = 0, w_identify_wakeup_ticks = WAKEUP_TICKS,
256 wakeup_ticks = WAKEUP_TICKS;
257
258 int w_testing = 0, w_silent = 0;
259
260 int w_next_drive = 0;
261
262 /* Variables. */
263
264 /* The struct wini is indexed by controller first, then drive (0-3).
265 * Controller 0 is always the 'compatability' ide controller, at
266 * the fixed locations, whether present or not.
267 */
268 PRIVATE struct wini { /* main drive struct, one entry per drive */
269 unsigned state; /* drive state: deaf, initialized, dead */
270 unsigned short w_status; /* device status register */
271 unsigned base_cmd; /* command base register */
272 unsigned base_ctl; /* control base register */
273 unsigned base_dma; /* dma base register */
274 unsigned irq; /* interrupt request line */
275 unsigned irq_mask; /* 1 << irq */
276 unsigned irq_need_ack; /* irq needs to be acknowledged */
277 int irq_hook_id; /* id of irq hook at the kernel */
278 int lba48; /* supports lba48 */
279 int dma; /* supports dma */
280 unsigned lcylinders; /* logical number of cylinders (BIOS) */
281 unsigned lheads; /* logical number of heads */
282 unsigned lsectors; /* logical number of sectors per track */
283 unsigned pcylinders; /* physical number of cylinders (translated) */
284 unsigned pheads; /* physical number of heads */
285 unsigned psectors; /* physical number of sectors per track */
286 unsigned ldhpref; /* top four bytes of the LDH (head) register */
287 unsigned precomp; /* write precompensation cylinder / 4 */
288 unsigned max_count; /* max request for this drive */
289 unsigned open_ct; /* in-use count */
290 struct device part[DEV_PER_DRIVE]; /* disks and partitions */
291 struct device subpart[SUB_PER_DRIVE]; /* subpartitions */
292 } wini[MAX_DRIVES], *w_wn;
293
294 PRIVATE int w_device = -1;
295 PRIVATE int w_controller = -1;
296 PRIVATE int w_major = -1;
297 PRIVATE char w_id_string[40];
298
299 PRIVATE int win_tasknr; /* my task number */
300 PRIVATE int w_command; /* current command in execution */
301 PRIVATE u8_t w_byteval; /* used for SYS_IRQCTL */
302 PRIVATE int w_drive; /* selected drive */
303 PRIVATE int w_controller; /* selected controller */
304 PRIVATE struct device *w_dv; /* device's base and size */
305
306 /* Unfortunately, DMA_SECTORS and DMA_BUF_SIZE are already defined libdriver
307 * for 'tmp_buf'.
308 */
309 #define ATA_DMA_SECTORS 64
310 #define ATA_DMA_BUF_SIZE (ATA_DMA_SECTORS*SECTOR_SIZE)
311
312 PRIVATE char dma_buf[ATA_DMA_BUF_SIZE];
313 PRIVATE phys_bytes dma_buf_phys;
314
315 #define N_PRDTE 1024 /* Should be enough for large requests */
316
317 PRIVATE struct prdte
318 {
319 u32_t prdte_base;
320 u16_t prdte_count;
321 u8_t prdte_reserved;
322 u8_t prdte_flags;
323 } prdt[N_PRDTE];
324 PRIVATE phys_bytes prdt_phys;
325
326 #define PRDTE_FL_EOT 0x80 /* End of table */
327
328 /* Some IDE devices announce themselves as RAID controllers */
329 PRIVATE struct
330 {
331 u16_t vendor;
332 u16_t device;
333 } raid_table[]=
334 {
335 { 0x1106, 0x3149 }, /* VIA VT6420 */
336 { 0, 0 } /* end of list */
337 };
338
339 FORWARD _PROTOTYPE( void init_params, (void) );
340 FORWARD _PROTOTYPE( void init_drive, (struct wini *w, int base_cmd,
341 int base_ctl, int base_dma, int irq, int ack, int hook,
342 int drive) );
343 FORWARD _PROTOTYPE( void init_params_pci, (int) );
344 FORWARD _PROTOTYPE( int w_do_open, (struct driver *dp, message *m_ptr) );
345 FORWARD _PROTOTYPE( struct device *w_prepare, (int dev) );
346 FORWARD _PROTOTYPE( int w_identify, (void) );
347 FORWARD _PROTOTYPE( char *w_name, (void) );
348 FORWARD _PROTOTYPE( int w_specify, (void) );
349 FORWARD _PROTOTYPE( int w_io_test, (void) );
350 FORWARD _PROTOTYPE( int w_transfer, (int proc_nr, int opcode, u64_t position,
351 iovec_t *iov, unsigned nr_req, int safe));
352 FORWARD _PROTOTYPE( int com_out, (struct command *cmd) );
353 FORWARD _PROTOTYPE( int com_out_ext, (struct command *cmd) );
354 FORWARD _PROTOTYPE( void setup_dma, (unsigned *sizep, int proc_nr,
355 iovec_t *iov, int do_write, int *do_copyoutp, int safe) );
356 FORWARD _PROTOTYPE( void w_need_reset, (void) );
357 FORWARD _PROTOTYPE( void ack_irqs, (unsigned int) );
358 FORWARD _PROTOTYPE( int w_do_close, (struct driver *dp, message *m_ptr) );
359 FORWARD _PROTOTYPE( int w_other, (struct driver *dp, message *m_ptr, int));
360 FORWARD _PROTOTYPE( int w_hw_int, (struct driver *dp, message *m_ptr) );
361 FORWARD _PROTOTYPE( int com_simple, (struct command *cmd) );
362 FORWARD _PROTOTYPE( void w_timeout, (void) );
363 FORWARD _PROTOTYPE( int w_reset, (void) );
364 FORWARD _PROTOTYPE( void w_intr_wait, (void) );
365 FORWARD _PROTOTYPE( int at_intr_wait, (void) );
366 FORWARD _PROTOTYPE( int w_waitfor, (int mask, int value) );
367 FORWARD _PROTOTYPE( int w_waitfor_dma, (int mask, int value) );
368 FORWARD _PROTOTYPE( void w_geometry, (struct partition *entry) );
369 #if ENABLE_ATAPI
370 FORWARD _PROTOTYPE( int atapi_sendpacket, (u8_t *packet, unsigned cnt) );
371 FORWARD _PROTOTYPE( int atapi_intr_wait, (void) );
372 FORWARD _PROTOTYPE( int atapi_open, (void) );
373 FORWARD _PROTOTYPE( void atapi_close, (void) );
374 FORWARD _PROTOTYPE( int atapi_transfer, (int proc_nr, int opcode,
375 u64_t position, iovec_t *iov, unsigned nr_req, int safe));
376 #endif
377
378 #define panic(f,m,n) at_panic(__LINE__, (f), (m), (n))
379 FORWARD _PROTOTYPE( void at_panic, (int line, char *h, char *msg, int n));
380
381 /* Entry points to this driver. */
382 PRIVATE struct driver w_dtab = {
383 w_name, /* current device's name */
384 w_do_open, /* open or mount request, initialize device */
385 w_do_close, /* release device */
386 do_diocntl, /* get or set a partition's geometry */
387 w_prepare, /* prepare for I/O on a given minor device */
388 w_transfer, /* do the I/O */
389 nop_cleanup, /* nothing to clean up */
390 w_geometry, /* tell the geometry of the disk */
391 nop_signal, /* no cleanup needed on shutdown */
392 nop_alarm, /* ignore leftover alarms */
393 nop_cancel, /* ignore CANCELs */
394 nop_select, /* ignore selects */
395 w_other, /* catch-all for unrecognized commands and ioctls */
396 w_hw_int /* leftover hardware interrupts */
397 };
398
399 /*===========================================================================*
400 * at_winchester_task *
401 *===========================================================================*/
402 PUBLIC int main(int argc, char *argv[])
403 {
404 /* Install signal handlers. Ask PM to transform signal into message. */
405 struct sigaction sa;
406
407 sa.sa_handler = SIG_MESS;
408 sigemptyset(&sa.sa_mask);
409 sa.sa_flags = 0;
410 if (sigaction(SIGTERM,&sa,NULL)<0) panic("AT","sigaction failed", errno);
411
412 /* Set special disk parameters then call the generic main loop. */
413 env_setargs(argc, argv);
414 init_params();
415 signal(SIGTERM, SIG_IGN);
416 driver_task(&w_dtab);
417 return(OK);
418 }
419
420 /*===========================================================================*
421 * init_params *
422 *===========================================================================*/
423 PRIVATE void init_params()
424 {
425 /* This routine is called at startup to initialize the drive parameters. */
426
427 u16_t parv[2];
428 unsigned int vector, size;
429 int drive, nr_drives;
430 struct wini *wn;
431 u8_t params[16];
432 int s;
433 long wakeup_secs = WAKEUP_SECS;
434
435 /* Boot variables. */
436 env_parse("ata_std_timeout", "d", 0, &w_standard_timeouts, 0, 1);
437 env_parse("ata_pci_debug", "d", 0, &w_pci_debug, 0, 1);
438 env_parse("ata_instance", "d", 0, &w_instance, 0, 8);
439 env_parse("ata_no_dma", "d", 0, &disable_dma, 0, 1);
440 env_parse("ata_id_timeout", "d", WAKEUP_SECS, &wakeup_secs, 1, 60);
441 env_parse("atapi_debug", "d", 0, &atapi_debug, 0, 1);
442
443 w_identify_wakeup_ticks = wakeup_secs * HZ;
444
445 if(w_identify_wakeup_ticks <= 0) {
446 printf("changing wakeup from %d to %d ticks.\n",
447 w_identify_wakeup_ticks, WAKEUP_TICKS);
448 w_identify_wakeup_ticks = WAKEUP_TICKS;
449 }
450
451 if (disable_dma)
452 printf("DMA for ATA devices is disabled.\n");
453
454 s= sys_umap(SELF, D, (vir_bytes)dma_buf, sizeof(dma_buf), &dma_buf_phys);
455 if (s != 0)
456 panic("at_wini", "can't map dma buffer", s);
457
458 s= sys_umap(SELF, D, (vir_bytes)prdt, sizeof(prdt), &prdt_phys);
459 if (s != 0)
460 panic("at_wini", "can't map prd table", s);
461
462 if (w_instance == 0) {
463 /* Get the number of drives from the BIOS data area */
464 s=sys_readbios(NR_HD_DRIVES_ADDR, params, NR_HD_DRIVES_SIZE);
465 if (s != OK)
466 panic(w_name(), "Couldn't read BIOS", s);
467 if ((nr_drives = params[0]) > 2) nr_drives = 2;
468
469 for (drive = 0, wn = wini; drive < COMPAT_DRIVES; drive++, wn++) {
470 if (drive < nr_drives) {
471 /* Copy the BIOS parameter vector */
472 vector = (drive == 0) ? BIOS_HD0_PARAMS_ADDR :
473 BIOS_HD1_PARAMS_ADDR;
474 size = (drive == 0) ? BIOS_HD0_PARAMS_SIZE :
475 BIOS_HD1_PARAMS_SIZE;
476 s=sys_readbios(vector, parv, size);
477 if (s != OK)
478 panic(w_name(), "Couldn't read BIOS", s);
479
480 /* Calculate the address of the parameters and copy them */
481 s=sys_readbios(hclick_to_physb(parv[1]) + parv[0],
482 params, 16L);
483 if (s != OK)
484 panic(w_name(),"Couldn't copy parameters", s);
485
486 /* Copy the parameters to the structures of the drive */
487 wn->lcylinders = bp_cylinders(params);
488 wn->lheads = bp_heads(params);
489 wn->lsectors = bp_sectors(params);
490 wn->precomp = bp_precomp(params) >> 2;
491 }
492
493 /* Fill in non-BIOS parameters. */
494 init_drive(wn,
495 drive < 2 ? REG_CMD_BASE0 : REG_CMD_BASE1,
496 drive < 2 ? REG_CTL_BASE0 : REG_CTL_BASE1,
497 0 /* no DMA */, NO_IRQ, 0, 0, drive);
498 w_next_drive++;
499 }
500 }
501
502 /* Look for controllers on the pci bus. Skip none the first instance,
503 * skip one and then 2 for every instance, for every next instance.
504 */
505 if (w_instance == 0)
506 init_params_pci(0);
507 else
508 init_params_pci(w_instance*2-1);
509
510 }
511
512 #define ATA_IF_NOTCOMPAT1 (1L << 0)
513 #define ATA_IF_NOTCOMPAT2 (1L << 2)
514
515 /*===========================================================================*
516 * init_drive *
517 *===========================================================================*/
518 PRIVATE void init_drive(struct wini *w, int base_cmd, int base_ctl,
519 int base_dma, int irq, int ack, int hook, int drive)
520 {
521 w->state = 0;
522 w->w_status = 0;
523 w->base_cmd = base_cmd;
524 w->base_ctl = base_ctl;
525 w->base_dma = base_dma;
526 if(w_pci_debug)
527 printf("at_wini%d: drive %d: base_cmd 0x%x, base_ctl 0x%x, base_dma 0x%x\n",
528 w_instance, w-wini, w->base_cmd, w->base_ctl, w->base_dma);
529 w->irq = irq;
530 w->irq_mask = 1 << irq;
531 w->irq_need_ack = ack;
532 w->irq_hook_id = hook;
533 w->ldhpref = ldh_init(drive);
534 w->max_count = MAX_SECS << SECTOR_SHIFT;
535 w->lba48 = 0;
536 w->dma = 0;
537 }
538
539 /*===========================================================================*
540 * init_params_pci *
541 *===========================================================================*/
542 PRIVATE void init_params_pci(int skip)
543 {
544 int i, r, devind, drive, pci_compat = 0;
545 int irq, irq_hook, raid;
546 u8_t bcr, scr, interface;
547 u16_t vid, did;
548 u32_t base_dma, t3;
549
550 pci_init();
551 for(drive = w_next_drive; drive < MAX_DRIVES; drive++)
552 wini[drive].state = IGNORING;
553 for(r = pci_first_dev(&devind, &vid, &did); r != 0;
554 r = pci_next_dev(&devind, &vid, &did)) {
555
556 raid= 0;
557
558 /* Except class 01h (mass storage), subclass be 01h (ATA).
559 * Also check listed RAID controllers.
560 */
561 bcr= pci_attr_r8(devind, PCI_BCR);
562 scr= pci_attr_r8(devind, PCI_SCR);
563 interface= pci_attr_r8(devind, PCI_PIFR);
564 t3= ((bcr << 16) | (scr << 8) | interface);
565 if (bcr == PCI_BCR_MASS_STORAGE && scr == PCI_MS_IDE)
566 ; /* Okay */
567 else if (t3 == PCI_T3_RAID)
568 {
569 for (i= 0; raid_table[i].vendor != 0; i++)
570 {
571 if (raid_table[i].vendor == vid &&
572 raid_table[i].device == did)
573 {
574 break;
575 }
576 }
577 if (raid_table[i].vendor == 0)
578 {
579 printf(
580 "atapci skipping unsupported RAID controller 0x%04x / 0x%04x\n",
581 vid, did);
582 continue;
583 }
584 printf("found supported RAID controller\n");
585 raid= 1;
586 }
587 else
588 continue; /* Unsupported device class */
589
590 /* Found a controller.
591 * Programming interface register tells us more.
592 */
593 irq = pci_attr_r8(devind, PCI_ILR);
594
595 /* Any non-compat drives? */
596 if (raid || (interface & (ATA_IF_NOTCOMPAT1 | ATA_IF_NOTCOMPAT2))) {
597 int s;
598
599 if (w_next_drive >= MAX_DRIVES)
600 {
601 /* We can't accept more drives, but have to search for
602 * controllers operating in compatibility mode.
603 */
604 continue;
605 }
606
607 irq_hook = irq;
608 if (skip > 0) {
609 if (w_pci_debug)
610 {
611 printf(
612 "atapci skipping controller (remain %d)\n",
613 skip);
614 }
615 skip--;
616 continue;
617 }
618 if(pci_reserve_ok(devind) != OK) {
619 printf("at_wini%d: pci_reserve %d failed - "
620 "ignoring controller!\n",
621 w_instance, devind);
622 continue;
623 }
624 if ((s=sys_irqsetpolicy(irq, 0, &irq_hook)) != OK) {
625 printf("atapci: couldn't set IRQ policy %d\n", irq);
626 continue;
627 }
628 if ((s=sys_irqenable(&irq_hook)) != OK) {
629 printf("atapci: couldn't enable IRQ line %d\n", irq);
630 continue;
631 }
632 } else if(w_pci_debug) printf("at_wini%d: dev %d: only compat drives\n", w_instance, devind);
633
634 base_dma = pci_attr_r32(devind, PCI_BAR_5) & 0xfffffffc;
635
636 /* Primary channel not in compatability mode? */
637 if (raid || (interface & ATA_IF_NOTCOMPAT1)) {
638 u32_t base_cmd, base_ctl;
639
640 base_cmd = pci_attr_r32(devind, PCI_BAR) & 0xfffffffc;
641 base_ctl = pci_attr_r32(devind, PCI_BAR_2) & 0xfffffffc;
642 if (base_cmd != REG_CMD_BASE0 && base_cmd != REG_CMD_BASE1) {
643 init_drive(&wini[w_next_drive],
644 base_cmd, base_ctl+PCI_CTL_OFF,
645 base_dma, irq, 1, irq_hook, 0);
646 init_drive(&wini[w_next_drive+1],
647 base_cmd, base_ctl+PCI_CTL_OFF,
648 base_dma, irq, 1, irq_hook, 1);
649 if (w_pci_debug)
650 printf("at_wini%d: atapci %d: 0x%x 0x%x irq %d\n", w_instance, devind, base_cmd, base_ctl, irq);
651 w_next_drive += 2;
652 } else printf("at_wini%d: atapci: ignored drives on primary channel, base %x\n", w_instance, base_cmd);
653 }
654 else
655 {
656 /* Update base_dma for compatibility device */
657 for (i= 0; i<MAX_DRIVES; i++)
658 {
659 if (wini[i].base_cmd == REG_CMD_BASE0) {
660 wini[i].base_dma= base_dma;
661 if(w_pci_debug)
662 printf("at_wini%d: drive %d: base_dma 0x%x\n",
663 w_instance, i, wini[i].base_dma);
664 pci_compat = 1;
665 }
666 }
667 }
668
669 /* Secondary channel not in compatability mode? */
670 if (raid || (interface & ATA_IF_NOTCOMPAT2)) {
671 u32_t base_cmd, base_ctl;
672
673 base_cmd = pci_attr_r32(devind, PCI_BAR_3) & 0xfffffffc;
674 base_ctl = pci_attr_r32(devind, PCI_BAR_4) & 0xfffffffc;
675 if (base_dma != 0)
676 base_dma += PCI_DMA_2ND_OFF;
677 if (base_cmd != REG_CMD_BASE0 && base_cmd != REG_CMD_BASE1) {
678 init_drive(&wini[w_next_drive],
679 base_cmd, base_ctl+PCI_CTL_OFF, base_dma,
680 irq, 1, irq_hook, 2);
681 init_drive(&wini[w_next_drive+1],
682 base_cmd, base_ctl+PCI_CTL_OFF, base_dma,
683 irq, 1, irq_hook, 3);
684 if (w_pci_debug)
685 printf("at_wini%d: atapci %d: 0x%x 0x%x irq %d\n",
686 w_instance, devind, base_cmd, base_ctl, irq);
687 w_next_drive += 2;
688 } else printf("at_wini%d: atapci: ignored drives on "
689 "secondary channel, base %x\n", w_instance, base_cmd);
690 }
691 else
692 {
693 /* Update base_dma for compatibility device */
694 for (i= 0; i<MAX_DRIVES; i++)
695 {
696 if (wini[i].base_cmd == REG_CMD_BASE1 && base_dma != 0) {
697 wini[i].base_dma= base_dma+PCI_DMA_2ND_OFF;
698 if (w_pci_debug)
699 printf("at_wini%d: drive %d: base_dma 0x%x\n",
700 w_instance, i, wini[i].base_dma);
701 pci_compat = 1;
702 }
703 }
704 }
705
706 if(pci_compat) {
707 if(pci_reserve_ok(devind) != OK) {
708 printf("at_wini%d (compat): pci_reserve %d failed!\n",
709 w_instance, devind);
710 }
711 }
712 }
713 }
714
715 /*===========================================================================*
716 * w_do_open *
717 *===========================================================================*/
718 PRIVATE int w_do_open(dp, m_ptr)
719 struct driver *dp;
720 message *m_ptr;
721 {
722 /* Device open: Initialize the controller and read the partition table. */
723
724 struct wini *wn;
725
726 if (w_prepare(m_ptr->DEVICE) == NIL_DEV) return(ENXIO);
727
728 wn = w_wn;
729
730 /* If we've probed it before and it failed, don't probe it again. */
731 if (wn->state & IGNORING) return ENXIO;
732
733 /* If we haven't identified it yet, or it's gone deaf,
734 * (re-)identify it.
735 */
736 if (!(wn->state & IDENTIFIED) || (wn->state & DEAF)) {
737 /* Try to identify the device. */
738 if (w_identify() != OK) {
739 #if VERBOSE
740 printf("%s: probe failed\n", w_name());
741 #endif
742 if (wn->state & DEAF) w_reset();
743 wn->state = IGNORING;
744 return(ENXIO);
745 }
746 /* Do a test transaction unless it's a CD drive (then
747 * we can believe the controller, and a test may fail
748 * due to no CD being in the drive). If it fails, ignore
749 * the device forever.
750 */
751 if (!(wn->state & ATAPI) && w_io_test() != OK) {
752 wn->state |= IGNORING;
753 return(ENXIO);
754 }
755
756 #if VERBOSE
757 printf("%s: AT driver detected ", w_name());
758 if (wn->state & (SMART|ATAPI)) {
759 printf("%.40s\n", w_id_string);
760 } else {
761 printf("%ux%ux%u\n", wn->pcylinders, wn->pheads, wn->psectors);
762 }
763 #endif
764 }
765
766 #if ENABLE_ATAPI
767 if ((wn->state & ATAPI) && (m_ptr->COUNT & W_BIT))
768 return(EACCES);
769 #endif
770
771 /* Partition the drive if it's being opened for the first time,
772 * or being opened after being closed.
773 */
774 if (wn->open_ct == 0) {
775 #if ENABLE_ATAPI
776 if (wn->state & ATAPI) {
777 int r;
778 if ((r = atapi_open()) != OK) return(r);
779 }
780 #endif
781
782 /* Partition the disk. */
783 partition(&w_dtab, w_drive * DEV_PER_DRIVE, P_PRIMARY, wn->state & ATAPI);
784 }
785 wn->open_ct++;
786 return(OK);
787 }
788
789 /*===========================================================================*
790 * w_prepare *
791 *===========================================================================*/
792 PRIVATE struct device *w_prepare(int device)
793 {
794 /* Prepare for I/O on a device. */
795 struct wini *prev_wn;
796 prev_wn = w_wn;
797 w_device = device;
798
799 if (device < NR_MINORS) { /* d0, d0p[0-3], d1, ... */
800 w_drive = device / DEV_PER_DRIVE; /* save drive number */
801 w_wn = &wini[w_drive];
802 w_dv = &w_wn->part[device % DEV_PER_DRIVE];
803 } else
804 if ((unsigned) (device -= MINOR_d0p0s0) < NR_SUBDEVS) {/*d[0-7]p[0-3]s[0-3]*/
805 w_drive = device / SUB_PER_DRIVE;
806 w_wn = &wini[w_drive];
807 w_dv = &w_wn->subpart[device % SUB_PER_DRIVE];
808 } else {
809 w_device = -1;
810 return(NIL_DEV);
811 }
812 return(w_dv);
813 }
814
815 /*===========================================================================*
816 * w_identify *
817 *===========================================================================*/
818 PRIVATE int w_identify()
819 {
820 /* Find out if a device exists, if it is an old AT disk, or a newer ATA
821 * drive, a removable media device, etc.
822 */
823
824 struct wini *wn = w_wn;
825 struct command cmd;
826 int i, s;
827 int id_dma, ultra_dma;
828 u32_t dma_base;
829 u16_t w;
830 unsigned long dma_status;
831 unsigned long size;
832 int prev_wakeup;
833 int r;
834 #define id_byte(n) (&tmp_buf[2 * (n)])
835 #define id_word(n) (((u16_t) id_byte(n)[0] << 0) \
836 |((u16_t) id_byte(n)[1] << 8))
837 #define id_longword(n) (((u32_t) id_byte(n)[0] << 0) \
838 |((u32_t) id_byte(n)[1] << 8) \
839 |((u32_t) id_byte(n)[2] << 16) \
840 |((u32_t) id_byte(n)[3] << 24))
841
842 /* Try to identify the device. */
843 cmd.ldh = wn->ldhpref;
844 cmd.command = ATA_IDENTIFY;
845
846 /* In testing mode, a drive will get ignored at the first timeout. */
847 w_testing = 1;
848
849 /* Execute *_IDENTIFY with configured *_IDENTIFY timeout. */
850 prev_wakeup = wakeup_ticks;
851 wakeup_ticks = w_identify_wakeup_ticks;
852 r = com_simple(&cmd);
853
854 if (r == OK && w_waitfor(STATUS_DRQ, STATUS_DRQ) &&
855 !(wn->w_status & (STATUS_ERR|STATUS_WF))) {
856
857 /* Device information. */
858 if ((s=sys_insw(wn->base_cmd + REG_DATA, SELF, tmp_buf, SECTOR_SIZE)) != OK)
859 panic(w_name(),"Call to sys_insw() failed", s);
860
861 #if 0
862 if (id_word(0) & ID_GEN_NOT_ATA)
863 {
864 printf("%s: not an ATA device?\n", w_name());
865 wakeup_ticks = prev_wakeup;
866 w_testing = 0;
867 return ERR;
868 }
869 #endif
870
871 /* This is an ATA device. */
872 wn->state |= SMART;
873
874 /* Why are the strings byte swapped??? */
875 for (i = 0; i < 40; i++) w_id_string[i] = id_byte(27)[i^1];
876
877 /* Preferred CHS translation mode. */
878 wn->pcylinders = id_word(1);
879 wn->pheads = id_word(3);
880 wn->psectors = id_word(6);
881 size = (u32_t) wn->pcylinders * wn->pheads * wn->psectors;
882
883 w= id_word(ID_CAPABILITIES);
884 if ((w & ID_CAP_LBA) && size > 512L*1024*2) {
885 /* Drive is LBA capable and is big enough to trust it to
886 * not make a mess of it.
887 */
888 wn->ldhpref |= LDH_LBA;
889 size = id_longword(60);
890
891 w= id_word(ID_CSS);
892 if (size < LBA48_CHECK_SIZE)
893 {
894 /* No need to check for LBA48 */
895 }
896 else if (w & ID_CSS_LBA48) {
897 /* Drive is LBA48 capable (and LBA48 is turned on). */
898 if (id_longword(102)) {
899 /* If no. of sectors doesn't fit in 32 bits,
900 * trunacte to this. So it's LBA32 for now.
901 * This can still address devices up to 2TB
902 * though.
903 */
904 size = ULONG_MAX;
905 } else {
906 /* Actual number of sectors fits in 32 bits. */
907 size = id_longword(100);
908 }
909 wn->lba48 = 1;
910 }
911
912 /* Check for DMA. Assume that only LBA capable devices can do
913 * DMA.
914 */
915 w= id_word(ID_CAPABILITIES);
916 id_dma= !!(w & ID_CAP_DMA);
917 w= id_byte(ID_FIELD_VALIDITY)[0];
918 ultra_dma= !!(w & ID_FV_88);
919 dma_base= wn->base_dma;
920 if (dma_base)
921 {
922 if (sys_inb(dma_base + DMA_STATUS, &dma_status) != OK)
923 {
924 panic(w_name(),
925 "unable to read DMA status register",
926 NO_NUM);
927 }
928 }
929 if (disable_dma)
930 ; /* DMA is disabled */
931 else if (id_dma && dma_base)
932 {
933 w= id_word(ID_MULTIWORD_DMA);
934 if (w & (ID_MWDMA_2_SUP|ID_MWDMA_1_SUP|ID_MWDMA_0_SUP))
935 {
936 printf(
937 "%s: multiword DMA modes supported:%s%s%s\n",
938 w_name(),
939 (w & ID_MWDMA_0_SUP) ? " 0" : "",
940 (w & ID_MWDMA_1_SUP) ? " 1" : "",
941 (w & ID_MWDMA_2_SUP) ? " 2" : "");
942 }
943 if (w & (ID_MWDMA_0_SEL|ID_MWDMA_1_SEL|ID_MWDMA_2_SEL))
944 {
945 printf(
946 "%s: multiword DMA mode selected:%s%s%s\n",
947 w_name(),
948 (w & ID_MWDMA_0_SEL) ? " 0" : "",
949 (w & ID_MWDMA_1_SEL) ? " 1" : "",
950 (w & ID_MWDMA_2_SEL) ? " 2" : "");
951 }
952 if (ultra_dma)
953 {
954 w= id_word(ID_ULTRA_DMA);
955 if (w & (ID_UDMA_0_SUP|ID_UDMA_1_SUP|
956 ID_UDMA_2_SUP|ID_UDMA_3_SUP|
957 ID_UDMA_4_SUP|ID_UDMA_5_SUP))
958 {
959 printf(
960 "%s: Ultra DMA modes supported:%s%s%s%s%s%s\n",
961 w_name(),
962 (w & ID_UDMA_0_SUP) ? " 0" : "",
963 (w & ID_UDMA_1_SUP) ? " 1" : "",
964 (w & ID_UDMA_2_SUP) ? " 2" : "",
965 (w & ID_UDMA_3_SUP) ? " 3" : "",
966 (w & ID_UDMA_4_SUP) ? " 4" : "",
967 (w & ID_UDMA_5_SUP) ? " 5" : "");
968 }
969 if (w & (ID_UDMA_0_SEL|ID_UDMA_1_SEL|
970 ID_UDMA_2_SEL|ID_UDMA_3_SEL|
971 ID_UDMA_4_SEL|ID_UDMA_5_SEL))
972 {
973 printf(
974 "%s: Ultra DMA mode selected:%s%s%s%s%s%s\n",
975 w_name(),
976 (w & ID_UDMA_0_SEL) ? " 0" : "",
977 (w & ID_UDMA_1_SEL) ? " 1" : "",
978 (w & ID_UDMA_2_SEL) ? " 2" : "",
979 (w & ID_UDMA_3_SEL) ? " 3" : "",
980 (w & ID_UDMA_4_SEL) ? " 4" : "",
981 (w & ID_UDMA_5_SEL) ? " 5" : "");
982 }
983 }
984 wn->dma= 1;
985 }
986 else if (id_dma || dma_base)
987 {
988 printf("id_dma %d, dma_base 0x%x\n", id_dma, dma_base);
989 }
990 else
991 printf("no DMA support\n");
992
993 #if 0
994 if (wn->dma && wn == &wini[0])
995 {
996 printf("disabling DMA for drive 0\n");
997 wn->dma= 0;
998 }
999 #endif
1000 }
1001
1002 if (wn->lcylinders == 0) {
1003 /* No BIOS parameters? Then make some up. */
1004 wn->lcylinders = wn->pcylinders;
1005 wn->lheads = wn->pheads;
1006 wn->lsectors = wn->psectors;
1007 while (wn->lcylinders > 1024) {
1008 wn->lheads *= 2;
1009 wn->lcylinders /= 2;
1010 }
1011 }
1012 #if ENABLE_ATAPI
1013 } else
1014 if (cmd.command = ATAPI_IDENTIFY,
1015 com_simple(&cmd) == OK && w_waitfor(STATUS_DRQ, STATUS_DRQ) &&
1016 !(wn->w_status & (STATUS_ERR|STATUS_WF))) {
1017 /* An ATAPI device. */
1018 wn->state |= ATAPI;
1019
1020 /* Device information. */
1021 if ((s=sys_insw(wn->base_cmd + REG_DATA, SELF, tmp_buf, 512)) != OK)
1022 panic(w_name(),"Call to sys_insw() failed", s);
1023
1024 /* Why are the strings byte swapped??? */
1025 for (i = 0; i < 40; i++) w_id_string[i] = id_byte(27)[i^1];
1026
1027 size = 0; /* Size set later. */
1028 #endif
1029 } else {
1030 /* Not an ATA device; no translations, no special features. Don't
1031 * touch it unless the BIOS knows about it.
1032 */
1033 if (wn->lcylinders == 0) {
1034 wakeup_ticks = prev_wakeup;
1035 w_testing = 0;
1036 return(ERR);
1037 } /* no BIOS parameters */
1038 wn->pcylinders = wn->lcylinders;
1039 wn->pheads = wn->lheads;
1040 wn->psectors = wn->lsectors;
1041 size = (u32_t) wn->pcylinders * wn->pheads * wn->psectors;
1042 }
1043
1044 /* Restore wakeup_ticks and unset testing mode. */
1045 wakeup_ticks = prev_wakeup;
1046 w_testing = 0;
1047
1048 /* Size of the whole drive */
1049 wn->part[0].dv_size = mul64u(size, SECTOR_SIZE);
1050
1051 /* Reset/calibrate (where necessary) */
1052 if (w_specify() != OK && w_specify() != OK) {
1053 return(ERR);
1054 }
1055
1056 if (wn->irq == NO_IRQ) {
1057 /* Everything looks OK; register IRQ so we can stop polling. */
1058 wn->irq = w_drive < 2 ? AT_WINI_0_IRQ : AT_WINI_1_IRQ;
1059 wn->irq_hook_id = wn->irq; /* id to be returned if interrupt occurs */
1060 if ((s=sys_irqsetpolicy(wn->irq, IRQ_REENABLE, &wn->irq_hook_id)) != OK)
1061 panic(w_name(), "couldn't set IRQ policy", s);
1062 if ((s=sys_irqenable(&wn->irq_hook_id)) != OK)
1063 panic(w_name(), "couldn't enable IRQ line", s);
1064 }
1065 wn->state |= IDENTIFIED;
1066 return(OK);
1067 }
1068
1069 /*===========================================================================*
1070 * w_name *
1071 *===========================================================================*/
1072 PRIVATE char *w_name()
1073 {
1074 /* Return a name for the current device. */
1075 static char name[] = "AT0-D0";
1076
1077 name[2] = '0' + w_instance;
1078 name[5] = '0' + w_drive;
1079 return name;
1080 }
1081
1082 /*===========================================================================*
1083 * w_io_test *
1084 *===========================================================================*/
1085 PRIVATE int w_io_test(void)
1086 {
1087 int r, save_dev;
1088 int save_timeout, save_errors, save_wakeup;
1089 iovec_t iov;
1090 #ifdef CD_SECTOR_SIZE
1091 static char buf[CD_SECTOR_SIZE];
1092 #else
1093 static char buf[SECTOR_SIZE];
1094 #endif
1095
1096 iov.iov_addr = (vir_bytes) buf;
1097 iov.iov_size = sizeof(buf);
1098 save_dev = w_device;
1099
1100 /* Reduce timeout values for this test transaction. */
1101 save_timeout = timeout_ticks;
1102 save_errors = max_errors;
1103 save_wakeup = wakeup_ticks;
1104
1105 if (!w_standard_timeouts) {
1106 timeout_ticks = HZ * 4;
1107 wakeup_ticks = HZ * 6;
1108 max_errors = 3;
1109 }
1110
1111 w_testing = 1;
1112
1113 /* Try I/O on the actual drive (not any (sub)partition). */
1114 if (w_prepare(w_drive * DEV_PER_DRIVE) == NIL_DEV)
1115 panic(w_name(), "Couldn't switch devices", NO_NUM);
1116
1117 r = w_transfer(SELF, DEV_GATHER_S, cvu64(0), &iov, 1, 0);
1118
1119 /* Switch back. */
1120 if (w_prepare(save_dev) == NIL_DEV)
1121 panic(w_name(), "Couldn't switch back devices", NO_NUM);
1122
1123 /* Restore parameters. */
1124 timeout_ticks = save_timeout;
1125 max_errors = save_errors;
1126 wakeup_ticks = save_wakeup;
1127 w_testing = 0;
1128
1129 /* Test if everything worked. */
1130 if (r != OK || iov.iov_size != 0) {
1131 return ERR;
1132 }
1133
1134 /* Everything worked. */
1135
1136 return OK;
1137 }
1138
1139 /*===========================================================================*
1140 * w_specify *
1141 *===========================================================================*/
1142 PRIVATE int w_specify()
1143 {
1144 /* Routine to initialize the drive after boot or when a reset is needed. */
1145
1146 struct wini *wn = w_wn;
1147 struct command cmd;
1148
1149 if ((wn->state & DEAF) && w_reset() != OK) {
1150 return(ERR);
1151 }
1152
1153 if (!(wn->state & ATAPI)) {
1154 /* Specify parameters: precompensation, number of heads and sectors. */
1155 cmd.precomp = wn->precomp;
1156 cmd.count = wn->psectors;
1157 cmd.ldh = w_wn->ldhpref | (wn->pheads - 1);
1158 cmd.command = CMD_SPECIFY; /* Specify some parameters */
1159
1160 /* Output command block and see if controller accepts the parameters. */
1161 if (com_simple(&cmd) != OK) return(ERR);
1162
1163 if (!(wn->state & SMART)) {
1164 /* Calibrate an old disk. */
1165 cmd.sector = 0;
1166 cmd.cyl_lo = 0;
1167 cmd.cyl_hi = 0;
1168 cmd.ldh = w_wn->ldhpref;
1169 cmd.command = CMD_RECALIBRATE;
1170
1171 if (com_simple(&cmd) != OK) return(ERR);
1172 }
1173 }
1174 wn->state |= INITIALIZED;
1175 return(OK);
1176 }
1177
1178 /*===========================================================================*
1179 * do_transfer *
1180 *===========================================================================*/
1181 PRIVATE int do_transfer(struct wini *wn, unsigned int precomp,
1182 unsigned int count, unsigned int sector,
1183 unsigned int opcode, int do_dma)
1184 {
1185 struct command cmd;
1186 unsigned int sector_high;
1187 unsigned secspcyl = wn->pheads * wn->psectors;
1188 int do_lba48;
1189
1190 sector_high= 0; /* For future extensions */
1191
1192 do_lba48= 0;
1193 if (sector >= LBA48_CHECK_SIZE || sector_high != 0)
1194 {
1195 if (wn->lba48)
1196 do_lba48= 1;
1197 else if (sector > LBA_MAX_SIZE || sector_high != 0)
1198 {
1199 /* Strange sector count for LBA device */
1200 return EIO;
1201 }
1202 }
1203
1204 cmd.precomp = precomp;
1205 cmd.count = count;
1206 if (do_dma)
1207 {
1208 cmd.command = opcode == DEV_SCATTER_S ? CMD_WRITE_DMA :
1209 CMD_READ_DMA;
1210 }
1211 else
1212 cmd.command = opcode == DEV_SCATTER_S ? CMD_WRITE : CMD_READ;
1213
1214 if (do_lba48) {
1215 if (do_dma)
1216 {
1217 cmd.command = ((opcode == DEV_SCATTER_S) ?
1218 CMD_WRITE_DMA_EXT : CMD_READ_DMA_EXT);
1219 }
1220 else
1221 {
1222 cmd.command = ((opcode == DEV_SCATTER_S) ?
1223 CMD_WRITE_EXT : CMD_READ_EXT);
1224 }
1225 cmd.count_prev= (count >> 8);
1226 cmd.sector = (sector >> 0) & 0xFF;
1227 cmd.cyl_lo = (sector >> 8) & 0xFF;
1228 cmd.cyl_hi = (sector >> 16) & 0xFF;
1229 cmd.sector_prev= (sector >> 24) & 0xFF;
1230 cmd.cyl_lo_prev= (sector_high) & 0xFF;
1231 cmd.cyl_hi_prev= (sector_high >> 8) & 0xFF;
1232 cmd.ldh = wn->ldhpref;
1233
1234 return com_out_ext(&cmd);
1235 } else if (wn->ldhpref & LDH_LBA) {
1236 cmd.sector = (sector >> 0) & 0xFF;
1237 cmd.cyl_lo = (sector >> 8) & 0xFF;
1238 cmd.cyl_hi = (sector >> 16) & 0xFF;
1239 cmd.ldh = wn->ldhpref | ((sector >> 24) & 0xF);
1240 } else {
1241 int cylinder, head, sec;
1242 cylinder = sector / secspcyl;
1243 head = (sector % secspcyl) / wn->psectors;
1244 sec = sector % wn->psectors;
1245 cmd.sector = sec + 1;
1246 cmd.cyl_lo = cylinder & BYTE;
1247 cmd.cyl_hi = (cylinder >> 8) & BYTE;
1248 cmd.ldh = wn->ldhpref | head;
1249 }
1250
1251 return com_out(&cmd);
1252 }
1253
1254 /*===========================================================================*
1255 * w_transfer *
1256 *===========================================================================*/
1257 PRIVATE int w_transfer(proc_nr, opcode, position, iov, nr_req, safe)
1258 int proc_nr; /* process doing the request */
1259 int opcode; /* DEV_GATHER_S or DEV_SCATTER_S */
1260 u64_t position; /* offset on device to read or write */
1261 iovec_t *iov; /* pointer to read or write request vector */
1262 unsigned nr_req; /* length of request vector */
1263 int safe; /* iov contains addresses (0) or grants? */
1264 {
1265 struct wini *wn = w_wn;
1266 iovec_t *iop, *iov_end = iov + nr_req;
1267 int n, r, s, errors, do_dma, do_write, do_copyout;
1268 unsigned long v, block, w_status;
1269 u64_t dv_size = w_dv->dv_size;
1270 unsigned cylinder, head, sector, nbytes;
1271 unsigned dma_buf_offset;
1272 size_t addr_offset = 0;
1273
1274 #if ENABLE_ATAPI
1275 if (w_wn->state & ATAPI) {
1276 return atapi_transfer(proc_nr, opcode, position, iov, nr_req, safe);
1277 }
1278 #endif
1279
1280 /* Check disk address. */
1281 if (rem64u(position, SECTOR_SIZE) != 0) return(EINVAL);
1282
1283 errors = 0;
1284
1285 while (nr_req > 0) {
1286 /* How many bytes to transfer? */
1287 nbytes = 0;
1288 for (iop = iov; iop < iov_end; iop++) nbytes += iop->iov_size;
1289 if ((nbytes & SECTOR_MASK) != 0) return(EINVAL);
1290
1291 /* Which block on disk and how close to EOF? */
1292 if (cmp64(position, dv_size) >= 0) return(OK); /* At EOF */
1293 if (cmp64(add64ul(position, nbytes), dv_size) > 0)
1294 nbytes = diff64(dv_size, position);
1295 block = div64u(add64(w_dv->dv_base, position), SECTOR_SIZE);
1296
1297 do_dma= wn->dma;
1298 do_write= (opcode == DEV_SCATTER_S);
1299
1300 if (nbytes >= wn->max_count) {
1301 /* The drive can't do more then max_count at once. */
1302 nbytes = wn->max_count;
1303 }
1304
1305 /* First check to see if a reinitialization is needed. */
1306 if (!(wn->state & INITIALIZED) && w_specify() != OK) return(EIO);
1307
1308 if (do_dma)
1309 {
1310 setup_dma(&nbytes, proc_nr, iov, do_write, &do_copyout, safe);
1311 #if 0
1312 printf("nbytes = %d\n", nbytes);
1313 #endif
1314 }
1315
1316 /* Tell the controller to transfer nbytes bytes. */
1317 r = do_transfer(wn, wn->precomp, (nbytes >> SECTOR_SHIFT),
1318 block, opcode, do_dma);
1319
1320 if (opcode == DEV_SCATTER_S) {
1321 /* The specs call for a 400 ns wait after issuing the command.
1322 * Reading the alternate status register is the suggested
1323 * way to implement this wait.
1324 */
1325 if (sys_inb((wn->base_ctl+REG_CTL_ALTSTAT), &w_status) != OK)
1326 panic(w_name(), "couldn't get status", NO_NUM);
1327 }
1328
1329 if (do_dma)
1330 {
1331 /* Wait for the interrupt, check DMA status and optionally
1332 * copy out.
1333 */
1334
1335 if ((r = at_intr_wait()) != OK)
1336 {
1337 /* Don't retry if sector marked bad or too many
1338 * errors.
1339 */
1340 if (r == ERR_BAD_SECTOR || ++errors == max_errors) {
1341 w_command = CMD_IDLE;
1342 return(EIO);
1343 }
1344 continue;
1345 }
1346
1347 /* Wait for DMA_ST_INT to get set */
1348 w_waitfor_dma(DMA_ST_INT, DMA_ST_INT);
1349
1350 r= sys_inb(wn->base_dma + DMA_STATUS, &v);
1351 if (r != 0) panic("at_wini", "w_transfer: sys_inb failed", r);
1352
1353 #if 0
1354 printf("dma_status: 0x%x\n", v);
1355 #endif
1356 if (!(v & DMA_ST_INT))
1357 {
1358 /* DMA did not complete successfully */
1359 if (v & DMA_ST_BM_ACTIVE)
1360 panic(w_name(), "DMA did not complete", NO_NUM);
1361 else if (v & DMA_ST_ERROR)
1362 {
1363 printf("at_wini: DMA error\n");
1364 r= EIO;
1365 break;
1366 }
1367 else
1368 {
1369 #if 0
1370 printf("DMA buffer too small\n");
1371 #endif
1372 panic(w_name(), "DMA buffer too small", NO_NUM);
1373 }
1374 }
1375 else if (v & DMA_ST_BM_ACTIVE)
1376 panic(w_name(), "DMA buffer too large", NO_NUM);
1377
1378 dma_buf_offset= 0;
1379 while (r == OK && nbytes > 0)
1380 {
1381 n= iov->iov_size;
1382 if (n > nbytes)
1383 n= nbytes;
1384
1385 if (do_copyout)
1386 {
1387 if(safe) {
1388 s= sys_safecopyto(proc_nr, iov->iov_addr,
1389 addr_offset,
1390 (vir_bytes)dma_buf+dma_buf_offset, n, D);
1391 } else {
1392 s= sys_vircopy(SELF, D,
1393 (vir_bytes)dma_buf+dma_buf_offset,
1394 proc_nr, D,
1395 iov->iov_addr + addr_offset, n);
1396 }
1397 if (s != OK)
1398 {
1399 panic(w_name(),
1400 "w_transfer: sys_vircopy failed",
1401 s);
1402 }
1403 }
1404
1405 /* Book the bytes successfully transferred. */
1406 nbytes -= n;
1407 position= add64ul(position, n);
1408 if ((iov->iov_size -= n) == 0) {
1409 iov++; nr_req--; addr_offset = 0;
1410 }
1411 dma_buf_offset += n;
1412 }
1413 }
1414
1415 while (r == OK && nbytes > 0) {
1416 /* For each sector, wait for an interrupt and fetch the data
1417 * (read), or supply data to the controller and wait for an
1418 * interrupt (write).
1419 */
1420
1421 if (opcode == DEV_GATHER_S) {
1422 /* First an interrupt, then data. */
1423 if ((r = at_intr_wait()) != OK) {
1424 /* An error, send data to the bit bucket. */
1425 if (w_wn->w_status & STATUS_DRQ) {
1426 if ((s=sys_insw(wn->base_cmd+REG_DATA,
1427 SELF, tmp_buf,
1428 SECTOR_SIZE)) != OK)
1429 {
1430 panic(w_name(),
1431 "Call to sys_insw() failed",
1432 s);
1433 }
1434 }
1435 break;
1436 }
1437 }
1438
1439 /* Wait for busy to clear. */
1440 if (!w_waitfor(STATUS_BSY, 0)) { r = ERR; break; }
1441
1442 /* Wait for data transfer requested. */
1443 if (!w_waitfor(STATUS_DRQ, STATUS_DRQ)) { r = ERR; break; }
1444
1445 /* Copy bytes to or from the device's buffer. */
1446 if (opcode == DEV_GATHER_S) {
1447 if(safe) {
1448 s=sys_safe_insw(wn->base_cmd + REG_DATA, proc_nr,
1449 (void *) (iov->iov_addr), addr_offset,
1450 SECTOR_SIZE);
1451 } else {
1452 s=sys_insw(wn->base_cmd + REG_DATA, proc_nr,
1453 (void *) (iov->iov_addr + addr_offset),
1454 SECTOR_SIZE);
1455 }
1456 if(s != OK) {
1457 panic(w_name(),"Call to sys_insw() failed", s);
1458 }
1459 } else {
1460 if(safe) {
1461 s=sys_safe_outsw(wn->base_cmd + REG_DATA, proc_nr,
1462 (void *) (iov->iov_addr), addr_offset,
1463 SECTOR_SIZE);
1464 } else {
1465 s=sys_outsw(wn->base_cmd + REG_DATA, proc_nr,
1466 (void *) (iov->iov_addr + addr_offset),
1467 SECTOR_SIZE);
1468 }
1469
1470 if(s != OK) {
1471 panic(w_name(),"Call to sys_outsw() failed",
1472 s);
1473 }
1474
1475 /* Data sent, wait for an interrupt. */
1476 if ((r = at_intr_wait()) != OK) break;
1477 }
1478
1479 /* Book the bytes successfully transferred. */
1480 nbytes -= SECTOR_SIZE;
1481 position= add64u(position, SECTOR_SIZE);
1482 addr_offset += SECTOR_SIZE;
1483 if ((iov->iov_size -= SECTOR_SIZE) == 0) {
1484 iov++;
1485 nr_req--;
1486 addr_offset = 0;
1487 }
1488 }
1489
1490 /* Any errors? */
1491 if (r != OK) {
1492 /* Don't retry if sector marked bad or too many errors. */
1493 if (r == ERR_BAD_SECTOR || ++errors == max_errors) {
1494 w_command = CMD_IDLE;
1495 return(EIO);
1496 }
1497 }
1498 }
1499
1500 w_command = CMD_IDLE;
1501 return(OK);
1502 }
1503
1504 /*===========================================================================*
1505 * com_out *
1506 *===========================================================================*/
1507 PRIVATE int com_out(cmd)
1508 struct command *cmd; /* Command block */
1509 {
1510 /* Output the command block to the winchester controller and return status */
1511
1512 struct wini *wn = w_wn;
1513 unsigned base_cmd = wn->base_cmd;
1514 unsigned base_ctl = wn->base_ctl;
1515 pvb_pair_t outbyte[7]; /* vector for sys_voutb() */
1516 int s; /* status for sys_(v)outb() */
1517
1518 if (w_wn->state & IGNORING) return ERR;
1519
1520 if (!w_waitfor(STATUS_BSY, 0)) {
1521 printf("%s: controller not ready\n", w_name());
1522 return(ERR);
1523 }
1524
1525 /* Select drive. */
1526 if ((s=sys_outb(base_cmd + REG_LDH, cmd->ldh)) != OK)
1527 panic(w_name(),"Couldn't write register to select drive",s);
1528
1529 if (!w_waitfor(STATUS_BSY, 0)) {
1530 printf("%s: com_out: drive not ready\n", w_name());
1531 return(ERR);
1532 }
1533
1534 /* Schedule a wakeup call, some controllers are flaky. This is done with
1535 * a synchronous alarm. If a timeout occurs a SYN_ALARM message is sent
1536 * from HARDWARE, so that w_intr_wait() can call w_timeout() in case the
1537 * controller was not able to execute the command. Leftover timeouts are
1538 * simply ignored by the main loop.
1539 */
1540 sys_setalarm(wakeup_ticks, 0);
1541
1542 wn->w_status = STATUS_ADMBSY;
1543 w_command = cmd->command;
1544 pv_set(outbyte[0], base_ctl + REG_CTL, wn->pheads >= 8 ? CTL_EIGHTHEADS : 0);
1545 pv_set(outbyte[1], base_cmd + REG_PRECOMP, cmd->precomp);
1546 pv_set(outbyte[2], base_cmd + REG_COUNT, cmd->count);
1547 pv_set(outbyte[3], base_cmd + REG_SECTOR, cmd->sector);
1548 pv_set(outbyte[4], base_cmd + REG_CYL_LO, cmd->cyl_lo);
1549 pv_set(outbyte[5], base_cmd + REG_CYL_HI, cmd->cyl_hi);
1550 pv_set(outbyte[6], base_cmd + REG_COMMAND, cmd->command);
1551 if ((s=sys_voutb(outbyte,7)) != OK)
1552 panic(w_name(),"Couldn't write registers with sys_voutb()",s);
1553 return(OK);
1554 }
1555
1556 /*===========================================================================*
1557 * com_out_ext *
1558 *===========================================================================*/
1559 PRIVATE int com_out_ext(cmd)
1560 struct command *cmd; /* Command block */
1561 {
1562 /* Output the command block to the winchester controller and return status */
1563
1564 struct wini *wn = w_wn;
1565 unsigned base_cmd = wn->base_cmd;
1566 unsigned base_ctl = wn->base_ctl;
1567 pvb_pair_t outbyte[11]; /* vector for sys_voutb() */
1568 int s; /* status for sys_(v)outb() */
1569 unsigned long w_status;
1570
1571 if (w_wn->state & IGNORING) return ERR;
1572
1573 if (!w_waitfor(STATUS_BSY, 0)) {
1574 printf("%s: controller not ready\n", w_name());
1575 return(ERR);
1576 }
1577
1578 /* Select drive. */
1579 if ((s=sys_outb(base_cmd + REG_LDH, cmd->ldh)) != OK)
1580 panic(w_name(),"Couldn't write register to select drive",s);
1581
1582 if (!w_waitfor(STATUS_BSY, 0)) {
1583 printf("%s: com_out: drive not ready\n", w_name());
1584 return(ERR);
1585 }
1586
1587 /* Schedule a wakeup call, some controllers are flaky. This is done with
1588 * a synchronous alarm. If a timeout occurs a SYN_ALARM message is sent
1589 * from HARDWARE, so that w_intr_wait() can call w_timeout() in case the
1590 * controller was not able to execute the command. Leftover timeouts are
1591 * simply ignored by the main loop.
1592 */
1593 sys_setalarm(wakeup_ticks, 0);
1594
1595 wn->w_status = STATUS_ADMBSY;
1596 w_command = cmd->command;
1597 pv_set(outbyte[0], base_ctl + REG_CTL, 0);
1598 pv_set(outbyte[1], base_cmd + REG_COUNT, cmd->count_prev);
1599 pv_set(outbyte[2], base_cmd + REG_SECTOR, cmd->sector_prev);
1600 pv_set(outbyte[3], base_cmd + REG_CYL_LO, cmd->cyl_lo_prev);
1601 pv_set(outbyte[4], base_cmd + REG_CYL_HI, cmd->cyl_hi_prev);
1602 pv_set(outbyte[5], base_cmd + REG_COUNT, cmd->count);
1603 pv_set(outbyte[6], base_cmd + REG_SECTOR, cmd->sector);
1604 pv_set(outbyte[7], base_cmd + REG_CYL_LO, cmd->cyl_lo);
1605 pv_set(outbyte[8], base_cmd + REG_CYL_HI, cmd->cyl_hi);
1606
1607 pv_set(outbyte[10], base_cmd + REG_COMMAND, cmd->command);
1608 if ((s=sys_voutb(outbyte, 11)) != OK)
1609 panic(w_name(),"Couldn't write registers with sys_voutb()",s);
1610
1611 return(OK);
1612 }
1613
1614 /*===========================================================================*
1615 * setup_dma *
1616 *===========================================================================*/
1617 PRIVATE void setup_dma(sizep, proc_nr, iov, do_write, do_copyoutp, safe)
1618 unsigned *sizep;
1619 int proc_nr;
1620 iovec_t *iov;
1621 int do_write;
1622 int *do_copyoutp;
1623 int safe;
1624 {
1625 phys_bytes phys, user_phys;
1626 unsigned n, offset, size;
1627 int i, j, r, bad;
1628 unsigned long v;
1629 struct wini *wn = w_wn;
1630
1631 /* First try direct scatter/gather to the supplied buffers */
1632 size= *sizep;
1633 i= 0; /* iov index */
1634 j= 0; /* prdt index */
1635 bad= 0;
1636 offset= 0; /* Offset in current iov */
1637
1638 #if 0
1639 printf("setup_dma: proc_nr %d\n", proc_nr);
1640 #endif
1641
1642 while (size > 0)
1643 {
1644 #if 0
1645 printf(
1646 "setup_dma: iov[%d]: addr 0x%x, size %d offset %d, size %d\n",
1647 i, iov[i].iov_addr, iov[i].iov_size, offset, size);
1648 #endif
1649
1650 n= iov[i].iov_size-offset;
1651 if (n > size)
1652 n= size;
1653 if (n == 0 || (n & 1))
1654 panic("at_wini", "bad size in iov", iov[i].iov_size);
1655 if(safe) {
1656 r= sys_umap(proc_nr, GRANT_SEG, iov[i].iov_addr, n,&user_phys);
1657 user_phys += offset;
1658 } else {
1659 r= sys_umap(proc_nr, D, iov[i].iov_addr+offset, n, &user_phys);
1660 }
1661 if (r != 0)
1662 panic("at_wini", "can't map user buffer", r);
1663 if (user_phys & 1)
1664 {
1665 /* Buffer is not aligned */
1666 printf("setup_dma: user buffer is not aligned\n");
1667 bad= 1;
1668 break;
1669 }
1670
1671 /* vector is not allowed to cross a 64K boundary */
1672 if (user_phys/0x10000 != (user_phys+n-1)/0x10000)
1673 n= ((user_phys/0x10000)+1)*0x10000 - user_phys;
1674
1675 /* vector is not allowed to be bigger than 64K, but we get that
1676 * for free.
1677 */
1678
1679 if (j >= N_PRDTE)
1680 {
1681 /* Too many entries */
1682 bad= 1;
1683 break;
1684 }
1685
1686 prdt[j].prdte_base= user_phys;
1687 prdt[j].prdte_count= n;
1688 prdt[j].prdte_reserved= 0;
1689 prdt[j].prdte_flags= 0;
1690 j++;
1691
1692 offset += n;
1693 if (offset >= iov[i].iov_size)
1694 {
1695 i++;
1696 offset= 0;
1697 }
1698
1699 size -= n;
1700 }
1701
1702 if (!bad)
1703 {
1704 if (j <= 0 || j > N_PRDTE)
1705 panic("at_wini", "bad prdt index", j);
1706 prdt[j-1].prdte_flags |= PRDTE_FL_EOT;
1707
1708 #if 0
1709 for (i= 0; i<j; i++)
1710 {
1711 printf("prdt[%d]: base 0x%x, size %d, flags 0x%x\n",
1712 i, prdt[i].prdte_base, prdt[i].prdte_count,
1713 prdt[i].prdte_flags);
1714 }
1715 #endif
1716 }
1717
1718 /* The caller needs to perform a copy-out from the dma buffer if
1719 * this is a read request and we can't DMA directly to the user's
1720 * buffers.
1721 */
1722 *do_copyoutp= (!do_write && bad);
1723
1724 if (bad)
1725 {
1726 /* Adjust request size */
1727 size= *sizep;
1728 if (size > ATA_DMA_BUF_SIZE)
1729 *sizep= size= ATA_DMA_BUF_SIZE;
1730
1731 if (do_write)
1732 {
1733 /* Copy-in */
1734 for (offset= 0; offset < size; offset += n)
1735 {
1736 n= size-offset;
1737 if (n > iov->iov_size)
1738 n= iov->iov_size;
1739
1740 if(safe) {
1741 r= sys_safecopyfrom(proc_nr, iov->iov_addr,
1742 0, (vir_bytes)dma_buf+offset, n, D);
1743 } else {
1744 r= sys_vircopy(proc_nr, D, iov->iov_addr,
1745 SELF, D, (vir_bytes)dma_buf+offset,
1746 n);
1747 }
1748 if (r != OK)
1749 {
1750 panic(w_name(),
1751 "setup_dma: sys_vircopy failed",
1752 r);
1753 }
1754 iov++;
1755 }
1756 }
1757
1758 /* Fill-in the physical region descriptor table */
1759 phys= dma_buf_phys;
1760 if (phys & 1)
1761 {
1762 /* Two byte alignment is required */
1763 panic("at_wini", "bad buffer alignment in setup_dma",
1764 phys);
1765 }
1766 for (j= 0; j<N_PRDTE; i++)
1767 {
1768 if (size == 0)
1769 {
1770 panic("at_wini", "bad size in setup_dma",
1771 size);
1772 }
1773 if (size & 1)
1774 {
1775 /* Two byte alignment is required for size */
1776 panic("at_wini",
1777 "bad size alignment in setup_dma",
1778 size);
1779 }
1780 n= size;
1781
1782 /* Buffer is not allowed to cross a 64K boundary */
1783 if (phys / 0x10000 != (phys+n-1) / 0x10000)
1784 {
1785 n= ((phys/0x10000)+1)*0x10000 - phys;
1786 }
1787 prdt[j].prdte_base= phys;
1788 prdt[j].prdte_count= n;
1789 prdt[j].prdte_reserved= 0;
1790 prdt[j].prdte_flags= 0;
1791
1792 size -= n;
1793 if (size == 0)
1794 {
1795 prdt[j].prdte_flags |= PRDTE_FL_EOT;
1796 break;
1797 }
1798 }
1799 if (size != 0)
1800 panic("at_wini", "size to large for prdt", NO_NUM);
1801
1802 #if 0
1803 for (i= 0; i<=j; i++)
1804 {
1805 printf("prdt[%d]: base 0x%x, size %d, flags 0x%x\n",
1806 i, prdt[i].prdte_base, prdt[i].prdte_count,
1807 prdt[i].prdte_flags);
1808 }
1809 #endif
1810 }
1811
1812 /* Stop bus master operation */
1813 r= sys_outb(wn->base_dma + DMA_COMMAND, 0);
1814 if (r != 0) panic("at_wini", "setup_dma: sys_outb failed", r);
1815
1816 /* Verify that the bus master is not active */
1817 r= sys_inb(wn->base_dma + DMA_STATUS, &v);
1818 if (r != 0) panic("at_wini", "setup_dma: sys_inb failed", r);
1819 if (v & DMA_ST_BM_ACTIVE)
1820 panic("at_wini", "Bus master IDE active", NO_NUM);
1821
1822 if (prdt_phys & 3)
1823 panic("at_wini", "prdt not aligned", prdt_phys);
1824 r= sys_outl(wn->base_dma + DMA_PRDTP, prdt_phys);
1825 if (r != 0) panic("at_wini", "setup_dma: sys_outl failed", r);
1826
1827 /* Clear interrupt and error flags */
1828 r= sys_outb(wn->base_dma + DMA_STATUS, DMA_ST_INT | DMA_ST_ERROR);
1829 if (r != 0) panic("at_wini", "setup_dma: sys_outb failed", r);
1830
1831 /* Assume disk reads. Start DMA */
1832 v= DMA_CMD_START;
1833 if (!do_write)
1834 {
1835 /* Disk reads generate PCI write cycles. */
1836 v |= DMA_CMD_WRITE;
1837 }
1838 r= sys_outb(wn->base_dma + DMA_COMMAND, v);
1839 if (r != 0) panic("at_wini", "setup_dma: sys_outb failed", r);
1840
1841 #if 0
1842 r= sys_inb(wn->base_dma + DMA_STATUS, &v);
1843 if (r != 0) panic("at_wini", "setup_dma: sys_inb failed", r);
1844 printf("dma status: 0x%x\n", v);
1845 #endif
1846 }
1847
1848
1849 /*===========================================================================*
1850 * w_need_reset *
1851 *===========================================================================*/
1852 PRIVATE void w_need_reset()
1853 {
1854 /* The controller needs to be reset. */
1855 struct wini *wn;
1856 int dr = 0;
1857
1858 for (wn = wini; wn < &wini[MAX_DRIVES]; wn++, dr++) {
1859 if (wn->base_cmd == w_wn->base_cmd) {
1860 wn->state |= DEAF;
1861 wn->state &= ~INITIALIZED;
1862 }
1863 }
1864 }
1865
1866 /*===========================================================================*
1867 * w_do_close *
1868 *===========================================================================*/
1869 PRIVATE int w_do_close(dp, m_ptr)
1870 struct driver *dp;
1871 message *m_ptr;
1872 {
1873 /* Device close: Release a device. */
1874 if (w_prepare(m_ptr->DEVICE) == NIL_DEV)
1875 return(ENXIO);
1876 w_wn->open_ct--;
1877 #if ENABLE_ATAPI
1878 if (w_wn->open_ct == 0 && (w_wn->state & ATAPI)) atapi_close();
1879 #endif
1880 return(OK);
1881 }
1882
1883 /*===========================================================================*
1884 * com_simple *
1885 *===========================================================================*/
1886 PRIVATE int com_simple(cmd)
1887 struct command *cmd; /* Command block */
1888 {
1889 /* A simple controller command, only one interrupt and no data-out phase. */
1890 int r;
1891
1892 if (w_wn->state & IGNORING) return ERR;
1893
1894 if ((r = com_out(cmd)) == OK) r = at_intr_wait();
1895 w_command = CMD_IDLE;
1896 return(r);
1897 }
1898
1899 /*===========================================================================*
1900 * w_timeout *
1901 *===========================================================================*/
1902 PRIVATE void w_timeout(void)
1903 {
1904 struct wini *wn = w_wn;
1905
1906 switch (w_command) {
1907 case CMD_IDLE:
1908 break; /* fine */
1909 case CMD_READ:
1910 case CMD_READ_EXT:
1911 case CMD_WRITE:
1912 case CMD_WRITE_EXT:
1913 /* Impossible, but not on PC's: The controller does not respond. */
1914
1915 /* Limiting multisector I/O seems to help. */
1916 if (wn->max_count > 8 * SECTOR_SIZE) {
1917 wn->max_count = 8 * SECTOR_SIZE;
1918 } else {
1919 wn->max_count = SECTOR_SIZE;
1920 }
1921 /*FALL THROUGH*/
1922 default:
1923 /* Some other command. */
1924 if (w_testing) wn->state |= IGNORING; /* Kick out this drive. */
1925 else if (!w_silent) printf("%s: timeout on command 0x%02x\n",
1926 w_name(), w_command);
1927 w_need_reset();
1928 wn->w_status = 0;
1929 }
1930 }
1931
1932 /*===========================================================================*
1933 * w_reset *
1934 *===========================================================================*/
1935 PRIVATE int w_reset()
1936 {
1937 /* Issue a reset to the controller. This is done after any catastrophe,
1938 * like the controller refusing to respond.
1939 */
1940 int s;
1941 struct wini *wn = w_wn;
1942
1943 /* Don't bother if this drive is forgotten. */
1944 if (w_wn->state & IGNORING) return ERR;
1945
1946 /* Wait for any internal drive recovery. */
1947 tickdelay(RECOVERY_TICKS);
1948
1949 /* Strobe reset bit */
1950 if ((s=sys_outb(wn->base_ctl + REG_CTL, CTL_RESET)) != OK)
1951 panic(w_name(),"Couldn't strobe reset bit",s);
1952 tickdelay(DELAY_TICKS);
1953 if ((s=sys_outb(wn->base_ctl + REG_CTL, 0)) != OK)
1954 panic(w_name(),"Couldn't strobe reset bit",s);
1955 tickdelay(DELAY_TICKS);
1956
1957 /* Wait for controller ready */
1958 if (!w_waitfor(STATUS_BSY, 0)) {
1959 printf("%s: reset failed, drive busy\n", w_name());
1960 return(ERR);
1961 }
1962
1963 /* The error register should be checked now, but some drives mess it up. */
1964
1965 for (wn = wini; wn < &wini[MAX_DRIVES]; wn++) {
1966 if (wn->base_cmd == w_wn->base_cmd) {
1967 wn->state &= ~DEAF;
1968 if (w_wn->irq_need_ack) {
1969 /* Make sure irq is actually enabled.. */
1970 sys_irqenable(&w_wn->irq_hook_id);
1971 }
1972 }
1973 }
1974
1975
1976 return(OK);
1977 }
1978
1979 /*===========================================================================*
1980 * w_intr_wait *
1981 *===========================================================================*/
1982 PRIVATE void w_intr_wait()
1983 {
1984 /* Wait for a task completion interrupt. */
1985
1986 int r;
1987 unsigned long w_status;
1988 message m;
1989
1990 if (w_wn->irq != NO_IRQ) {
1991 /* Wait for an interrupt that sets w_status to "not busy".
1992 * (w_timeout() also clears w_status.)
1993 */
1994 while (w_wn->w_status & (STATUS_ADMBSY|STATUS_BSY)) {
1995 int rr;
1996 if((rr=receive(ANY, &m)) != OK)
1997 panic("at_wini", "receive(ANY) failed", rr);
1998 switch(m.m_type) {
1999 case SYN_ALARM:
2000 /* Timeout. */
2001 w_timeout(); /* a.o. set w_status */
2002 break;
2003 case HARD_INT:
2004 /* Interrupt. */
2005 r= sys_inb(w_wn->base_cmd + REG_STATUS, &w_status);
2006 if (r != 0)
2007 panic("at_wini", "sys_inb failed", r);
2008 w_wn->w_status= w_status;
2009 ack_irqs(m.NOTIFY_ARG);
2010 break;
2011 case DEV_PING:
2012 /* RS monitor ping. */
2013 notify(m.m_source);
2014 break;
2015 default:
2016 /* unhandled message.
2017 * queue it and handle it in the libdriver loop.
2018 */
2019 mq_queue(&m);
2020 }
2021 }
2022 } else {
2023 /* Interrupt not yet allocated; use polling. */
2024 (void) w_waitfor(STATUS_BSY, 0);
2025 }
2026 }
2027
2028 /*===========================================================================*
2029 * at_intr_wait *
2030 *===========================================================================*/
2031 PRIVATE int at_intr_wait()
2032 {
2033 /* Wait for an interrupt, study the status bits and return error/success. */
2034 int r, s;
2035 unsigned long inbval;
2036
2037 w_intr_wait();
2038 if ((w_wn->w_status & (STATUS_BSY | STATUS_WF | STATUS_ERR)) == 0) {
2039 r = OK;
2040 } else {
2041 if ((s=sys_inb(w_wn->base_cmd + REG_ERROR, &inbval)) != OK)
2042 panic(w_name(),"Couldn't read register",s);
2043 if ((w_wn->w_status & STATUS_ERR) && (inbval & ERROR_BB)) {
2044 r = ERR_BAD_SECTOR; /* sector marked bad, retries won't help */
2045 } else {
2046 r = ERR; /* any other error */
2047 }
2048 }
2049 w_wn->w_status |= STATUS_ADMBSY; /* assume still busy with I/O */
2050 return(r);
2051 }
2052
2053 /*===========================================================================*
2054 * w_waitfor *
2055 *===========================================================================*/
2056 PRIVATE int w_waitfor(mask, value)
2057 int mask; /* status mask */
2058 int value; /* required status */
2059 {
2060 /* Wait until controller is in the required state. Return zero on timeout.
2061 * An alarm that set a timeout flag is used. TIMEOUT is in micros, we need
2062 * ticks. Disabling the alarm is not needed, because a static flag is used
2063 * and a leftover timeout cannot do any harm.
2064 */
2065 unsigned long w_status;
2066 clock_t t0, t1;
2067 int s;
2068
2069 getuptime(&t0);
2070 do {
2071 if ((s=sys_inb(w_wn->base_cmd + REG_STATUS, &w_status)) != OK)
2072 panic(w_name(),"Couldn't read register",s);
2073 w_wn->w_status= w_status;
2074 if ((w_wn->w_status & mask) == value) {
2075 return 1;
2076 }
2077 } while ((s=getuptime(&t1)) == OK && (t1-t0) < timeout_ticks );
2078 if (OK != s) printf("AT_WINI: warning, get_uptime failed: %d\n",s);
2079
2080 w_need_reset(); /* controller gone deaf */
2081 return(0);
2082 }
2083
2084 /*===========================================================================*
2085 * w_waitfor_dma *
2086 *===========================================================================*/
2087 PRIVATE int w_waitfor_dma(mask, value)
2088 int mask; /* status mask */
2089 int value; /* required status */
2090 {
2091 /* Wait until controller is in the required state. Return zero on timeout.
2092 * An alarm that set a timeout flag is used. TIMEOUT is in micros, we need
2093 * ticks. Disabling the alarm is not needed, because a static flag is used
2094 * and a leftover timeout cannot do any harm.
2095 */
2096 unsigned long w_status;
2097 clock_t t0, t1;
2098 int s;
2099
2100 getuptime(&t0);
2101 do {
2102 if ((s=sys_inb(w_wn->base_dma + DMA_STATUS, &w_status)) != OK)
2103 panic(w_name(),"Couldn't read register",s);
2104 if ((w_status & mask) == value) {
2105 return 1;
2106 }
2107 } while ((s=getuptime(&t1)) == OK && (t1-t0) < timeout_ticks );
2108 if (OK != s) printf("AT_WINI: warning, get_uptime failed: %d\n",s);
2109
2110 return(0);
2111 }
2112
2113 /*===========================================================================*
2114 * w_geometry *
2115 *===========================================================================*/
2116 PRIVATE void w_geometry(entry)
2117 struct partition *entry;
2118 {
2119 struct wini *wn = w_wn;
2120
2121 if (wn->state & ATAPI) { /* Make up some numbers. */
2122 entry->cylinders = div64u(wn->part[0].dv_size, SECTOR_SIZE) / (64*32);
2123 entry->heads = 64;
2124 entry->sectors = 32;
2125 } else { /* Return logical geometry. */
2126 entry->cylinders = wn->lcylinders;
2127 entry->heads = wn->lheads;
2128 entry->sectors = wn->lsectors;
2129 }
2130 }
2131
2132 #if ENABLE_ATAPI
2133 /*===========================================================================*
2134 * atapi_open *
2135 *===========================================================================*/
2136 PRIVATE int atapi_open()
2137 {
2138 /* Should load and lock the device and obtain its size. For now just set the
2139 * size of the device to something big. What is really needed is a generic
2140 * SCSI layer that does all this stuff for ATAPI and SCSI devices (kjb). (XXX)
2141 */
2142 w_wn->part[0].dv_size = mul64u(800L*1024, 1024);
2143 return(OK);
2144 }
2145
2146 /*===========================================================================*
2147 * atapi_close *
2148 *===========================================================================*/
2149 PRIVATE void atapi_close()
2150 {
2151 /* Should unlock the device. For now do nothing. (XXX) */
2152 }
2153
2154 void sense_request(void)
2155 {
2156 int r, i;
2157 static u8_t sense[100], packet[ATAPI_PACKETSIZE];
2158
2159 packet[0] = SCSI_SENSE;
2160 packet[1] = 0;
2161 packet[2] = 0;
2162 packet[3] = 0;
2163 packet[4] = SENSE_PACKETSIZE;
2164 packet[5] = 0;
2165 packet[7] = 0;
2166 packet[8] = 0;
2167 packet[9] = 0;
2168 packet[10] = 0;
2169 packet[11] = 0;
2170
2171 for(i = 0; i < SENSE_PACKETSIZE; i++) sense[i] = 0xff;
2172 r = atapi_sendpacket(packet, SENSE_PACKETSIZE);
2173 if (r != OK) { printf("request sense command failed\n"); return; }
2174 if (atapi_intr_wait() <= 0) { printf("WARNING: request response failed\n"); }
2175
2176 if (sys_insw(w_wn->base_cmd + REG_DATA, SELF, (void *) sense, SENSE_PACKETSIZE) != OK)
2177 printf("WARNING: sense reading failed\n");
2178
2179 printf("sense data:");
2180 for(i = 0; i < SENSE_PACKETSIZE; i++) printf(" %02x", sense[i]);
2181 printf("\n");
2182 }
2183
2184 /*===========================================================================*
2185 * atapi_transfer *
2186 *===========================================================================*/
2187 PRIVATE int atapi_transfer(proc_nr, opcode, position, iov, nr_req, safe)
2188 int proc_nr; /* process doing the request */
2189 int opcode; /* DEV_GATHER_S or DEV_SCATTER_S */
2190 u64_t position; /* offset on device to read or write */
2191 iovec_t *iov; /* pointer to read or write request vector */
2192 unsigned nr_req; /* length of request vector */
2193 int safe; /* use safecopies? */
2194 {
2195 struct wini *wn = w_wn;
2196 iovec_t *iop, *iov_end = iov + nr_req;
2197 int r, s, errors, fresh;
2198 u64_t pos;
2199 unsigned long block;
2200 u64_t dv_size = w_dv->dv_size;
2201 unsigned nbytes, nblocks, count, before, chunk;
2202 static u8_t packet[ATAPI_PACKETSIZE];
2203 size_t addr_offset = 0;
2204
2205 errors = fresh = 0;
2206
2207 while (nr_req > 0 && !fresh) {
2208 /* The Minix block size is smaller than the CD block size, so we
2209 * may have to read extra before or after the good data.
2210 */
2211 pos = add64(w_dv->dv_base, position);
2212 block = div64u(pos, CD_SECTOR_SIZE);
2213 before = rem64u(pos, CD_SECTOR_SIZE);
2214
2215 /* How many bytes to transfer? */
2216 nbytes = count = 0;
2217 for (iop = iov; iop < iov_end; iop++) {
2218 nbytes += iop->iov_size;
2219 if ((before + nbytes) % CD_SECTOR_SIZE == 0) count = nbytes;
2220 }
2221
2222 /* Does one of the memory chunks end nicely on a CD sector multiple? */
2223 if (count != 0) nbytes = count;
2224
2225 /* Data comes in as words, so we have to enforce even byte counts. */
2226 if ((before | nbytes) & 1) return(EINVAL);
2227
2228 /* Which block on disk and how close to EOF? */
2229 if (cmp64(position, dv_size) >= 0) return(OK); /* At EOF */
2230 if (cmp64(add64ul(position, nbytes), dv_size) > 0)
2231 nbytes = diff64(dv_size, position);
2232
2233 nblocks = (before + nbytes + CD_SECTOR_SIZE - 1) / CD_SECTOR_SIZE;
2234 if (ATAPI_DEBUG) {
2235 printf("block=%lu, before=%u, nbytes=%u, nblocks=%u\n",
2236 block, before, nbytes, nblocks);
2237 }
2238
2239 /* First check to see if a reinitialization is needed. */
2240 if (!(wn->state & INITIALIZED) && w_specify() != OK) return(EIO);
2241
2242 /* Build an ATAPI command packet. */
2243 packet[0] = SCSI_READ10;
2244 packet[1] = 0;
2245 packet[2] = (block >> 24) & 0xFF;
2246 packet[3] = (block >> 16) & 0xFF;
2247 packet[4] = (block >> 8) & 0xFF;
2248 packet[5] = (block >> 0) & 0xFF;
2249 packet[6] = 0;
2250 packet[7] = (nblocks >> 8) & 0xFF;
2251 packet[8] = (nblocks >> 0) & 0xFF;
2252 packet[9] = 0;
2253 packet[10] = 0;
2254 packet[11] = 0;
2255
2256 /* Tell the controller to execute the packet command. */
2257 r = atapi_sendpacket(packet, nblocks * CD_SECTOR_SIZE);
2258 if (r != OK) goto err;
2259
2260 /* Read chunks of data. */
2261 while ((r = atapi_intr_wait()) > 0) {
2262 count = r;
2263
2264 if (ATAPI_DEBUG) {
2265 printf("before=%u, nbytes=%u, count=%u\n",
2266 before, nbytes, count);
2267 }
2268
2269 while (before > 0 && count > 0) { /* Discard before. */
2270 chunk = before;
2271 if (chunk > count) chunk = count;
2272 if (chunk > DMA_BUF_SIZE) chunk = DMA_BUF_SIZE;
2273 if ((s=sys_insw(wn->base_cmd + REG_DATA, SELF, tmp_buf, chunk)) != OK)
2274 panic(w_name(),"Call to sys_insw() failed", s);
2275 before -= chunk;
2276 count -= chunk;
2277 }
2278
2279 while (nbytes > 0 && count > 0) { /* Requested data. */
2280 chunk = nbytes;
2281 if (chunk > count) chunk = count;
2282 if (chunk > iov->iov_size) chunk = iov->iov_size;
2283 if(safe) {
2284 s=sys_safe_insw(wn->base_cmd + REG_DATA, proc_nr,
2285 (void *) iov->iov_addr, addr_offset, chunk);
2286 } else {
2287 s=sys_insw(wn->base_cmd + REG_DATA, proc_nr,
2288 (void *) (iov->iov_addr + addr_offset), chunk);
2289 }
2290 if (s != OK)
2291 panic(w_name(),"Call to sys_insw() failed", s);
2292 position= add64ul(position, chunk);
2293 nbytes -= chunk;
2294 count -= chunk;
2295 addr_offset += chunk;
2296 fresh = 0;
2297 if ((iov->iov_size -= chunk) == 0) {
2298 iov++;
2299 nr_req--;
2300 fresh = 1; /* new element is optional */
2301 addr_offset = 0;
2302 }
2303 }
2304
2305 while (count > 0) { /* Excess data. */
2306 chunk = count;
2307 if (chunk > DMA_BUF_SIZE) chunk = DMA_BUF_SIZE;
2308 if ((s=sys_insw(wn->base_cmd + REG_DATA, SELF, tmp_buf, chunk)) != OK)
2309 panic(w_name(),"Call to sys_insw() failed", s);
2310 count -= chunk;
2311 }
2312 }
2313
2314 if (r < 0) {
2315 err: /* Don't retry if too many errors. */
2316 if (atapi_debug) sense_request();
2317 if (++errors == max_errors) {
2318 w_command = CMD_IDLE;
2319 if (atapi_debug) printf("giving up (%d)\n", errors);
2320 return(EIO);
2321 }
2322 if (atapi_debug) printf("retry (%d)\n", errors);
2323 }
2324 }
2325
2326 w_command = CMD_IDLE;
2327 return(OK);
2328 }
2329
2330 /*===========================================================================*
2331 * atapi_sendpacket *
2332 *===========================================================================*/
2333 PRIVATE int atapi_sendpacket(packet, cnt)
2334 u8_t *packet;
2335 unsigned cnt;
2336 {
2337 /* Send an Atapi Packet Command */
2338 struct wini *wn = w_wn;
2339 pvb_pair_t outbyte[6]; /* vector for sys_voutb() */
2340 int s;
2341
2342 if (wn->state & IGNORING) return ERR;
2343
2344 /* Select Master/Slave drive */
2345 if ((s=sys_outb(wn->base_cmd + REG_DRIVE, wn->ldhpref)) != OK)
2346 panic(w_name(),"Couldn't select master/ slave drive",s);
2347
2348 if (!w_waitfor(STATUS_BSY | STATUS_DRQ, 0)) {
2349 printf("%s: atapi_sendpacket: drive not ready\n", w_name());
2350 return(ERR);
2351 }
2352
2353 /* Schedule a wakeup call, some controllers are flaky. This is done with
2354 * a synchronous alarm. If a timeout occurs a SYN_ALARM message is sent
2355 * from HARDWARE, so that w_intr_wait() can call w_timeout() in case the
2356 * controller was not able to execute the command. Leftover timeouts are
2357 * simply ignored by the main loop.
2358 */
2359 sys_setalarm(wakeup_ticks, 0);
2360
2361 #if _WORD_SIZE > 2
2362 if (cnt > 0xFFFE) cnt = 0xFFFE; /* Max data per interrupt. */
2363 #endif
2364
2365 w_command = ATAPI_PACKETCMD;
2366 pv_set(outbyte[0], wn->base_cmd + REG_FEAT, 0);
2367 pv_set(outbyte[1], wn->base_cmd + REG_IRR, 0);
2368 pv_set(outbyte[2], wn->base_cmd + REG_SAMTAG, 0);
2369 pv_set(outbyte[3], wn->base_cmd + REG_CNT_LO, (cnt >> 0) & 0xFF);
2370 pv_set(outbyte[4], wn->base_cmd + REG_CNT_HI, (cnt >> 8) & 0xFF);
2371 pv_set(outbyte[5], wn->base_cmd + REG_COMMAND, w_command);
2372 if (atapi_debug) printf("cmd: %x ", w_command);
2373 if ((s=sys_voutb(outbyte,6)) != OK)
2374 panic(w_name(),"Couldn't write registers with sys_voutb()",s);
2375
2376 if (!w_waitfor(STATUS_BSY | STATUS_DRQ, STATUS_DRQ)) {
2377 printf("%s: timeout (BSY|DRQ -> DRQ)\n", w_name());
2378 return(ERR);
2379 }
2380 wn->w_status |= STATUS_ADMBSY; /* Command not at all done yet. */
2381
2382 /* Send the command packet to the device. */
2383 if ((s=sys_outsw(wn->base_cmd + REG_DATA, SELF, packet, ATAPI_PACKETSIZE)) != OK)
2384 panic(w_name(),"sys_outsw() failed", s);
2385
2386 {
2387 int p;
2388 if (atapi_debug) {
2389 printf("sent command:");
2390 for(p = 0; p < ATAPI_PACKETSIZE; p++) { printf(" %02x", packet[p]); }
2391 printf("\n");
2392 }
2393 }
2394 return(OK);
2395 }
2396
2397
2398 #endif /* ENABLE_ATAPI */
2399
2400 /*===========================================================================*
2401 * w_other *
2402 *===========================================================================*/
2403 PRIVATE int w_other(dr, m, safe)
2404 struct driver *dr;
2405 message *m;
2406 int safe;
2407 {
2408 int r, timeout, prev;
2409
2410 if (m->m_type != DEV_IOCTL_S )
2411 return EINVAL;
2412
2413 if (m->REQUEST == DIOCTIMEOUT) {
2414 if(safe) {
2415 r= sys_safecopyfrom(m->IO_ENDPT, (vir_bytes) m->IO_GRANT,
2416 0, (vir_bytes)&timeout, sizeof(timeout), D);
2417 } else {
2418 r= sys_datacopy(m->IO_ENDPT, (vir_bytes)m->ADDRESS,
2419 SELF, (vir_bytes)&timeout, sizeof(timeout));
2420 }
2421
2422 if(r != OK)
2423 return r;
2424
2425 if (timeout == 0) {
2426 /* Restore defaults. */
2427 timeout_ticks = DEF_TIMEOUT_TICKS;
2428 max_errors = MAX_ERRORS;
2429 wakeup_ticks = WAKEUP_TICKS;
2430 w_silent = 0;
2431 } else if (timeout < 0) {
2432 return EINVAL;
2433 } else {
2434 prev = wakeup_ticks;
2435
2436 if (!w_standard_timeouts) {
2437 /* Set (lower) timeout, lower error
2438 * tolerance and set silent mode.
2439 */
2440 wakeup_ticks = timeout;
2441 max_errors = 3;
2442 w_silent = 1;
2443
2444 if (timeout_ticks > timeout)
2445 timeout_ticks = timeout;
2446 }
2447
2448 if(safe) {
2449 r= sys_safecopyto(m->IO_ENDPT,
2450 (vir_bytes) m->IO_GRANT,
2451 0, (vir_bytes)&prev, sizeof(prev), D);
2452 } else {
2453 r=sys_datacopy(SELF, (vir_bytes)&prev,
2454 m->IO_ENDPT, (vir_bytes)m->ADDRESS,
2455 sizeof(prev));
2456 }
2457
2458 if(r != OK)
2459 return r;
2460 }
2461
2462 return OK;
2463 } else if (m->REQUEST == DIOCOPENCT) {
2464 int count;
2465 if (w_prepare(m->DEVICE) == NIL_DEV) return ENXIO;
2466 count = w_wn->open_ct;
2467 if(safe) {
2468 r= sys_safecopyto(m->IO_ENDPT, (vir_bytes) m->IO_GRANT,
2469 0, (vir_bytes)&count, sizeof(count), D);
2470 } else {
2471 r=sys_datacopy(SELF, (vir_bytes)&count,
2472 m->IO_ENDPT, (vir_bytes)m->ADDRESS, sizeof(count));
2473 }
2474
2475 if(r != OK)
2476 return r;
2477
2478 return OK;
2479 }
2480 return EINVAL;
2481 }
2482
2483 /*===========================================================================*
2484 * w_hw_int *
2485 *===========================================================================*/
2486 PRIVATE int w_hw_int(dr, m)
2487 struct driver *dr;
2488 message *m;
2489 {
2490 /* Leftover interrupt(s) received; ack it/them. */
2491 ack_irqs(m->NOTIFY_ARG);
2492
2493 return OK;
2494 }
2495
2496
2497 /*===========================================================================*
2498 * ack_irqs *
2499 *===========================================================================*/
2500 PRIVATE void ack_irqs(unsigned int irqs)
2501 {
2502 unsigned int drive;
2503 unsigned long w_status;
2504
2505 for (drive = 0; drive < MAX_DRIVES && irqs; drive++) {
2506 if (!(wini[drive].state & IGNORING) && wini[drive].irq_need_ack &&
2507 (wini[drive].irq_mask & irqs)) {
2508 if (sys_inb((wini[drive].base_cmd + REG_STATUS),
2509 &w_status) != OK)
2510 {
2511 panic(w_name(), "couldn't ack irq on drive %d\n",
2512 drive);
2513 }
2514 wini[drive].w_status= w_status;
2515 if (sys_irqenable(&wini[drive].irq_hook_id) != OK)
2516 printf("couldn't re-enable drive %d\n", drive);
2517 irqs &= ~wini[drive].irq_mask;
2518 }
2519 }
2520 }
2521
2522
2523 #define STSTR(a) if (status & STATUS_ ## a) { strcat(str, #a); strcat(str, " "); }
2524 #define ERRSTR(a) if (e & ERROR_ ## a) { strcat(str, #a); strcat(str, " "); }
2525 char *strstatus(int status)
2526 {
2527 static char str[200];
2528 str[0] = '\0';
2529
2530 STSTR(BSY);
2531 STSTR(DRDY);
2532 STSTR(DMADF);
2533 STSTR(SRVCDSC);
2534 STSTR(DRQ);
2535 STSTR(CORR);
2536 STSTR(CHECK);
2537 return str;
2538 }
2539
2540 char *strerr(int e)
2541 {
2542 static char str[200];
2543 str[0] = '\0';
2544
2545 ERRSTR(BB);
2546 ERRSTR(ECC);
2547 ERRSTR(ID);
2548 ERRSTR(AC);
2549 ERRSTR(TK);
2550 ERRSTR(DM);
2551
2552 return str;
2553 }
2554
2555 #if ENABLE_ATAPI
2556
2557 /*===========================================================================*
2558 * atapi_intr_wait *
2559 *===========================================================================*/
2560 PRIVATE int atapi_intr_wait()
2561 {
2562 /* Wait for an interrupt and study the results. Returns a number of bytes
2563 * that need to be transferred, or an error code.
2564 */
2565 struct wini *wn = w_wn;
2566 pvb_pair_t inbyte[4]; /* vector for sys_vinb() */
2567 int s; /* status for sys_vinb() */
2568 int e;
2569 int len;
2570 int irr;
2571 int r;
2572 int phase;
2573
2574 w_intr_wait();
2575
2576 /* Request series of device I/O. */
2577 inbyte[0].port = wn->base_cmd + REG_ERROR;
2578 inbyte[1].port = wn->base_cmd + REG_CNT_LO;
2579 inbyte[2].port = wn->base_cmd + REG_CNT_HI;
2580 inbyte[3].port = wn->base_cmd + REG_IRR;
2581 if ((s=sys_vinb(inbyte, 4)) != OK)
2582 panic(w_name(),"ATAPI failed sys_vinb()", s);
2583 e = inbyte[0].value;
2584 len = inbyte[1].value;
2585 len |= inbyte[2].value << 8;
2586 irr = inbyte[3].value;
2587
2588 #if ATAPI_DEBUG
2589 printf("wn %p S=%x=%s E=%02x=%s L=%04x I=%02x\n", wn, wn->w_status, strstatus(wn->w_status), e, strerr(e), len, irr);
2590 #endif
2591 if (wn->w_status & (STATUS_BSY | STATUS_CHECK)) {
2592 if (atapi_debug) {
2593 printf("atapi fail: S=%x=%s E=%02x=%s L=%04x I=%02x\n", wn->w_status, strstatus(wn->w_status), e, strerr(e), len, irr);
2594 }
2595 return ERR;
2596 }
2597
2598 phase = (wn->w_status & STATUS_DRQ) | (irr & (IRR_COD | IRR_IO));
2599
2600 switch (phase) {
2601 case IRR_COD | IRR_IO:
2602 if (ATAPI_DEBUG) printf("ACD: Phase Command Complete\n");
2603 r = OK;
2604 break;
2605 case 0:
2606 if (ATAPI_DEBUG) printf("ACD: Phase Command Aborted\n");
2607 r = ERR;
2608 break;
2609 case STATUS_DRQ | IRR_COD:
2610 if (ATAPI_DEBUG) printf("ACD: Phase Command Out\n");
2611 r = ERR;
2612 break;
2613 case STATUS_DRQ:
2614 if (ATAPI_DEBUG) printf("ACD: Phase Data Out %d\n", len);
2615 r = len;
2616 break;
2617 case STATUS_DRQ | IRR_IO:
2618 if (ATAPI_DEBUG) printf("ACD: Phase Data In %d\n", len);
2619 r = len;
2620 break;
2621 default:
2622 if (ATAPI_DEBUG) printf("ACD: Phase Unknown\n");
2623 r = ERR;
2624 break;
2625 }
2626
2627 #if 0
2628 /* retry if the media changed */
2629 XXX while (phase == (IRR_IO | IRR_COD) && (wn->w_status & STATUS_CHECK)
2630 && (e & ERROR_SENSE) == SENSE_UATTN && --try > 0);
2631 #endif
2632
2633 wn->w_status |= STATUS_ADMBSY; /* Assume not done yet. */
2634 return(r);
2635 }
2636
2637 #endif /* ENABLE_ATAPI */
2638
2639 #undef panic
2640
2641 PRIVATE void at_panic(line, h, msg, n)
2642 int line;
2643 char *h;
2644 char *msg;
2645 int n;
2646 {
2647 printf("at_wini%d: panic at line %d: ", w_instance, line);
2648 panic(h, msg, n);
2649 }
2650
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