kernel/arch/earm/bsp/ti/omap_intr.c

   1 #include <sys/types.h>
   2 #include <machine/cpu.h>
   3 #include <minix/type.h>
   4 #include <minix/board.h>
   5 #include <io.h>
   6
   7 #include "kernel/kernel.h"
   8 #include "kernel/proc.h"
   9 #include "kernel/vm.h"
  10 #include "kernel/proto.h"
  11 #include "arch_proto.h"
  12 #include "hw_intr.h"
  13
  14 #include "omap_intr_registers.h"
  15 static struct omap_intr
  16 {
  17         vir_bytes base;
  18         int size;
  19 } omap_intr;
  20
  21 static kern_phys_map intr_phys_map;
  22
  23 int
  24 intr_init(const int auto_eoi)
  25 {
  26         if (BOARD_IS_BBXM(machine.board_id)) {
  27                 omap_intr.base = OMAP3_DM37XX_INTR_BASE;
  28         } else if (BOARD_IS_BB(machine.board_id)) {
  29                 omap_intr.base = OMAP3_AM335X_INTR_BASE;
  30         } else {
  31                 panic
  32                     ("Can not do the interrupt setup. machine (0x%08x) is unknown\n",
  33                     machine.board_id);
  34         };
  35         omap_intr.size = 0x1000;        /* 4K */
  36
  37         kern_phys_map_ptr(omap_intr.base, omap_intr.size,
  38             VMMF_UNCACHED | VMMF_WRITE,
  39             &intr_phys_map, (vir_bytes) & omap_intr.base);
  40         return 0;
  41 }
  42
  43 void
  44 bsp_irq_handle(void)
  45 {
  46         /* Function called from assembly to handle interrupts */
  47
  48         /* get irq */
  49         int irq =
  50             mmio_read(omap_intr.base +
  51             OMAP3_INTCPS_SIR_IRQ) & OMAP3_INTR_ACTIVEIRQ_MASK;
  52         /* handle irq */
  53         irq_handle(irq);
  54         /* re-enable. this should not trigger interrupts due to current cpsr
  55          * state */
  56         mmio_write(omap_intr.base + OMAP3_INTCPS_CONTROL,
  57             OMAP3_INTR_NEWIRQAGR);
  58 }
  59
  60 void
  61 bsp_irq_unmask(int irq)
  62 {
  63         mmio_write(OMAP3_INTR_MIR_CLEAR(omap_intr.base, irq >> 5),
  64             1 << (irq & 0x1f));
  65 }
  66
  67 void
  68 bsp_irq_mask(const int irq)
  69 {
  70         mmio_write(OMAP3_INTR_MIR_SET(omap_intr.base, irq >> 5),
  71             1 << (irq & 0x1f));
  72 }