kernel/arch/i386/serial.h

   1
   2 #ifndef _KERN_SERIAL_H
   3 #define _KERN_SERIAL_H 1
   4
   5 #define THRREG  0       /* transmitter holding, write-only, DLAB must be clear */
   6 #define RBRREG  0       /* receiver buffer, read-only, DLAB must be clear */
   7 #define DLLREG  0       /* divisor latch LSB, read/write, DLAB must be set */
   8 #define DLMREG  1       /* divisor latch MSB, read/write, DLAB must be set */
   9 #define FICRREG 2       /* FIFO control, write-only */
  10 #define LCRREG  3       /* line control, read/write */
  11 #define LSRREG  5       /* line status, read-only */
  12 #define SPRREG  7
  13
  14 #define COM1_BASE       0x3F8
  15 #define COM1_THR        (COM1_BASE + THRREG)
  16 #define COM1_RBR        (COM1_BASE + RBRREG)
  17 #define COM1_DLL        (COM1_BASE + DLLREG)
  18 #define COM1_DLM        (COM1_BASE + DLMREG)
  19 #define COM1_LCR        (COM1_BASE + LCRREG)
  20 #define         LCR_5BIT        0x00 /* 5 bits per data word */
  21 #define         LCR_6BIT        0x01 /* 6 bits per data word */
  22 #define         LCR_7BIT        0x02 /* 7 bits per data word */
  23 #define         LCR_8BIT        0x03 /* 8 bits per data word */
  24 #define         LCR_1STOP       0x00 /* 1/1.5 stop bits */
  25 #define         LCR_2STOP       0x04 /* 2 stop bits */
  26 #define         LCR_NPAR        0x00 /* no parity */
  27 #define         LCR_OPAR        0x08 /* odd parity */
  28 #define         LCR_EPAR        0x18 /* even parity */
  29 #define         LCR_BREAK       0x40 /* enable break */
  30 #define         LCR_DLAB        0x80 /* access DLAB registers */
  31 #define COM1_LSR        (COM1_BASE + LSRREG)
  32 #define         LSR_DR          0x01
  33 #define         LSR_THRE        0x20
  34 #define         LCR_DLA         0x80
  35
  36 #define UART_BASE_FREQ  115200U
  37
  38 #endif