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Retired DEV_{READ,WRITE,GATHER,SCATTER,IOCTL} (safe versions *_S are to
[minix3.git] / drivers / at_wini / at_wini.c
blob7b68446d464d32f6166e0f56e47edd3bcb277d60
1 /* This file contains the device dependent part of a driver for the IBM-AT
2 * winchester controller. Written by Adri Koppes.
3 *
4 * The file contains one entry point:
5 *
6 * at_winchester_task: main entry when system is brought up
7 *
8 * Changes:
9 * Aug 19, 2005 ATA PCI support, supports SATA (Ben Gras)
10 * Nov 18, 2004 moved AT disk driver to user-space (Jorrit N. Herder)
11 * Aug 20, 2004 watchdogs replaced by sync alarms (Jorrit N. Herder)
12 * Mar 23, 2000 added ATAPI CDROM support (Michael Temari)
13 * May 14, 2000 d-d/i rewrite (Kees J. Bot)
14 * Apr 13, 1992 device dependent/independent split (Kees J. Bot)
15 */
16
17 #include "at_wini.h"
18
19 #include <minix/sysutil.h>
20 #include <minix/keymap.h>
21 #include <sys/ioc_disk.h>
22 #include <ibm/pci.h>
23
24 #define ATAPI_DEBUG 0 /* To debug ATAPI code. */
25
26 /* I/O Ports used by winchester disk controllers. */
27
28 /* Read and write registers */
29 #define REG_CMD_BASE0 0x1F0 /* command base register of controller 0 */
30 #define REG_CMD_BASE1 0x170 /* command base register of controller 1 */
31 #define REG_CTL_BASE0 0x3F6 /* control base register of controller 0 */
32 #define REG_CTL_BASE1 0x376 /* control base register of controller 1 */
33
34 #define PCI_CTL_OFF 2 /* Offset of control registers from BAR2 */
35 #define PCI_DMA_2ND_OFF 8 /* Offset of DMA registers from BAR4 for
36 * secondary channel
37 */
38
39 #define REG_DATA 0 /* data register (offset from the base reg.) */
40 #define REG_PRECOMP 1 /* start of write precompensation */
41 #define REG_COUNT 2 /* sectors to transfer */
42 #define REG_SECTOR 3 /* sector number */
43 #define REG_CYL_LO 4 /* low byte of cylinder number */
44 #define REG_CYL_HI 5 /* high byte of cylinder number */
45 #define REG_LDH 6 /* lba, drive and head */
46 #define LDH_DEFAULT 0xA0 /* ECC enable, 512 bytes per sector */
47 #define LDH_LBA 0x40 /* Use LBA addressing */
48 #define LDH_DEV 0x10 /* Drive 1 iff set */
49 #define ldh_init(drive) (LDH_DEFAULT | ((drive) << 4))
50
51 /* Read only registers */
52 #define REG_STATUS 7 /* status */
53 #define STATUS_BSY 0x80 /* controller busy */
54 #define STATUS_RDY 0x40 /* drive ready */
55 #define STATUS_WF 0x20 /* write fault */
56 #define STATUS_SC 0x10 /* seek complete (obsolete) */
57 #define STATUS_DRQ 0x08 /* data transfer request */
58 #define STATUS_CRD 0x04 /* corrected data */
59 #define STATUS_IDX 0x02 /* index pulse */
60 #define STATUS_ERR 0x01 /* error */
61 #define STATUS_ADMBSY 0x100 /* administratively busy (software) */
62 #define REG_ERROR 1 /* error code */
63 #define ERROR_BB 0x80 /* bad block */
64 #define ERROR_ECC 0x40 /* bad ecc bytes */
65 #define ERROR_ID 0x10 /* id not found */
66 #define ERROR_AC 0x04 /* aborted command */
67 #define ERROR_TK 0x02 /* track zero error */
68 #define ERROR_DM 0x01 /* no data address mark */
69
70 /* Write only registers */
71 #define REG_COMMAND 7 /* command */
72 #define CMD_IDLE 0x00 /* for w_command: drive idle */
73 #define CMD_RECALIBRATE 0x10 /* recalibrate drive */
74 #define CMD_READ 0x20 /* read data */
75 #define CMD_READ_EXT 0x24 /* read data (LBA48 addressed) */
76 #define CMD_READ_DMA_EXT 0x25 /* read data using DMA (w/ LBA48) */
77 #define CMD_WRITE 0x30 /* write data */
78 #define CMD_WRITE_EXT 0x34 /* write data (LBA48 addressed) */
79 #define CMD_WRITE_DMA_EXT 0x35 /* write data using DMA (w/ LBA48) */
80 #define CMD_READVERIFY 0x40 /* read verify */
81 #define CMD_FORMAT 0x50 /* format track */
82 #define CMD_SEEK 0x70 /* seek cylinder */
83 #define CMD_DIAG 0x90 /* execute device diagnostics */
84 #define CMD_SPECIFY 0x91 /* specify parameters */
85 #define CMD_READ_DMA 0xC8 /* read data using DMA */
86 #define CMD_WRITE_DMA 0xCA /* write data using DMA */
87 #define ATA_IDENTIFY 0xEC /* identify drive */
88 /* #define REG_CTL 0x206 */ /* control register */
89 #define REG_CTL 0 /* control register */
90 #define CTL_NORETRY 0x80 /* disable access retry */
91 #define CTL_NOECC 0x40 /* disable ecc retry */
92 #define CTL_EIGHTHEADS 0x08 /* more than eight heads */
93 #define CTL_RESET 0x04 /* reset controller */
94 #define CTL_INTDISABLE 0x02 /* disable interrupts */
95 #define REG_CTL_ALTSTAT 0 /* alternate status register */
96
97 /* Identify words */
98 #define ID_GENERAL 0x00 /* General configuration information */
99 #define ID_GEN_NOT_ATA 0x8000 /* Not an ATA device */
100 #define ID_CAPABILITIES 0x31 /* Capabilities (49)*/
101 #define ID_CAP_LBA 0x0200 /* LBA supported */
102 #define ID_CAP_DMA 0x0100 /* DMA supported */
103 #define ID_FIELD_VALIDITY 0x35 /* Field Validity (53) */
104 #define ID_FV_88 0x04 /* Word 88 is valid (UDMA) */
105 #define ID_MULTIWORD_DMA 0x3f /* Multiword DMA (63) */
106 #define ID_MWDMA_2_SEL 0x0400 /* Mode 2 is selected */
107 #define ID_MWDMA_1_SEL 0x0200 /* Mode 1 is selected */
108 #define ID_MWDMA_0_SEL 0x0100 /* Mode 0 is selected */
109 #define ID_MWDMA_2_SUP 0x0004 /* Mode 2 is supported */
110 #define ID_MWDMA_1_SUP 0x0002 /* Mode 1 is supported */
111 #define ID_MWDMA_0_SUP 0x0001 /* Mode 0 is supported */
112 #define ID_CSS 0x53 /* Command Sets Supported (83) */
113 #define ID_CSS_LBA48 0x0400
114 #define ID_ULTRA_DMA 0x58 /* Ultra DMA (88) */
115 #define ID_UDMA_5_SEL 0x2000 /* Mode 5 is selected */
116 #define ID_UDMA_4_SEL 0x1000 /* Mode 4 is selected */
117 #define ID_UDMA_3_SEL 0x0800 /* Mode 3 is selected */
118 #define ID_UDMA_2_SEL 0x0400 /* Mode 2 is selected */
119 #define ID_UDMA_1_SEL 0x0200 /* Mode 1 is selected */
120 #define ID_UDMA_0_SEL 0x0100 /* Mode 0 is selected */
121 #define ID_UDMA_5_SUP 0x0020 /* Mode 5 is supported */
122 #define ID_UDMA_4_SUP 0x0010 /* Mode 4 is supported */
123 #define ID_UDMA_3_SUP 0x0008 /* Mode 3 is supported */
124 #define ID_UDMA_2_SUP 0x0004 /* Mode 2 is supported */
125 #define ID_UDMA_1_SUP 0x0002 /* Mode 1 is supported */
126 #define ID_UDMA_0_SUP 0x0001 /* Mode 0 is supported */
127
128 /* DMA registers */
129 #define DMA_COMMAND 0 /* Command register */
130 #define DMA_CMD_WRITE 0x08 /* PCI bus master writes */
131 #define DMA_CMD_START 0x01 /* Start Bus Master */
132 #define DMA_STATUS 2 /* Status register */
133 #define DMA_ST_D1_DMACAP 0x40 /* Drive 1 is DMA capable */
134 #define DMA_ST_D0_DMACAP 0x20 /* Drive 0 is DMA capable */
135 #define DMA_ST_INT 0x04 /* Interrupt */
136 #define DMA_ST_ERROR 0x02 /* Error */
137 #define DMA_ST_BM_ACTIVE 0x01 /* Bus Master IDE Active */
138 #define DMA_PRDTP 4 /* PRD Table Pointer */
139
140 /* Check for the presence of LBA48 only on drives that are 'big'. */
141 #define LBA48_CHECK_SIZE 0x0f000000
142 #define LBA_MAX_SIZE 0x0fffffff /* Highest sector size for
143 * regular LBA.
144 */
145
146 #if ENABLE_ATAPI
147 #define ERROR_SENSE 0xF0 /* sense key mask */
148 #define SENSE_NONE 0x00 /* no sense key */
149 #define SENSE_RECERR 0x10 /* recovered error */
150 #define SENSE_NOTRDY 0x20 /* not ready */
151 #define SENSE_MEDERR 0x30 /* medium error */
152 #define SENSE_HRDERR 0x40 /* hardware error */
153 #define SENSE_ILRQST 0x50 /* illegal request */
154 #define SENSE_UATTN 0x60 /* unit attention */
155 #define SENSE_DPROT 0x70 /* data protect */
156 #define SENSE_ABRT 0xb0 /* aborted command */
157 #define SENSE_MISCOM 0xe0 /* miscompare */
158 #define ERROR_MCR 0x08 /* media change requested */
159 #define ERROR_ABRT 0x04 /* aborted command */
160 #define ERROR_EOM 0x02 /* end of media detected */
161 #define ERROR_ILI 0x01 /* illegal length indication */
162 #define REG_FEAT 1 /* features */
163 #define FEAT_OVERLAP 0x02 /* overlap */
164 #define FEAT_DMA 0x01 /* dma */
165 #define REG_IRR 2 /* interrupt reason register */
166 #define IRR_REL 0x04 /* release */
167 #define IRR_IO 0x02 /* direction for xfer */
168 #define IRR_COD 0x01 /* command or data */
169 #define REG_SAMTAG 3
170 #define REG_CNT_LO 4 /* low byte of cylinder number */
171 #define REG_CNT_HI 5 /* high byte of cylinder number */
172 #define REG_DRIVE 6 /* drive select */
173 #endif
174
175 #define REG_STATUS 7 /* status */
176 #define STATUS_BSY 0x80 /* controller busy */
177 #define STATUS_DRDY 0x40 /* drive ready */
178 #define STATUS_DMADF 0x20 /* dma ready/drive fault */
179 #define STATUS_SRVCDSC 0x10 /* service or dsc */
180 #define STATUS_DRQ 0x08 /* data transfer request */
181 #define STATUS_CORR 0x04 /* correctable error occurred */
182 #define STATUS_CHECK 0x01 /* check error */
183
184 #ifdef ENABLE_ATAPI
185 #define ATAPI_PACKETCMD 0xA0 /* packet command */
186 #define ATAPI_IDENTIFY 0xA1 /* identify drive */
187 #define SCSI_READ10 0x28 /* read from disk */
188 #define SCSI_SENSE 0x03 /* sense request */
189
190 #define CD_SECTOR_SIZE 2048 /* sector size of a CD-ROM */
191 #endif /* ATAPI */
192
193 /* Interrupt request lines. */
194 #define NO_IRQ 0 /* no IRQ set yet */
195
196 #define ATAPI_PACKETSIZE 12
197 #define SENSE_PACKETSIZE 18
198
199 /* Common command block */
200 struct command {
201 u8_t precomp; /* REG_PRECOMP, etc. */
202 u8_t count;
203 u8_t sector;
204 u8_t cyl_lo;
205 u8_t cyl_hi;
206 u8_t ldh;
207 u8_t command;
208
209 /* The following at for LBA48 */
210 u8_t count_prev;
211 u8_t sector_prev;
212 u8_t cyl_lo_prev;
213 u8_t cyl_hi_prev;
214 };
215
216 /* Error codes */
217 #define ERR (-1) /* general error */
218 #define ERR_BAD_SECTOR (-2) /* block marked bad detected */
219
220 /* Some controllers don't interrupt, the clock will wake us up. */
221 #define WAKEUP (32*HZ) /* drive may be out for 31 seconds max */
222
223 /* Miscellaneous. */
224 #define MAX_DRIVES 8
225 #define COMPAT_DRIVES 4
226 #if _WORD_SIZE > 2
227 #define MAX_SECS 256 /* controller can transfer this many sectors */
228 #else
229 #define MAX_SECS 127 /* but not to a 16 bit process */
230 #endif
231 #define MAX_ERRORS 4 /* how often to try rd/wt before quitting */
232 #define NR_MINORS (MAX_DRIVES * DEV_PER_DRIVE)
233 #define SUB_PER_DRIVE (NR_PARTITIONS * NR_PARTITIONS)
234 #define NR_SUBDEVS (MAX_DRIVES * SUB_PER_DRIVE)
235 #define DELAY_USECS 1000 /* controller timeout in microseconds */
236 #define DELAY_TICKS 1 /* controller timeout in ticks */
237 #define DEF_TIMEOUT_TICKS 300 /* controller timeout in ticks */
238 #define RECOVERY_USECS 500000 /* controller recovery time in microseconds */
239 #define RECOVERY_TICKS 30 /* controller recovery time in ticks */
240 #define INITIALIZED 0x01 /* drive is initialized */
241 #define DEAF 0x02 /* controller must be reset */
242 #define SMART 0x04 /* drive supports ATA commands */
243 #if ENABLE_ATAPI
244 #define ATAPI 0x08 /* it is an ATAPI device */
245 #else
246 #define ATAPI 0 /* don't bother with ATAPI; optimise out */
247 #endif
248 #define IDENTIFIED 0x10 /* w_identify done successfully */
249 #define IGNORING 0x20 /* w_identify failed once */
250
251 /* Timeouts and max retries. */
252 int timeout_ticks = DEF_TIMEOUT_TICKS, max_errors = MAX_ERRORS;
253 int wakeup_ticks = WAKEUP;
254 long w_standard_timeouts = 0, w_pci_debug = 0, w_instance = 0,
255 disable_dma = 0, atapi_debug = 0;
256
257 int w_testing = 0, w_silent = 0;
258
259 int w_next_drive = 0;
260
261 /* Variables. */
262
263 /* The struct wini is indexed by controller first, then drive (0-3).
264 * Controller 0 is always the 'compatability' ide controller, at
265 * the fixed locations, whether present or not.
266 */
267 PRIVATE struct wini { /* main drive struct, one entry per drive */
268 unsigned state; /* drive state: deaf, initialized, dead */
269 unsigned short w_status; /* device status register */
270 unsigned base_cmd; /* command base register */
271 unsigned base_ctl; /* control base register */
272 unsigned base_dma; /* dma base register */
273 unsigned irq; /* interrupt request line */
274 unsigned irq_mask; /* 1 << irq */
275 unsigned irq_need_ack; /* irq needs to be acknowledged */
276 int irq_hook_id; /* id of irq hook at the kernel */
277 int lba48; /* supports lba48 */
278 int dma; /* supports dma */
279 unsigned lcylinders; /* logical number of cylinders (BIOS) */
280 unsigned lheads; /* logical number of heads */
281 unsigned lsectors; /* logical number of sectors per track */
282 unsigned pcylinders; /* physical number of cylinders (translated) */
283 unsigned pheads; /* physical number of heads */
284 unsigned psectors; /* physical number of sectors per track */
285 unsigned ldhpref; /* top four bytes of the LDH (head) register */
286 unsigned precomp; /* write precompensation cylinder / 4 */
287 unsigned max_count; /* max request for this drive */
288 unsigned open_ct; /* in-use count */
289 struct device part[DEV_PER_DRIVE]; /* disks and partitions */
290 struct device subpart[SUB_PER_DRIVE]; /* subpartitions */
291 } wini[MAX_DRIVES], *w_wn;
292
293 PRIVATE int w_device = -1;
294 PRIVATE int w_controller = -1;
295 PRIVATE int w_major = -1;
296 PRIVATE char w_id_string[40];
297
298 PRIVATE int win_tasknr; /* my task number */
299 PRIVATE int w_command; /* current command in execution */
300 PRIVATE u8_t w_byteval; /* used for SYS_IRQCTL */
301 PRIVATE int w_drive; /* selected drive */
302 PRIVATE int w_controller; /* selected controller */
303 PRIVATE struct device *w_dv; /* device's base and size */
304
305 /* Unfortunately, DMA_SECTORS and DMA_BUF_SIZE are already defined libdriver
306 * for 'tmp_buf'.
307 */
308 #define ATA_DMA_SECTORS 64
309 #define ATA_DMA_BUF_SIZE (ATA_DMA_SECTORS*SECTOR_SIZE)
310
311 PRIVATE char dma_buf[ATA_DMA_BUF_SIZE];
312 PRIVATE phys_bytes dma_buf_phys;
313
314 #define N_PRDTE 1024 /* Should be enough for large requests */
315
316 PRIVATE struct prdte
317 {
318 u32_t prdte_base;
319 u16_t prdte_count;
320 u8_t prdte_reserved;
321 u8_t prdte_flags;
322 } prdt[N_PRDTE];
323 PRIVATE phys_bytes prdt_phys;
324
325 #define PRDTE_FL_EOT 0x80 /* End of table */
326
327 /* Some IDE devices announce themselves as RAID controllers */
328 PRIVATE struct
329 {
330 u16_t vendor;
331 u16_t device;
332 } raid_table[]=
333 {
334 { 0x1106, 0x3149 }, /* VIA VT6420 */
335 { 0, 0 } /* end of list */
336 };
337
338 FORWARD _PROTOTYPE( void init_params, (void) );
339 FORWARD _PROTOTYPE( void init_drive, (struct wini *w, int base_cmd,
340 int base_ctl, int base_dma, int irq, int ack, int hook,
341 int drive) );
342 FORWARD _PROTOTYPE( void init_params_pci, (int) );
343 FORWARD _PROTOTYPE( int w_do_open, (struct driver *dp, message *m_ptr) );
344 FORWARD _PROTOTYPE( struct device *w_prepare, (int dev) );
345 FORWARD _PROTOTYPE( int w_identify, (void) );
346 FORWARD _PROTOTYPE( char *w_name, (void) );
347 FORWARD _PROTOTYPE( int w_specify, (void) );
348 FORWARD _PROTOTYPE( int w_io_test, (void) );
349 FORWARD _PROTOTYPE( int w_transfer, (int proc_nr, int opcode, u64_t position,
350 iovec_t *iov, unsigned nr_req, int safe));
351 FORWARD _PROTOTYPE( int com_out, (struct command *cmd) );
352 FORWARD _PROTOTYPE( int com_out_ext, (struct command *cmd) );
353 FORWARD _PROTOTYPE( void setup_dma, (unsigned *sizep, int proc_nr,
354 iovec_t *iov, int do_write, int *do_copyoutp, int safe) );
355 FORWARD _PROTOTYPE( void w_need_reset, (void) );
356 FORWARD _PROTOTYPE( void ack_irqs, (unsigned int) );
357 FORWARD _PROTOTYPE( int w_do_close, (struct driver *dp, message *m_ptr) );
358 FORWARD _PROTOTYPE( int w_other, (struct driver *dp, message *m_ptr, int));
359 FORWARD _PROTOTYPE( int w_hw_int, (struct driver *dp, message *m_ptr) );
360 FORWARD _PROTOTYPE( int com_simple, (struct command *cmd) );
361 FORWARD _PROTOTYPE( void w_timeout, (void) );
362 FORWARD _PROTOTYPE( int w_reset, (void) );
363 FORWARD _PROTOTYPE( void w_intr_wait, (void) );
364 FORWARD _PROTOTYPE( int at_intr_wait, (void) );
365 FORWARD _PROTOTYPE( int w_waitfor, (int mask, int value) );
366 FORWARD _PROTOTYPE( int w_waitfor_dma, (int mask, int value) );
367 FORWARD _PROTOTYPE( void w_geometry, (struct partition *entry) );
368 #if ENABLE_ATAPI
369 FORWARD _PROTOTYPE( int atapi_sendpacket, (u8_t *packet, unsigned cnt) );
370 FORWARD _PROTOTYPE( int atapi_intr_wait, (void) );
371 FORWARD _PROTOTYPE( int atapi_open, (void) );
372 FORWARD _PROTOTYPE( void atapi_close, (void) );
373 FORWARD _PROTOTYPE( int atapi_transfer, (int proc_nr, int opcode,
374 u64_t position, iovec_t *iov, unsigned nr_req, int safe));
375 #endif
376
377 /* Entry points to this driver. */
378 PRIVATE struct driver w_dtab = {
379 w_name, /* current device's name */
380 w_do_open, /* open or mount request, initialize device */
381 w_do_close, /* release device */
382 do_diocntl, /* get or set a partition's geometry */
383 w_prepare, /* prepare for I/O on a given minor device */
384 w_transfer, /* do the I/O */
385 nop_cleanup, /* nothing to clean up */
386 w_geometry, /* tell the geometry of the disk */
387 nop_signal, /* no cleanup needed on shutdown */
388 nop_alarm, /* ignore leftover alarms */
389 nop_cancel, /* ignore CANCELs */
390 nop_select, /* ignore selects */
391 w_other, /* catch-all for unrecognized commands and ioctls */
392 w_hw_int /* leftover hardware interrupts */
393 };
394
395 /*===========================================================================*
396 * at_winchester_task *
397 *===========================================================================*/
398 PUBLIC int main()
399 {
400 /* Install signal handlers. Ask PM to transform signal into message. */
401 struct sigaction sa;
402
403 sa.sa_handler = SIG_MESS;
404 sigemptyset(&sa.sa_mask);
405 sa.sa_flags = 0;
406 if (sigaction(SIGTERM,&sa,NULL)<0) panic("AT","sigaction failed", errno);
407
408 /* Set special disk parameters then call the generic main loop. */
409 init_params();
410 signal(SIGTERM, SIG_IGN);
411 driver_task(&w_dtab);
412 return(OK);
413 }
414
415 /*===========================================================================*
416 * init_params *
417 *===========================================================================*/
418 PRIVATE void init_params()
419 {
420 /* This routine is called at startup to initialize the drive parameters. */
421
422 u16_t parv[2];
423 unsigned int vector, size;
424 int drive, nr_drives;
425 struct wini *wn;
426 u8_t params[16];
427 int s;
428
429 /* Boot variables. */
430 env_parse("ata_std_timeout", "d", 0, &w_standard_timeouts, 0, 1);
431 env_parse("ata_pci_debug", "d", 0, &w_pci_debug, 0, 1);
432 env_parse("ata_instance", "d", 0, &w_instance, 0, 8);
433 env_parse("ata_no_dma", "d", 0, &disable_dma, 0, 1);
434 env_parse("atapi_debug", "d", 0, &atapi_debug, 0, 1);
435
436 if (disable_dma)
437 printf("DMA for ATA devices is disabled.\n");
438
439 s= sys_umap(SELF, D, (vir_bytes)dma_buf, sizeof(dma_buf), &dma_buf_phys);
440 if (s != 0)
441 panic("at_wini", "can't map dma buffer", s);
442
443 s= sys_umap(SELF, D, (vir_bytes)prdt, sizeof(prdt), &prdt_phys);
444 if (s != 0)
445 panic("at_wini", "can't map prd table", s);
446
447 if (w_instance == 0) {
448 /* Get the number of drives from the BIOS data area */
449 s=sys_readbios(NR_HD_DRIVES_ADDR, params, NR_HD_DRIVES_SIZE);
450 if (s != OK)
451 panic(w_name(), "Couldn't read BIOS", s);
452 if ((nr_drives = params[0]) > 2) nr_drives = 2;
453
454 for (drive = 0, wn = wini; drive < COMPAT_DRIVES; drive++, wn++) {
455 if (drive < nr_drives) {
456 /* Copy the BIOS parameter vector */
457 vector = (drive == 0) ? BIOS_HD0_PARAMS_ADDR :
458 BIOS_HD1_PARAMS_ADDR;
459 size = (drive == 0) ? BIOS_HD0_PARAMS_SIZE :
460 BIOS_HD1_PARAMS_SIZE;
461 s=sys_readbios(vector, parv, size);
462 if (s != OK)
463 panic(w_name(), "Couldn't read BIOS", s);
464
465 /* Calculate the address of the parameters and copy them */
466 s=sys_readbios(hclick_to_physb(parv[1]) + parv[0],
467 params, 16L);
468 if (s != OK)
469 panic(w_name(),"Couldn't copy parameters", s);
470
471 /* Copy the parameters to the structures of the drive */
472 wn->lcylinders = bp_cylinders(params);
473 wn->lheads = bp_heads(params);
474 wn->lsectors = bp_sectors(params);
475 wn->precomp = bp_precomp(params) >> 2;
476 }
477
478 /* Fill in non-BIOS parameters. */
479 init_drive(wn,
480 drive < 2 ? REG_CMD_BASE0 : REG_CMD_BASE1,
481 drive < 2 ? REG_CTL_BASE0 : REG_CTL_BASE1,
482 0 /* no DMA */, NO_IRQ, 0, 0, drive);
483 w_next_drive++;
484 }
485 }
486
487 /* Look for controllers on the pci bus. Skip none the first instance,
488 * skip one and then 2 for every instance, for every next instance.
489 */
490 if (w_instance == 0)
491 init_params_pci(0);
492 else
493 init_params_pci(w_instance*2-1);
494
495 }
496
497 #define ATA_IF_NOTCOMPAT1 (1L << 0)
498 #define ATA_IF_NOTCOMPAT2 (1L << 2)
499
500 /*===========================================================================*
501 * init_drive *
502 *===========================================================================*/
503 PRIVATE void init_drive(struct wini *w, int base_cmd, int base_ctl,
504 int base_dma, int irq, int ack, int hook, int drive)
505 {
506 w->state = 0;
507 w->w_status = 0;
508 w->base_cmd = base_cmd;
509 w->base_ctl = base_ctl;
510 w->base_dma = base_dma;
511 w->irq = irq;
512 w->irq_mask = 1 << irq;
513 w->irq_need_ack = ack;
514 w->irq_hook_id = hook;
515 w->ldhpref = ldh_init(drive);
516 w->max_count = MAX_SECS << SECTOR_SHIFT;
517 w->lba48 = 0;
518 w->dma = 0;
519 }
520
521 /*===========================================================================*
522 * init_params_pci *
523 *===========================================================================*/
524 PRIVATE void init_params_pci(int skip)
525 {
526 int i, r, devind, drive;
527 int irq, irq_hook, raid;
528 u8_t bcr, scr, interface;
529 u16_t vid, did;
530 u32_t base_dma, t3;
531
532 pci_init();
533 for(drive = w_next_drive; drive < MAX_DRIVES; drive++)
534 wini[drive].state = IGNORING;
535 for(r = pci_first_dev(&devind, &vid, &did); r != 0;
536 r = pci_next_dev(&devind, &vid, &did)) {
537
538 raid= 0;
539
540 /* Except class 01h (mass storage), subclass be 01h (ATA).
541 * Also check listed RAID controllers.
542 */
543 bcr= pci_attr_r8(devind, PCI_BCR);
544 scr= pci_attr_r8(devind, PCI_SCR);
545 interface= pci_attr_r8(devind, PCI_PIFR);
546 t3= ((bcr << 16) | (scr << 8) | interface);
547 if (bcr == PCI_BCR_MASS_STORAGE && scr == PCI_MS_IDE)
548 ; /* Okay */
549 else if (t3 == PCI_T3_RAID)
550 {
551 for (i= 0; raid_table[i].vendor != 0; i++)
552 {
553 if (raid_table[i].vendor == vid &&
554 raid_table[i].device == did)
555 {
556 break;
557 }
558 }
559 if (raid_table[i].vendor == 0)
560 {
561 printf(
562 "atapci skipping unsupported RAID controller 0x%04x / 0x%04x\n",
563 vid, did);
564 continue;
565 }
566 printf("found supported RAID controller\n");
567 raid= 1;
568 }
569 else
570 continue; /* Unsupported device class */
571
572 pci_reserve(devind);
573
574 /* Found a controller.
575 * Programming interface register tells us more.
576 */
577 irq = pci_attr_r8(devind, PCI_ILR);
578
579 /* Any non-compat drives? */
580 if (raid || (interface & (ATA_IF_NOTCOMPAT1 | ATA_IF_NOTCOMPAT2))) {
581 int s;
582
583 if (w_next_drive >= MAX_DRIVES)
584 {
585 /* We can't accept more drives, but have to search for
586 * controllers operating in compatibility mode.
587 */
588 continue;
589 }
590
591 irq_hook = irq;
592 if (skip > 0) {
593 if (w_pci_debug)
594 {
595 printf(
596 "atapci skipping controller (remain %d)\n",
597 skip);
598 }
599 skip--;
600 continue;
601 }
602 if ((s=sys_irqsetpolicy(irq, 0, &irq_hook)) != OK) {
603 printf("atapci: couldn't set IRQ policy %d\n", irq);
604 continue;
605 }
606 if ((s=sys_irqenable(&irq_hook)) != OK) {
607 printf("atapci: couldn't enable IRQ line %d\n", irq);
608 continue;
609 }
610 }
611
612 base_dma = pci_attr_r32(devind, PCI_BAR_5) & 0xfffffffc;
613
614 /* Primary channel not in compatability mode? */
615 if (raid || (interface & ATA_IF_NOTCOMPAT1)) {
616 u32_t base_cmd, base_ctl;
617
618 base_cmd = pci_attr_r32(devind, PCI_BAR) & 0xfffffffc;
619 base_ctl = pci_attr_r32(devind, PCI_BAR_2) & 0xfffffffc;
620 if (base_cmd != REG_CMD_BASE0 && base_cmd != REG_CMD_BASE1) {
621 init_drive(&wini[w_next_drive],
622 base_cmd, base_ctl+PCI_CTL_OFF,
623 base_dma, irq, 1, irq_hook, 0);
624 init_drive(&wini[w_next_drive+1],
625 base_cmd, base_ctl+PCI_CTL_OFF,
626 base_dma, irq, 1, irq_hook, 1);
627 if (w_pci_debug)
628 printf("atapci %d: 0x%x 0x%x irq %d\n", devind, base_cmd, base_ctl, irq);
629 w_next_drive += 2;
630 } else printf("atapci: ignored drives on primary channel, base %x\n", base_cmd);
631 }
632 else
633 {
634 /* Update base_dma for compatibility device */
635 for (i= 0; i<MAX_DRIVES; i++)
636 {
637 if (wini[i].base_cmd == REG_CMD_BASE0)
638 wini[i].base_dma= base_dma;
639 }
640 }
641
642 /* Secondary channel not in compatability mode? */
643 if (raid || (interface & ATA_IF_NOTCOMPAT2)) {
644 u32_t base_cmd, base_ctl;
645
646 base_cmd = pci_attr_r32(devind, PCI_BAR_3) & 0xfffffffc;
647 base_ctl = pci_attr_r32(devind, PCI_BAR_4) & 0xfffffffc;
648 if (base_dma != 0)
649 base_dma += PCI_DMA_2ND_OFF;
650 if (base_cmd != REG_CMD_BASE0 && base_cmd != REG_CMD_BASE1) {
651 init_drive(&wini[w_next_drive],
652 base_cmd, base_ctl+PCI_CTL_OFF, base_dma,
653 irq, 1, irq_hook, 2);
654 init_drive(&wini[w_next_drive+1],
655 base_cmd, base_ctl+PCI_CTL_OFF, base_dma,
656 irq, 1, irq_hook, 3);
657 if (w_pci_debug)
658 printf("atapci %d: 0x%x 0x%x irq %d\n", devind, base_cmd, base_ctl, irq);
659 w_next_drive += 2;
660 } else printf("atapci: ignored drives on secondary channel, base %x\n", base_cmd);
661 }
662 else
663 {
664 /* Update base_dma for compatibility device */
665 for (i= 0; i<MAX_DRIVES; i++)
666 {
667 if (wini[i].base_cmd == REG_CMD_BASE1 && base_dma != 0)
668 wini[i].base_dma= base_dma+PCI_DMA_2ND_OFF;
669 }
670 }
671 }
672 }
673
674 /*===========================================================================*
675 * w_do_open *
676 *===========================================================================*/
677 PRIVATE int w_do_open(dp, m_ptr)
678 struct driver *dp;
679 message *m_ptr;
680 {
681 /* Device open: Initialize the controller and read the partition table. */
682
683 struct wini *wn;
684
685 if (w_prepare(m_ptr->DEVICE) == NIL_DEV) return(ENXIO);
686
687 wn = w_wn;
688
689 /* If we've probed it before and it failed, don't probe it again. */
690 if (wn->state & IGNORING) return ENXIO;
691
692 /* If we haven't identified it yet, or it's gone deaf,
693 * (re-)identify it.
694 */
695 if (!(wn->state & IDENTIFIED) || (wn->state & DEAF)) {
696 /* Try to identify the device. */
697 if (w_identify() != OK) {
698 #if VERBOSE
699 printf("%s: probe failed\n", w_name());
700 #endif
701 if (wn->state & DEAF) w_reset();
702 wn->state = IGNORING;
703 return(ENXIO);
704 }
705 /* Do a test transaction unless it's a CD drive (then
706 * we can believe the controller, and a test may fail
707 * due to no CD being in the drive). If it fails, ignore
708 * the device forever.
709 */
710 if (!(wn->state & ATAPI) && w_io_test() != OK) {
711 wn->state |= IGNORING;
712 return(ENXIO);
713 }
714
715 #if VERBOSE
716 printf("%s: AT driver detected ", w_name());
717 if (wn->state & (SMART|ATAPI)) {
718 printf("%.40s\n", w_id_string);
719 } else {
720 printf("%ux%ux%u\n", wn->pcylinders, wn->pheads, wn->psectors);
721 }
722 #endif
723 }
724
725 #if ENABLE_ATAPI
726 if ((wn->state & ATAPI) && (m_ptr->COUNT & W_BIT))
727 return(EACCES);
728 #endif
729
730 /* Partition the drive if it's being opened for the first time,
731 * or being opened after being closed.
732 */
733 if (wn->open_ct == 0) {
734 #if ENABLE_ATAPI
735 if (wn->state & ATAPI) {
736 int r;
737 if ((r = atapi_open()) != OK) return(r);
738 }
739 #endif
740
741 /* Partition the disk. */
742 partition(&w_dtab, w_drive * DEV_PER_DRIVE, P_PRIMARY, wn->state & ATAPI);
743 }
744 wn->open_ct++;
745 return(OK);
746 }
747
748 /*===========================================================================*
749 * w_prepare *
750 *===========================================================================*/
751 PRIVATE struct device *w_prepare(int device)
752 {
753 /* Prepare for I/O on a device. */
754 struct wini *prev_wn;
755 prev_wn = w_wn;
756 w_device = device;
757
758 if (device < NR_MINORS) { /* d0, d0p[0-3], d1, ... */
759 w_drive = device / DEV_PER_DRIVE; /* save drive number */
760 w_wn = &wini[w_drive];
761 w_dv = &w_wn->part[device % DEV_PER_DRIVE];
762 } else
763 if ((unsigned) (device -= MINOR_d0p0s0) < NR_SUBDEVS) {/*d[0-7]p[0-3]s[0-3]*/
764 w_drive = device / SUB_PER_DRIVE;
765 w_wn = &wini[w_drive];
766 w_dv = &w_wn->subpart[device % SUB_PER_DRIVE];
767 } else {
768 w_device = -1;
769 return(NIL_DEV);
770 }
771 return(w_dv);
772 }
773
774 /*===========================================================================*
775 * w_identify *
776 *===========================================================================*/
777 PRIVATE int w_identify()
778 {
779 /* Find out if a device exists, if it is an old AT disk, or a newer ATA
780 * drive, a removable media device, etc.
781 */
782
783 struct wini *wn = w_wn;
784 struct command cmd;
785 int i, s;
786 int id_dma, ultra_dma;
787 u32_t dma_base;
788 u16_t w;
789 unsigned long dma_status;
790 unsigned long size;
791 #define id_byte(n) (&tmp_buf[2 * (n)])
792 #define id_word(n) (((u16_t) id_byte(n)[0] << 0) \
793 |((u16_t) id_byte(n)[1] << 8))
794 #define id_longword(n) (((u32_t) id_byte(n)[0] << 0) \
795 |((u32_t) id_byte(n)[1] << 8) \
796 |((u32_t) id_byte(n)[2] << 16) \
797 |((u32_t) id_byte(n)[3] << 24))
798
799 /* Try to identify the device. */
800 cmd.ldh = wn->ldhpref;
801 cmd.command = ATA_IDENTIFY;
802 if (com_simple(&cmd) == OK && w_waitfor(STATUS_DRQ, STATUS_DRQ) &&
803 !(wn->w_status & (STATUS_ERR|STATUS_WF))) {
804
805 /* Device information. */
806 if ((s=sys_insw(wn->base_cmd + REG_DATA, SELF, tmp_buf, SECTOR_SIZE)) != OK)
807 panic(w_name(),"Call to sys_insw() failed", s);
808
809 #if 0
810 if (id_word(0) & ID_GEN_NOT_ATA)
811 {
812 printf("%s: not an ATA device?\n", w_name());
813 return ERR;
814 }
815 #endif
816
817 /* This is an ATA device. */
818 wn->state |= SMART;
819
820 /* Why are the strings byte swapped??? */
821 for (i = 0; i < 40; i++) w_id_string[i] = id_byte(27)[i^1];
822
823 /* Preferred CHS translation mode. */
824 wn->pcylinders = id_word(1);
825 wn->pheads = id_word(3);
826 wn->psectors = id_word(6);
827 size = (u32_t) wn->pcylinders * wn->pheads * wn->psectors;
828
829 w= id_word(ID_CAPABILITIES);
830 if ((w & ID_CAP_LBA) && size > 512L*1024*2) {
831 /* Drive is LBA capable and is big enough to trust it to
832 * not make a mess of it.
833 */
834 wn->ldhpref |= LDH_LBA;
835 size = id_longword(60);
836
837 w= id_word(ID_CSS);
838 if (size < LBA48_CHECK_SIZE)
839 {
840 /* No need to check for LBA48 */
841 }
842 else if (w & ID_CSS_LBA48) {
843 /* Drive is LBA48 capable (and LBA48 is turned on). */
844 if (id_longword(102)) {
845 /* If no. of sectors doesn't fit in 32 bits,
846 * trunacte to this. So it's LBA32 for now.
847 * This can still address devices up to 2TB
848 * though.
849 */
850 size = ULONG_MAX;
851 } else {
852 /* Actual number of sectors fits in 32 bits. */
853 size = id_longword(100);
854 }
855 wn->lba48 = 1;
856 }
857
858 /* Check for DMA. Assume that only LBA capable devices can do
859 * DMA.
860 */
861 w= id_word(ID_CAPABILITIES);
862 id_dma= !!(w & ID_CAP_DMA);
863 w= id_byte(ID_FIELD_VALIDITY)[0];
864 ultra_dma= !!(w & ID_FV_88);
865 dma_base= wn->base_dma;
866 if (dma_base)
867 {
868 if (sys_inb(dma_base + DMA_STATUS, &dma_status) != OK)
869 {
870 panic(w_name(),
871 "unable to read DMA status register",
872 NO_NUM);
873 }
874 }
875 if (disable_dma)
876 ; /* DMA is disabled */
877 else if (id_dma && dma_base)
878 {
879 w= id_word(ID_MULTIWORD_DMA);
880 if (w & (ID_MWDMA_2_SUP|ID_MWDMA_1_SUP|ID_MWDMA_0_SUP))
881 {
882 printf(
883 "%s: multiword DMA modes supported:%s%s%s\n",
884 w_name(),
885 (w & ID_MWDMA_0_SUP) ? " 0" : "",
886 (w & ID_MWDMA_1_SUP) ? " 1" : "",
887 (w & ID_MWDMA_2_SUP) ? " 2" : "");
888 }
889 if (w & (ID_MWDMA_0_SEL|ID_MWDMA_1_SEL|ID_MWDMA_2_SEL))
890 {
891 printf(
892 "%s: multiword DMA mode selected:%s%s%s\n",
893 w_name(),
894 (w & ID_MWDMA_0_SEL) ? " 0" : "",
895 (w & ID_MWDMA_1_SEL) ? " 1" : "",
896 (w & ID_MWDMA_2_SEL) ? " 2" : "");
897 }
898 if (ultra_dma)
899 {
900 w= id_word(ID_ULTRA_DMA);
901 if (w & (ID_UDMA_0_SUP|ID_UDMA_1_SUP|
902 ID_UDMA_2_SUP|ID_UDMA_3_SUP|
903 ID_UDMA_4_SUP|ID_UDMA_5_SUP))
904 {
905 printf(
906 "%s: Ultra DMA modes supported:%s%s%s%s%s%s\n",
907 w_name(),
908 (w & ID_UDMA_0_SUP) ? " 0" : "",
909 (w & ID_UDMA_1_SUP) ? " 1" : "",
910 (w & ID_UDMA_2_SUP) ? " 2" : "",
911 (w & ID_UDMA_3_SUP) ? " 3" : "",
912 (w & ID_UDMA_4_SUP) ? " 4" : "",
913 (w & ID_UDMA_5_SUP) ? " 5" : "");
914 }
915 if (w & (ID_UDMA_0_SEL|ID_UDMA_1_SEL|
916 ID_UDMA_2_SEL|ID_UDMA_3_SEL|
917 ID_UDMA_4_SEL|ID_UDMA_5_SEL))
918 {
919 printf(
920 "%s: Ultra DMA mode selected:%s%s%s%s%s%s\n",
921 w_name(),
922 (w & ID_UDMA_0_SEL) ? " 0" : "",
923 (w & ID_UDMA_1_SEL) ? " 1" : "",
924 (w & ID_UDMA_2_SEL) ? " 2" : "",
925 (w & ID_UDMA_3_SEL) ? " 3" : "",
926 (w & ID_UDMA_4_SEL) ? " 4" : "",
927 (w & ID_UDMA_5_SEL) ? " 5" : "");
928 }
929 }
930 wn->dma= 1;
931 }
932 else if (id_dma || dma_base)
933 {
934 printf("id_dma %d, dma_base 0x%x\n", id_dma, dma_base);
935 }
936 else
937 printf("no DMA support\n");
938
939 #if 0
940 if (wn->dma && wn == &wini[0])
941 {
942 printf("disabling DMA for drive 0\n");
943 wn->dma= 0;
944 }
945 #endif
946 }
947
948 if (wn->lcylinders == 0) {
949 /* No BIOS parameters? Then make some up. */
950 wn->lcylinders = wn->pcylinders;
951 wn->lheads = wn->pheads;
952 wn->lsectors = wn->psectors;
953 while (wn->lcylinders > 1024) {
954 wn->lheads *= 2;
955 wn->lcylinders /= 2;
956 }
957 }
958 #if ENABLE_ATAPI
959 } else
960 if (cmd.command = ATAPI_IDENTIFY,
961 com_simple(&cmd) == OK && w_waitfor(STATUS_DRQ, STATUS_DRQ) &&
962 !(wn->w_status & (STATUS_ERR|STATUS_WF))) {
963 /* An ATAPI device. */
964 wn->state |= ATAPI;
965
966 /* Device information. */
967 if ((s=sys_insw(wn->base_cmd + REG_DATA, SELF, tmp_buf, 512)) != OK)
968 panic(w_name(),"Call to sys_insw() failed", s);
969
970 /* Why are the strings byte swapped??? */
971 for (i = 0; i < 40; i++) w_id_string[i] = id_byte(27)[i^1];
972
973 size = 0; /* Size set later. */
974 #endif
975 } else {
976 /* Not an ATA device; no translations, no special features. Don't
977 * touch it unless the BIOS knows about it.
978 */
979 if (wn->lcylinders == 0) { return(ERR); } /* no BIOS parameters */
980 wn->pcylinders = wn->lcylinders;
981 wn->pheads = wn->lheads;
982 wn->psectors = wn->lsectors;
983 size = (u32_t) wn->pcylinders * wn->pheads * wn->psectors;
984 }
985
986 /* Size of the whole drive */
987 wn->part[0].dv_size = mul64u(size, SECTOR_SIZE);
988
989 /* Reset/calibrate (where necessary) */
990 if (w_specify() != OK && w_specify() != OK) {
991 return(ERR);
992 }
993
994 if (wn->irq == NO_IRQ) {
995 /* Everything looks OK; register IRQ so we can stop polling. */
996 wn->irq = w_drive < 2 ? AT_WINI_0_IRQ : AT_WINI_1_IRQ;
997 wn->irq_hook_id = wn->irq; /* id to be returned if interrupt occurs */
998 if ((s=sys_irqsetpolicy(wn->irq, IRQ_REENABLE, &wn->irq_hook_id)) != OK)
999 panic(w_name(), "couldn't set IRQ policy", s);
1000 if ((s=sys_irqenable(&wn->irq_hook_id)) != OK)
1001 panic(w_name(), "couldn't enable IRQ line", s);
1002 }
1003 wn->state |= IDENTIFIED;
1004 return(OK);
1005 }
1006
1007 /*===========================================================================*
1008 * w_name *
1009 *===========================================================================*/
1010 PRIVATE char *w_name()
1011 {
1012 /* Return a name for the current device. */
1013 static char name[] = "AT-D0";
1014
1015 name[4] = '0' + w_drive;
1016 return name;
1017 }
1018
1019 /*===========================================================================*
1020 * w_io_test *
1021 *===========================================================================*/
1022 PRIVATE int w_io_test(void)
1023 {
1024 int r, save_dev;
1025 int save_timeout, save_errors, save_wakeup;
1026 iovec_t iov;
1027 #ifdef CD_SECTOR_SIZE
1028 static char buf[CD_SECTOR_SIZE];
1029 #else
1030 static char buf[SECTOR_SIZE];
1031 #endif
1032
1033 iov.iov_addr = (vir_bytes) buf;
1034 iov.iov_size = sizeof(buf);
1035 save_dev = w_device;
1036
1037 /* Reduce timeout values for this test transaction. */
1038 save_timeout = timeout_ticks;
1039 save_errors = max_errors;
1040 save_wakeup = wakeup_ticks;
1041
1042 if (!w_standard_timeouts) {
1043 timeout_ticks = HZ * 4;
1044 wakeup_ticks = HZ * 6;
1045 max_errors = 3;
1046 }
1047
1048 w_testing = 1;
1049
1050 /* Try I/O on the actual drive (not any (sub)partition). */
1051 if (w_prepare(w_drive * DEV_PER_DRIVE) == NIL_DEV)
1052 panic(w_name(), "Couldn't switch devices", NO_NUM);
1053
1054 r = w_transfer(SELF, DEV_GATHER_S, cvu64(0), &iov, 1, 0);
1055
1056 /* Switch back. */
1057 if (w_prepare(save_dev) == NIL_DEV)
1058 panic(w_name(), "Couldn't switch back devices", NO_NUM);
1059
1060 /* Restore parameters. */
1061 timeout_ticks = save_timeout;
1062 max_errors = save_errors;
1063 wakeup_ticks = save_wakeup;
1064 w_testing = 0;
1065
1066 /* Test if everything worked. */
1067 if (r != OK || iov.iov_size != 0) {
1068 return ERR;
1069 }
1070
1071 /* Everything worked. */
1072
1073 return OK;
1074 }
1075
1076 /*===========================================================================*
1077 * w_specify *
1078 *===========================================================================*/
1079 PRIVATE int w_specify()
1080 {
1081 /* Routine to initialize the drive after boot or when a reset is needed. */
1082
1083 struct wini *wn = w_wn;
1084 struct command cmd;
1085
1086 if ((wn->state & DEAF) && w_reset() != OK) {
1087 return(ERR);
1088 }
1089
1090 if (!(wn->state & ATAPI)) {
1091 /* Specify parameters: precompensation, number of heads and sectors. */
1092 cmd.precomp = wn->precomp;
1093 cmd.count = wn->psectors;
1094 cmd.ldh = w_wn->ldhpref | (wn->pheads - 1);
1095 cmd.command = CMD_SPECIFY; /* Specify some parameters */
1096
1097 /* Output command block and see if controller accepts the parameters. */
1098 if (com_simple(&cmd) != OK) return(ERR);
1099
1100 if (!(wn->state & SMART)) {
1101 /* Calibrate an old disk. */
1102 cmd.sector = 0;
1103 cmd.cyl_lo = 0;
1104 cmd.cyl_hi = 0;
1105 cmd.ldh = w_wn->ldhpref;
1106 cmd.command = CMD_RECALIBRATE;
1107
1108 if (com_simple(&cmd) != OK) return(ERR);
1109 }
1110 }
1111 wn->state |= INITIALIZED;
1112 return(OK);
1113 }
1114
1115 /*===========================================================================*
1116 * do_transfer *
1117 *===========================================================================*/
1118 PRIVATE int do_transfer(struct wini *wn, unsigned int precomp,
1119 unsigned int count, unsigned int sector,
1120 unsigned int opcode, int do_dma)
1121 {
1122 struct command cmd;
1123 unsigned int sector_high;
1124 unsigned secspcyl = wn->pheads * wn->psectors;
1125 int do_lba48;
1126
1127 sector_high= 0; /* For future extensions */
1128
1129 do_lba48= 0;
1130 if (sector >= LBA48_CHECK_SIZE || sector_high != 0)
1131 {
1132 if (wn->lba48)
1133 do_lba48= 1;
1134 else if (sector > LBA_MAX_SIZE || sector_high != 0)
1135 {
1136 /* Strange sector count for LBA device */
1137 return EIO;
1138 }
1139 }
1140
1141 cmd.precomp = precomp;
1142 cmd.count = count;
1143 if (do_dma)
1144 {
1145 cmd.command = opcode == DEV_SCATTER_S ? CMD_WRITE_DMA :
1146 CMD_READ_DMA;
1147 }
1148 else
1149 cmd.command = opcode == DEV_SCATTER_S ? CMD_WRITE : CMD_READ;
1150
1151 if (do_lba48) {
1152 if (do_dma)
1153 {
1154 cmd.command = ((opcode == DEV_SCATTER_S) ?
1155 CMD_WRITE_DMA_EXT : CMD_READ_DMA_EXT);
1156 }
1157 else
1158 {
1159 cmd.command = ((opcode == DEV_SCATTER_S) ?
1160 CMD_WRITE_EXT : CMD_READ_EXT);
1161 }
1162 cmd.count_prev= (count >> 8);
1163 cmd.sector = (sector >> 0) & 0xFF;
1164 cmd.cyl_lo = (sector >> 8) & 0xFF;
1165 cmd.cyl_hi = (sector >> 16) & 0xFF;
1166 cmd.sector_prev= (sector >> 24) & 0xFF;
1167 cmd.cyl_lo_prev= (sector_high) & 0xFF;
1168 cmd.cyl_hi_prev= (sector_high >> 8) & 0xFF;
1169 cmd.ldh = wn->ldhpref;
1170
1171 return com_out_ext(&cmd);
1172 } else if (wn->ldhpref & LDH_LBA) {
1173 cmd.sector = (sector >> 0) & 0xFF;
1174 cmd.cyl_lo = (sector >> 8) & 0xFF;
1175 cmd.cyl_hi = (sector >> 16) & 0xFF;
1176 cmd.ldh = wn->ldhpref | ((sector >> 24) & 0xF);
1177 } else {
1178 int cylinder, head, sec;
1179 cylinder = sector / secspcyl;
1180 head = (sector % secspcyl) / wn->psectors;
1181 sec = sector % wn->psectors;
1182 cmd.sector = sec + 1;
1183 cmd.cyl_lo = cylinder & BYTE;
1184 cmd.cyl_hi = (cylinder >> 8) & BYTE;
1185 cmd.ldh = wn->ldhpref | head;
1186 }
1187
1188 return com_out(&cmd);
1189 }
1190
1191 /*===========================================================================*
1192 * w_transfer *
1193 *===========================================================================*/
1194 PRIVATE int w_transfer(proc_nr, opcode, position, iov, nr_req, safe)
1195 int proc_nr; /* process doing the request */
1196 int opcode; /* DEV_GATHER_S or DEV_SCATTER_S */
1197 u64_t position; /* offset on device to read or write */
1198 iovec_t *iov; /* pointer to read or write request vector */
1199 unsigned nr_req; /* length of request vector */
1200 int safe; /* iov contains addresses (0) or grants? */
1201 {
1202 struct wini *wn = w_wn;
1203 iovec_t *iop, *iov_end = iov + nr_req;
1204 int n, r, s, errors, do_dma, do_write, do_copyout;
1205 unsigned long v, block, w_status;
1206 u64_t dv_size = w_dv->dv_size;
1207 unsigned cylinder, head, sector, nbytes;
1208 unsigned dma_buf_offset;
1209 size_t addr_offset = 0;
1210
1211 #if ENABLE_ATAPI
1212 if (w_wn->state & ATAPI) {
1213 return atapi_transfer(proc_nr, opcode, position, iov, nr_req, safe);
1214 }
1215 #endif
1216
1217 /* Check disk address. */
1218 if (rem64u(position, SECTOR_SIZE) != 0) return(EINVAL);
1219
1220 errors = 0;
1221
1222 while (nr_req > 0) {
1223 /* How many bytes to transfer? */
1224 nbytes = 0;
1225 for (iop = iov; iop < iov_end; iop++) nbytes += iop->iov_size;
1226 if ((nbytes & SECTOR_MASK) != 0) return(EINVAL);
1227
1228 /* Which block on disk and how close to EOF? */
1229 if (cmp64(position, dv_size) >= 0) return(OK); /* At EOF */
1230 if (cmp64(add64ul(position, nbytes), dv_size) > 0)
1231 nbytes = diff64(dv_size, position);
1232 block = div64u(add64(w_dv->dv_base, position), SECTOR_SIZE);
1233
1234 do_dma= wn->dma;
1235 do_write= (opcode == DEV_SCATTER_S);
1236
1237 if (nbytes >= wn->max_count) {
1238 /* The drive can't do more then max_count at once. */
1239 nbytes = wn->max_count;
1240 }
1241
1242 /* First check to see if a reinitialization is needed. */
1243 if (!(wn->state & INITIALIZED) && w_specify() != OK) return(EIO);
1244
1245 if (do_dma)
1246 {
1247 setup_dma(&nbytes, proc_nr, iov, do_write, &do_copyout, safe);
1248 #if 0
1249 printf("nbytes = %d\n", nbytes);
1250 #endif
1251 }
1252
1253 /* Tell the controller to transfer nbytes bytes. */
1254 r = do_transfer(wn, wn->precomp, (nbytes >> SECTOR_SHIFT),
1255 block, opcode, do_dma);
1256
1257 if (opcode == DEV_SCATTER_S) {
1258 /* The specs call for a 400 ns wait after issuing the command.
1259 * Reading the alternate status register is the suggested
1260 * way to implement this wait.
1261 */
1262 if (sys_inb((wn->base_ctl+REG_CTL_ALTSTAT), &w_status) != OK)
1263 panic(w_name(), "couldn't get status", NO_NUM);
1264 }
1265
1266 if (do_dma)
1267 {
1268 /* Wait for the interrupt, check DMA status and optionally
1269 * copy out.
1270 */
1271
1272 if ((r = at_intr_wait()) != OK)
1273 {
1274 /* Don't retry if sector marked bad or too many
1275 * errors.
1276 */
1277 if (r == ERR_BAD_SECTOR || ++errors == max_errors) {
1278 w_command = CMD_IDLE;
1279 return(EIO);
1280 }
1281 continue;
1282 }
1283
1284 /* Wait for DMA_ST_INT to get set */
1285 w_waitfor_dma(DMA_ST_INT, DMA_ST_INT);
1286
1287 r= sys_inb(wn->base_dma + DMA_STATUS, &v);
1288 if (r != 0) panic("at_wini", "w_transfer: sys_inb failed", r);
1289
1290 #if 0
1291 printf("dma_status: 0x%x\n", v);
1292 #endif
1293 if (!(v & DMA_ST_INT))
1294 {
1295 /* DMA did not complete successfully */
1296 if (v & DMA_ST_BM_ACTIVE)
1297 panic(w_name(), "DMA did not complete", NO_NUM);
1298 else if (v & DMA_ST_ERROR)
1299 {
1300 printf("at_wini: DMA error\n");
1301 r= EIO;
1302 break;
1303 }
1304 else
1305 {
1306 #if 0
1307 printf("DMA buffer too small\n");
1308 #endif
1309 panic(w_name(), "DMA buffer too small", NO_NUM);
1310 }
1311 }
1312 else if (v & DMA_ST_BM_ACTIVE)
1313 panic(w_name(), "DMA buffer too large", NO_NUM);
1314
1315 dma_buf_offset= 0;
1316 while (r == OK && nbytes > 0)
1317 {
1318 n= iov->iov_size;
1319 if (n > nbytes)
1320 n= nbytes;
1321
1322 if (do_copyout)
1323 {
1324 if(safe) {
1325 s= sys_safecopyto(proc_nr, iov->iov_addr,
1326 addr_offset,
1327 (vir_bytes)dma_buf+dma_buf_offset, n, D);
1328 } else {
1329 s= sys_vircopy(SELF, D,
1330 (vir_bytes)dma_buf+dma_buf_offset,
1331 proc_nr, D,
1332 iov->iov_addr + addr_offset, n);
1333 }
1334 if (s != OK)
1335 {
1336 panic(w_name(),
1337 "w_transfer: sys_vircopy failed",
1338 s);
1339 }
1340 }
1341
1342 /* Book the bytes successfully transferred. */
1343 nbytes -= n;
1344 position= add64ul(position, n);
1345 if ((iov->iov_size -= n) == 0) {
1346 iov++; nr_req--; addr_offset = 0;
1347 }
1348 dma_buf_offset += n;
1349 }
1350 }
1351
1352 while (r == OK && nbytes > 0) {
1353 /* For each sector, wait for an interrupt and fetch the data
1354 * (read), or supply data to the controller and wait for an
1355 * interrupt (write).
1356 */
1357
1358 if (opcode == DEV_GATHER_S) {
1359 /* First an interrupt, then data. */
1360 if ((r = at_intr_wait()) != OK) {
1361 /* An error, send data to the bit bucket. */
1362 if (w_wn->w_status & STATUS_DRQ) {
1363 if ((s=sys_insw(wn->base_cmd+REG_DATA,
1364 SELF, tmp_buf,
1365 SECTOR_SIZE)) != OK)
1366 {
1367 panic(w_name(),
1368 "Call to sys_insw() failed",
1369 s);
1370 }
1371 }
1372 break;
1373 }
1374 }
1375
1376 /* Wait for busy to clear. */
1377 if (!w_waitfor(STATUS_BSY, 0)) { r = ERR; break; }
1378
1379 /* Wait for data transfer requested. */
1380 if (!w_waitfor(STATUS_DRQ, STATUS_DRQ)) { r = ERR; break; }
1381
1382 /* Copy bytes to or from the device's buffer. */
1383 if (opcode == DEV_GATHER_S) {
1384 if(safe) {
1385 s=sys_safe_insw(wn->base_cmd + REG_DATA, proc_nr,
1386 (void *) (iov->iov_addr), addr_offset,
1387 SECTOR_SIZE);
1388 } else {
1389 s=sys_insw(wn->base_cmd + REG_DATA, proc_nr,
1390 (void *) (iov->iov_addr + addr_offset),
1391 SECTOR_SIZE);
1392 }
1393 if(s != OK) {
1394 panic(w_name(),"Call to sys_insw() failed", s);
1395 }
1396 } else {
1397 if(safe) {
1398 s=sys_safe_outsw(wn->base_cmd + REG_DATA, proc_nr,
1399 (void *) (iov->iov_addr), addr_offset,
1400 SECTOR_SIZE);
1401 } else {
1402 s=sys_outsw(wn->base_cmd + REG_DATA, proc_nr,
1403 (void *) (iov->iov_addr + addr_offset),
1404 SECTOR_SIZE);
1405 }
1406
1407 if(s != OK) {
1408 panic(w_name(),"Call to sys_outsw() failed",
1409 s);
1410 }
1411
1412 /* Data sent, wait for an interrupt. */
1413 if ((r = at_intr_wait()) != OK) break;
1414 }
1415
1416 /* Book the bytes successfully transferred. */
1417 nbytes -= SECTOR_SIZE;
1418 position= add64u(position, SECTOR_SIZE);
1419 addr_offset += SECTOR_SIZE;
1420 if ((iov->iov_size -= SECTOR_SIZE) == 0) {
1421 iov++;
1422 nr_req--;
1423 addr_offset = 0;
1424 }
1425 }
1426
1427 /* Any errors? */
1428 if (r != OK) {
1429 /* Don't retry if sector marked bad or too many errors. */
1430 if (r == ERR_BAD_SECTOR || ++errors == max_errors) {
1431 w_command = CMD_IDLE;
1432 return(EIO);
1433 }
1434 }
1435 }
1436
1437 w_command = CMD_IDLE;
1438 return(OK);
1439 }
1440
1441 /*===========================================================================*
1442 * com_out *
1443 *===========================================================================*/
1444 PRIVATE int com_out(cmd)
1445 struct command *cmd; /* Command block */
1446 {
1447 /* Output the command block to the winchester controller and return status */
1448
1449 struct wini *wn = w_wn;
1450 unsigned base_cmd = wn->base_cmd;
1451 unsigned base_ctl = wn->base_ctl;
1452 pvb_pair_t outbyte[7]; /* vector for sys_voutb() */
1453 int s; /* status for sys_(v)outb() */
1454
1455 if (w_wn->state & IGNORING) return ERR;
1456
1457 if (!w_waitfor(STATUS_BSY, 0)) {
1458 printf("%s: controller not ready\n", w_name());
1459 return(ERR);
1460 }
1461
1462 /* Select drive. */
1463 if ((s=sys_outb(base_cmd + REG_LDH, cmd->ldh)) != OK)
1464 panic(w_name(),"Couldn't write register to select drive",s);
1465
1466 if (!w_waitfor(STATUS_BSY, 0)) {
1467 printf("%s: com_out: drive not ready\n", w_name());
1468 return(ERR);
1469 }
1470
1471 /* Schedule a wakeup call, some controllers are flaky. This is done with
1472 * a synchronous alarm. If a timeout occurs a SYN_ALARM message is sent
1473 * from HARDWARE, so that w_intr_wait() can call w_timeout() in case the
1474 * controller was not able to execute the command. Leftover timeouts are
1475 * simply ignored by the main loop.
1476 */
1477 sys_setalarm(wakeup_ticks, 0);
1478
1479 wn->w_status = STATUS_ADMBSY;
1480 w_command = cmd->command;
1481 pv_set(outbyte[0], base_ctl + REG_CTL, wn->pheads >= 8 ? CTL_EIGHTHEADS : 0);
1482 pv_set(outbyte[1], base_cmd + REG_PRECOMP, cmd->precomp);
1483 pv_set(outbyte[2], base_cmd + REG_COUNT, cmd->count);
1484 pv_set(outbyte[3], base_cmd + REG_SECTOR, cmd->sector);
1485 pv_set(outbyte[4], base_cmd + REG_CYL_LO, cmd->cyl_lo);
1486 pv_set(outbyte[5], base_cmd + REG_CYL_HI, cmd->cyl_hi);
1487 pv_set(outbyte[6], base_cmd + REG_COMMAND, cmd->command);
1488 if ((s=sys_voutb(outbyte,7)) != OK)
1489 panic(w_name(),"Couldn't write registers with sys_voutb()",s);
1490 return(OK);
1491 }
1492
1493 /*===========================================================================*
1494 * com_out_ext *
1495 *===========================================================================*/
1496 PRIVATE int com_out_ext(cmd)
1497 struct command *cmd; /* Command block */
1498 {
1499 /* Output the command block to the winchester controller and return status */
1500
1501 struct wini *wn = w_wn;
1502 unsigned base_cmd = wn->base_cmd;
1503 unsigned base_ctl = wn->base_ctl;
1504 pvb_pair_t outbyte[11]; /* vector for sys_voutb() */
1505 int s; /* status for sys_(v)outb() */
1506 unsigned long w_status;
1507
1508 if (w_wn->state & IGNORING) return ERR;
1509
1510 if (!w_waitfor(STATUS_BSY, 0)) {
1511 printf("%s: controller not ready\n", w_name());
1512 return(ERR);
1513 }
1514
1515 /* Select drive. */
1516 if ((s=sys_outb(base_cmd + REG_LDH, cmd->ldh)) != OK)
1517 panic(w_name(),"Couldn't write register to select drive",s);
1518
1519 if (!w_waitfor(STATUS_BSY, 0)) {
1520 printf("%s: com_out: drive not ready\n", w_name());
1521 return(ERR);
1522 }
1523
1524 /* Schedule a wakeup call, some controllers are flaky. This is done with
1525 * a synchronous alarm. If a timeout occurs a SYN_ALARM message is sent
1526 * from HARDWARE, so that w_intr_wait() can call w_timeout() in case the
1527 * controller was not able to execute the command. Leftover timeouts are
1528 * simply ignored by the main loop.
1529 */
1530 sys_setalarm(wakeup_ticks, 0);
1531
1532 wn->w_status = STATUS_ADMBSY;
1533 w_command = cmd->command;
1534 pv_set(outbyte[0], base_ctl + REG_CTL, 0);
1535 pv_set(outbyte[1], base_cmd + REG_COUNT, cmd->count_prev);
1536 pv_set(outbyte[2], base_cmd + REG_SECTOR, cmd->sector_prev);
1537 pv_set(outbyte[3], base_cmd + REG_CYL_LO, cmd->cyl_lo_prev);
1538 pv_set(outbyte[4], base_cmd + REG_CYL_HI, cmd->cyl_hi_prev);
1539 pv_set(outbyte[5], base_cmd + REG_COUNT, cmd->count);
1540 pv_set(outbyte[6], base_cmd + REG_SECTOR, cmd->sector);
1541 pv_set(outbyte[7], base_cmd + REG_CYL_LO, cmd->cyl_lo);
1542 pv_set(outbyte[8], base_cmd + REG_CYL_HI, cmd->cyl_hi);
1543
1544 pv_set(outbyte[10], base_cmd + REG_COMMAND, cmd->command);
1545 if ((s=sys_voutb(outbyte, 11)) != OK)
1546 panic(w_name(),"Couldn't write registers with sys_voutb()",s);
1547
1548 return(OK);
1549 }
1550
1551 /*===========================================================================*
1552 * setup_dma *
1553 *===========================================================================*/
1554 PRIVATE void setup_dma(sizep, proc_nr, iov, do_write, do_copyoutp, safe)
1555 unsigned *sizep;
1556 int proc_nr;
1557 iovec_t *iov;
1558 int do_write;
1559 int *do_copyoutp;
1560 int safe;
1561 {
1562 phys_bytes phys, user_phys;
1563 unsigned n, offset, size;
1564 int i, j, r, bad;
1565 unsigned long v;
1566 struct wini *wn = w_wn;
1567
1568 /* First try direct scatter/gather to the supplied buffers */
1569 size= *sizep;
1570 i= 0; /* iov index */
1571 j= 0; /* prdt index */
1572 bad= 0;
1573 offset= 0; /* Offset in current iov */
1574
1575 #if 0
1576 printf("setup_dma: proc_nr %d\n", proc_nr);
1577 #endif
1578
1579 while (size > 0)
1580 {
1581 #if 0
1582 printf(
1583 "setup_dma: iov[%d]: addr 0x%x, size %d offset %d, size %d\n",
1584 i, iov[i].iov_addr, iov[i].iov_size, offset, size);
1585 #endif
1586
1587 n= iov[i].iov_size-offset;
1588 if (n > size)
1589 n= size;
1590 if (n == 0 || (n & 1))
1591 panic("at_wini", "bad size in iov", iov[i].iov_size);
1592 if(safe) {
1593 r= sys_umap(proc_nr, GRANT_SEG, iov[i].iov_addr, n,&user_phys);
1594 user_phys += offset;
1595 } else {
1596 r= sys_umap(proc_nr, D, iov[i].iov_addr+offset, n, &user_phys);
1597 }
1598 if (r != 0)
1599 panic("at_wini", "can't map user buffer", r);
1600 if (user_phys & 1)
1601 {
1602 /* Buffer is not aligned */
1603 printf("setup_dma: user buffer is not aligned\n");
1604 bad= 1;
1605 break;
1606 }
1607
1608 /* vector is not allowed to cross a 64K boundary */
1609 if (user_phys/0x10000 != (user_phys+n-1)/0x10000)
1610 n= ((user_phys/0x10000)+1)*0x10000 - user_phys;
1611
1612 /* vector is not allowed to be bigger than 64K, but we get that
1613 * for free.
1614 */
1615
1616 if (j >= N_PRDTE)
1617 {
1618 /* Too many entries */
1619 bad= 1;
1620 break;
1621 }
1622
1623 prdt[j].prdte_base= user_phys;
1624 prdt[j].prdte_count= n;
1625 prdt[j].prdte_reserved= 0;
1626 prdt[j].prdte_flags= 0;
1627 j++;
1628
1629 offset += n;
1630 if (offset >= iov[i].iov_size)
1631 {
1632 i++;
1633 offset= 0;
1634 }
1635
1636 size -= n;
1637 }
1638
1639 if (!bad)
1640 {
1641 if (j <= 0 || j > N_PRDTE)
1642 panic("at_wini", "bad prdt index", j);
1643 prdt[j-1].prdte_flags |= PRDTE_FL_EOT;
1644
1645 #if 0
1646 for (i= 0; i<j; i++)
1647 {
1648 printf("prdt[%d]: base 0x%x, size %d, flags 0x%x\n",
1649 i, prdt[i].prdte_base, prdt[i].prdte_count,
1650 prdt[i].prdte_flags);
1651 }
1652 #endif
1653 }
1654
1655 /* The caller needs to perform a copy-out from the dma buffer if
1656 * this is a read request and we can't DMA directly to the user's
1657 * buffers.
1658 */
1659 *do_copyoutp= (!do_write && bad);
1660
1661 if (bad)
1662 {
1663 /* Adjust request size */
1664 size= *sizep;
1665 if (size > ATA_DMA_BUF_SIZE)
1666 *sizep= size= ATA_DMA_BUF_SIZE;
1667
1668 if (do_write)
1669 {
1670 /* Copy-in */
1671 for (offset= 0; offset < size; offset += n)
1672 {
1673 n= size-offset;
1674 if (n > iov->iov_size)
1675 n= iov->iov_size;
1676
1677 if(safe) {
1678 r= sys_safecopyfrom(proc_nr, iov->iov_addr,
1679 0, (vir_bytes)dma_buf+offset, n, D);
1680 } else {
1681 r= sys_vircopy(proc_nr, D, iov->iov_addr,
1682 SELF, D, (vir_bytes)dma_buf+offset,
1683 n);
1684 }
1685 if (r != OK)
1686 {
1687 panic(w_name(),
1688 "setup_dma: sys_vircopy failed",
1689 r);
1690 }
1691 iov++;
1692 }
1693 }
1694
1695 /* Fill-in the physical region descriptor table */
1696 phys= dma_buf_phys;
1697 if (phys & 1)
1698 {
1699 /* Two byte alignment is required */
1700 panic("at_wini", "bad buffer alignment in setup_dma",
1701 phys);
1702 }
1703 for (j= 0; j<N_PRDTE; i++)
1704 {
1705 if (size == 0)
1706 {
1707 panic("at_wini", "bad size in setup_dma",
1708 size);
1709 }
1710 if (size & 1)
1711 {
1712 /* Two byte alignment is required for size */
1713 panic("at_wini",
1714 "bad size alignment in setup_dma",
1715 size);
1716 }
1717 n= size;
1718
1719 /* Buffer is not allowed to cross a 64K boundary */
1720 if (phys / 0x10000 != (phys+n-1) / 0x10000)
1721 {
1722 n= ((phys/0x10000)+1)*0x10000 - phys;
1723 }
1724 prdt[j].prdte_base= phys;
1725 prdt[j].prdte_count= n;
1726 prdt[j].prdte_reserved= 0;
1727 prdt[j].prdte_flags= 0;
1728
1729 size -= n;
1730 if (size == 0)
1731 {
1732 prdt[j].prdte_flags |= PRDTE_FL_EOT;
1733 break;
1734 }
1735 }
1736 if (size != 0)
1737 panic("at_wini", "size to large for prdt", NO_NUM);
1738
1739 #if 0
1740 for (i= 0; i<=j; i++)
1741 {
1742 printf("prdt[%d]: base 0x%x, size %d, flags 0x%x\n",
1743 i, prdt[i].prdte_base, prdt[i].prdte_count,
1744 prdt[i].prdte_flags);
1745 }
1746 #endif
1747 }
1748
1749 /* Stop bus master operation */
1750 r= sys_outb(wn->base_dma + DMA_COMMAND, 0);
1751 if (r != 0) panic("at_wini", "setup_dma: sys_outb failed", r);
1752
1753 /* Verify that the bus master is not active */
1754 r= sys_inb(wn->base_dma + DMA_STATUS, &v);
1755 if (r != 0) panic("at_wini", "setup_dma: sys_inb failed", r);
1756 if (v & DMA_ST_BM_ACTIVE)
1757 panic("at_wini", "Bus master IDE active", NO_NUM);
1758
1759 if (prdt_phys & 3)
1760 panic("at_wini", "prdt not aligned", prdt_phys);
1761 r= sys_outl(wn->base_dma + DMA_PRDTP, prdt_phys);
1762 if (r != 0) panic("at_wini", "setup_dma: sys_outl failed", r);
1763
1764 /* Clear interrupt and error flags */
1765 r= sys_outb(wn->base_dma + DMA_STATUS, DMA_ST_INT | DMA_ST_ERROR);
1766 if (r != 0) panic("at_wini", "setup_dma: sys_outb failed", r);
1767
1768 /* Assume disk reads. Start DMA */
1769 v= DMA_CMD_START;
1770 if (!do_write)
1771 {
1772 /* Disk reads generate PCI write cycles. */
1773 v |= DMA_CMD_WRITE;
1774 }
1775 r= sys_outb(wn->base_dma + DMA_COMMAND, v);
1776 if (r != 0) panic("at_wini", "setup_dma: sys_outb failed", r);
1777
1778 #if 0
1779 r= sys_inb(wn->base_dma + DMA_STATUS, &v);
1780 if (r != 0) panic("at_wini", "setup_dma: sys_inb failed", r);
1781 printf("dma status: 0x%x\n", v);
1782 #endif
1783 }
1784
1785
1786 /*===========================================================================*
1787 * w_need_reset *
1788 *===========================================================================*/
1789 PRIVATE void w_need_reset()
1790 {
1791 /* The controller needs to be reset. */
1792 struct wini *wn;
1793 int dr = 0;
1794
1795 for (wn = wini; wn < &wini[MAX_DRIVES]; wn++, dr++) {
1796 if (wn->base_cmd == w_wn->base_cmd) {
1797 wn->state |= DEAF;
1798 wn->state &= ~INITIALIZED;
1799 }
1800 }
1801 }
1802
1803 /*===========================================================================*
1804 * w_do_close *
1805 *===========================================================================*/
1806 PRIVATE int w_do_close(dp, m_ptr)
1807 struct driver *dp;
1808 message *m_ptr;
1809 {
1810 /* Device close: Release a device. */
1811 if (w_prepare(m_ptr->DEVICE) == NIL_DEV)
1812 return(ENXIO);
1813 w_wn->open_ct--;
1814 #if ENABLE_ATAPI
1815 if (w_wn->open_ct == 0 && (w_wn->state & ATAPI)) atapi_close();
1816 #endif
1817 return(OK);
1818 }
1819
1820 /*===========================================================================*
1821 * com_simple *
1822 *===========================================================================*/
1823 PRIVATE int com_simple(cmd)
1824 struct command *cmd; /* Command block */
1825 {
1826 /* A simple controller command, only one interrupt and no data-out phase. */
1827 int r;
1828
1829 if (w_wn->state & IGNORING) return ERR;
1830
1831 if ((r = com_out(cmd)) == OK) r = at_intr_wait();
1832 w_command = CMD_IDLE;
1833 return(r);
1834 }
1835
1836 /*===========================================================================*
1837 * w_timeout *
1838 *===========================================================================*/
1839 PRIVATE void w_timeout(void)
1840 {
1841 struct wini *wn = w_wn;
1842
1843 switch (w_command) {
1844 case CMD_IDLE:
1845 break; /* fine */
1846 case CMD_READ:
1847 case CMD_READ_EXT:
1848 case CMD_WRITE:
1849 case CMD_WRITE_EXT:
1850 /* Impossible, but not on PC's: The controller does not respond. */
1851
1852 /* Limiting multisector I/O seems to help. */
1853 if (wn->max_count > 8 * SECTOR_SIZE) {
1854 wn->max_count = 8 * SECTOR_SIZE;
1855 } else {
1856 wn->max_count = SECTOR_SIZE;
1857 }
1858 /*FALL THROUGH*/
1859 default:
1860 /* Some other command. */
1861 if (w_testing) wn->state |= IGNORING; /* Kick out this drive. */
1862 else if (!w_silent) printf("%s: timeout on command 0x%02x\n",
1863 w_name(), w_command);
1864 w_need_reset();
1865 wn->w_status = 0;
1866 }
1867 }
1868
1869 /*===========================================================================*
1870 * w_reset *
1871 *===========================================================================*/
1872 PRIVATE int w_reset()
1873 {
1874 /* Issue a reset to the controller. This is done after any catastrophe,
1875 * like the controller refusing to respond.
1876 */
1877 int s;
1878 struct wini *wn = w_wn;
1879
1880 /* Don't bother if this drive is forgotten. */
1881 if (w_wn->state & IGNORING) return ERR;
1882
1883 /* Wait for any internal drive recovery. */
1884 tickdelay(RECOVERY_TICKS);
1885
1886 /* Strobe reset bit */
1887 if ((s=sys_outb(wn->base_ctl + REG_CTL, CTL_RESET)) != OK)
1888 panic(w_name(),"Couldn't strobe reset bit",s);
1889 tickdelay(DELAY_TICKS);
1890 if ((s=sys_outb(wn->base_ctl + REG_CTL, 0)) != OK)
1891 panic(w_name(),"Couldn't strobe reset bit",s);
1892 tickdelay(DELAY_TICKS);
1893
1894 /* Wait for controller ready */
1895 if (!w_waitfor(STATUS_BSY, 0)) {
1896 printf("%s: reset failed, drive busy\n", w_name());
1897 return(ERR);
1898 }
1899
1900 /* The error register should be checked now, but some drives mess it up. */
1901
1902 for (wn = wini; wn < &wini[MAX_DRIVES]; wn++) {
1903 if (wn->base_cmd == w_wn->base_cmd) {
1904 wn->state &= ~DEAF;
1905 if (w_wn->irq_need_ack) {
1906 /* Make sure irq is actually enabled.. */
1907 sys_irqenable(&w_wn->irq_hook_id);
1908 }
1909 }
1910 }
1911
1912
1913 return(OK);
1914 }
1915
1916 /*===========================================================================*
1917 * w_intr_wait *
1918 *===========================================================================*/
1919 PRIVATE void w_intr_wait()
1920 {
1921 /* Wait for a task completion interrupt. */
1922
1923 int r;
1924 unsigned long w_status;
1925 message m;
1926
1927 if (w_wn->irq != NO_IRQ) {
1928 /* Wait for an interrupt that sets w_status to "not busy".
1929 * (w_timeout() also clears w_status.)
1930 */
1931 while (w_wn->w_status & (STATUS_ADMBSY|STATUS_BSY)) {
1932 int rr;
1933 if((rr=receive(ANY, &m)) != OK)
1934 panic("at_wini", "receive(ANY) failed", rr);
1935 switch(m.m_type) {
1936 case SYN_ALARM:
1937 /* Timeout. */
1938 w_timeout(); /* a.o. set w_status */
1939 break;
1940 case HARD_INT:
1941 /* Interrupt. */
1942 r= sys_inb(w_wn->base_cmd + REG_STATUS, &w_status);
1943 if (r != 0)
1944 panic("at_wini", "sys_inb failed", r);
1945 w_wn->w_status= w_status;
1946 ack_irqs(m.NOTIFY_ARG);
1947 break;
1948 case DEV_PING:
1949 /* RS monitor ping. */
1950 notify(m.m_source);
1951 break;
1952 default:
1953 /* unhandled message.
1954 * queue it and handle it in the libdriver loop.
1955 */
1956 mq_queue(&m);
1957 }
1958 }
1959 } else {
1960 /* Interrupt not yet allocated; use polling. */
1961 (void) w_waitfor(STATUS_BSY, 0);
1962 }
1963 }
1964
1965 /*===========================================================================*
1966 * at_intr_wait *
1967 *===========================================================================*/
1968 PRIVATE int at_intr_wait()
1969 {
1970 /* Wait for an interrupt, study the status bits and return error/success. */
1971 int r, s;
1972 unsigned long inbval;
1973
1974 w_intr_wait();
1975 if ((w_wn->w_status & (STATUS_BSY | STATUS_WF | STATUS_ERR)) == 0) {
1976 r = OK;
1977 } else {
1978 if ((s=sys_inb(w_wn->base_cmd + REG_ERROR, &inbval)) != OK)
1979 panic(w_name(),"Couldn't read register",s);
1980 if ((w_wn->w_status & STATUS_ERR) && (inbval & ERROR_BB)) {
1981 r = ERR_BAD_SECTOR; /* sector marked bad, retries won't help */
1982 } else {
1983 r = ERR; /* any other error */
1984 }
1985 }
1986 w_wn->w_status |= STATUS_ADMBSY; /* assume still busy with I/O */
1987 return(r);
1988 }
1989
1990 /*===========================================================================*
1991 * w_waitfor *
1992 *===========================================================================*/
1993 PRIVATE int w_waitfor(mask, value)
1994 int mask; /* status mask */
1995 int value; /* required status */
1996 {
1997 /* Wait until controller is in the required state. Return zero on timeout.
1998 * An alarm that set a timeout flag is used. TIMEOUT is in micros, we need
1999 * ticks. Disabling the alarm is not needed, because a static flag is used
2000 * and a leftover timeout cannot do any harm.
2001 */
2002 unsigned long w_status;
2003 clock_t t0, t1;
2004 int s;
2005
2006 getuptime(&t0);
2007 do {
2008 if ((s=sys_inb(w_wn->base_cmd + REG_STATUS, &w_status)) != OK)
2009 panic(w_name(),"Couldn't read register",s);
2010 w_wn->w_status= w_status;
2011 if ((w_wn->w_status & mask) == value) {
2012 return 1;
2013 }
2014 } while ((s=getuptime(&t1)) == OK && (t1-t0) < timeout_ticks );
2015 if (OK != s) printf("AT_WINI: warning, get_uptime failed: %d\n",s);
2016
2017 w_need_reset(); /* controller gone deaf */
2018 return(0);
2019 }
2020
2021 /*===========================================================================*
2022 * w_waitfor_dma *
2023 *===========================================================================*/
2024 PRIVATE int w_waitfor_dma(mask, value)
2025 int mask; /* status mask */
2026 int value; /* required status */
2027 {
2028 /* Wait until controller is in the required state. Return zero on timeout.
2029 * An alarm that set a timeout flag is used. TIMEOUT is in micros, we need
2030 * ticks. Disabling the alarm is not needed, because a static flag is used
2031 * and a leftover timeout cannot do any harm.
2032 */
2033 unsigned long w_status;
2034 clock_t t0, t1;
2035 int s;
2036
2037 getuptime(&t0);
2038 do {
2039 if ((s=sys_inb(w_wn->base_dma + DMA_STATUS, &w_status)) != OK)
2040 panic(w_name(),"Couldn't read register",s);
2041 if ((w_status & mask) == value) {
2042 return 1;
2043 }
2044 } while ((s=getuptime(&t1)) == OK && (t1-t0) < timeout_ticks );
2045 if (OK != s) printf("AT_WINI: warning, get_uptime failed: %d\n",s);
2046
2047 return(0);
2048 }
2049
2050 /*===========================================================================*
2051 * w_geometry *
2052 *===========================================================================*/
2053 PRIVATE void w_geometry(entry)
2054 struct partition *entry;
2055 {
2056 struct wini *wn = w_wn;
2057
2058 if (wn->state & ATAPI) { /* Make up some numbers. */
2059 entry->cylinders = div64u(wn->part[0].dv_size, SECTOR_SIZE) / (64*32);
2060 entry->heads = 64;
2061 entry->sectors = 32;
2062 } else { /* Return logical geometry. */
2063 entry->cylinders = wn->lcylinders;
2064 entry->heads = wn->lheads;
2065 entry->sectors = wn->lsectors;
2066 }
2067 }
2068
2069 #if ENABLE_ATAPI
2070 /*===========================================================================*
2071 * atapi_open *
2072 *===========================================================================*/
2073 PRIVATE int atapi_open()
2074 {
2075 /* Should load and lock the device and obtain its size. For now just set the
2076 * size of the device to something big. What is really needed is a generic
2077 * SCSI layer that does all this stuff for ATAPI and SCSI devices (kjb). (XXX)
2078 */
2079 w_wn->part[0].dv_size = mul64u(800L*1024, 1024);
2080 return(OK);
2081 }
2082
2083 /*===========================================================================*
2084 * atapi_close *
2085 *===========================================================================*/
2086 PRIVATE void atapi_close()
2087 {
2088 /* Should unlock the device. For now do nothing. (XXX) */
2089 }
2090
2091 void sense_request(void)
2092 {
2093 int r, i;
2094 static u8_t sense[100], packet[ATAPI_PACKETSIZE];
2095
2096 packet[0] = SCSI_SENSE;
2097 packet[1] = 0;
2098 packet[2] = 0;
2099 packet[3] = 0;
2100 packet[4] = SENSE_PACKETSIZE;
2101 packet[5] = 0;
2102 packet[7] = 0;
2103 packet[8] = 0;
2104 packet[9] = 0;
2105 packet[10] = 0;
2106 packet[11] = 0;
2107
2108 for(i = 0; i < SENSE_PACKETSIZE; i++) sense[i] = 0xff;
2109 r = atapi_sendpacket(packet, SENSE_PACKETSIZE);
2110 if (r != OK) { printf("request sense command failed\n"); return; }
2111 if (atapi_intr_wait() <= 0) { printf("WARNING: request response failed\n"); }
2112
2113 if (sys_insw(w_wn->base_cmd + REG_DATA, SELF, (void *) sense, SENSE_PACKETSIZE) != OK)
2114 printf("WARNING: sense reading failed\n");
2115
2116 printf("sense data:");
2117 for(i = 0; i < SENSE_PACKETSIZE; i++) printf(" %02x", sense[i]);
2118 printf("\n");
2119 }
2120
2121 /*===========================================================================*
2122 * atapi_transfer *
2123 *===========================================================================*/
2124 PRIVATE int atapi_transfer(proc_nr, opcode, position, iov, nr_req, safe)
2125 int proc_nr; /* process doing the request */
2126 int opcode; /* DEV_GATHER_S or DEV_SCATTER_S */
2127 u64_t position; /* offset on device to read or write */
2128 iovec_t *iov; /* pointer to read or write request vector */
2129 unsigned nr_req; /* length of request vector */
2130 int safe; /* use safecopies? */
2131 {
2132 struct wini *wn = w_wn;
2133 iovec_t *iop, *iov_end = iov + nr_req;
2134 int r, s, errors, fresh;
2135 u64_t pos;
2136 unsigned long block;
2137 u64_t dv_size = w_dv->dv_size;
2138 unsigned nbytes, nblocks, count, before, chunk;
2139 static u8_t packet[ATAPI_PACKETSIZE];
2140 size_t addr_offset = 0;
2141
2142 errors = fresh = 0;
2143
2144 while (nr_req > 0 && !fresh) {
2145 /* The Minix block size is smaller than the CD block size, so we
2146 * may have to read extra before or after the good data.
2147 */
2148 pos = add64(w_dv->dv_base, position);
2149 block = div64u(pos, CD_SECTOR_SIZE);
2150 before = rem64u(pos, CD_SECTOR_SIZE);
2151
2152 /* How many bytes to transfer? */
2153 nbytes = count = 0;
2154 for (iop = iov; iop < iov_end; iop++) {
2155 nbytes += iop->iov_size;
2156 if ((before + nbytes) % CD_SECTOR_SIZE == 0) count = nbytes;
2157 }
2158
2159 /* Does one of the memory chunks end nicely on a CD sector multiple? */
2160 if (count != 0) nbytes = count;
2161
2162 /* Data comes in as words, so we have to enforce even byte counts. */
2163 if ((before | nbytes) & 1) return(EINVAL);
2164
2165 /* Which block on disk and how close to EOF? */
2166 if (cmp64(position, dv_size) >= 0) return(OK); /* At EOF */
2167 if (cmp64(add64ul(position, nbytes), dv_size) > 0)
2168 nbytes = diff64(dv_size, position);
2169
2170 nblocks = (before + nbytes + CD_SECTOR_SIZE - 1) / CD_SECTOR_SIZE;
2171 if (ATAPI_DEBUG) {
2172 printf("block=%lu, before=%u, nbytes=%u, nblocks=%u\n",
2173 block, before, nbytes, nblocks);
2174 }
2175
2176 /* First check to see if a reinitialization is needed. */
2177 if (!(wn->state & INITIALIZED) && w_specify() != OK) return(EIO);
2178
2179 /* Build an ATAPI command packet. */
2180 packet[0] = SCSI_READ10;
2181 packet[1] = 0;
2182 packet[2] = (block >> 24) & 0xFF;
2183 packet[3] = (block >> 16) & 0xFF;
2184 packet[4] = (block >> 8) & 0xFF;
2185 packet[5] = (block >> 0) & 0xFF;
2186 packet[6] = 0;
2187 packet[7] = (nblocks >> 8) & 0xFF;
2188 packet[8] = (nblocks >> 0) & 0xFF;
2189 packet[9] = 0;
2190 packet[10] = 0;
2191 packet[11] = 0;
2192
2193 /* Tell the controller to execute the packet command. */
2194 r = atapi_sendpacket(packet, nblocks * CD_SECTOR_SIZE);
2195 if (r != OK) goto err;
2196
2197 /* Read chunks of data. */
2198 while ((r = atapi_intr_wait()) > 0) {
2199 count = r;
2200
2201 if (ATAPI_DEBUG) {
2202 printf("before=%u, nbytes=%u, count=%u\n",
2203 before, nbytes, count);
2204 }
2205
2206 while (before > 0 && count > 0) { /* Discard before. */
2207 chunk = before;
2208 if (chunk > count) chunk = count;
2209 if (chunk > DMA_BUF_SIZE) chunk = DMA_BUF_SIZE;
2210 if ((s=sys_insw(wn->base_cmd + REG_DATA, SELF, tmp_buf, chunk)) != OK)
2211 panic(w_name(),"Call to sys_insw() failed", s);
2212 before -= chunk;
2213 count -= chunk;
2214 }
2215
2216 while (nbytes > 0 && count > 0) { /* Requested data. */
2217 chunk = nbytes;
2218 if (chunk > count) chunk = count;
2219 if (chunk > iov->iov_size) chunk = iov->iov_size;
2220 if(safe) {
2221 s=sys_safe_insw(wn->base_cmd + REG_DATA, proc_nr,
2222 (void *) iov->iov_addr, addr_offset, chunk);
2223 } else {
2224 s=sys_insw(wn->base_cmd + REG_DATA, proc_nr,
2225 (void *) (iov->iov_addr + addr_offset), chunk);
2226 }
2227 if (s != OK)
2228 panic(w_name(),"Call to sys_insw() failed", s);
2229 position= add64ul(position, chunk);
2230 nbytes -= chunk;
2231 count -= chunk;
2232 addr_offset += chunk;
2233 fresh = 0;
2234 if ((iov->iov_size -= chunk) == 0) {
2235 iov++;
2236 nr_req--;
2237 fresh = 1; /* new element is optional */
2238 addr_offset = 0;
2239 }
2240 }
2241
2242 while (count > 0) { /* Excess data. */
2243 chunk = count;
2244 if (chunk > DMA_BUF_SIZE) chunk = DMA_BUF_SIZE;
2245 if ((s=sys_insw(wn->base_cmd + REG_DATA, SELF, tmp_buf, chunk)) != OK)
2246 panic(w_name(),"Call to sys_insw() failed", s);
2247 count -= chunk;
2248 }
2249 }
2250
2251 if (r < 0) {
2252 err: /* Don't retry if too many errors. */
2253 if (atapi_debug) sense_request();
2254 if (++errors == max_errors) {
2255 w_command = CMD_IDLE;
2256 if (atapi_debug) printf("giving up (%d)\n", errors);
2257 return(EIO);
2258 }
2259 if (atapi_debug) printf("retry (%d)\n", errors);
2260 }
2261 }
2262
2263 w_command = CMD_IDLE;
2264 return(OK);
2265 }
2266
2267 /*===========================================================================*
2268 * atapi_sendpacket *
2269 *===========================================================================*/
2270 PRIVATE int atapi_sendpacket(packet, cnt)
2271 u8_t *packet;
2272 unsigned cnt;
2273 {
2274 /* Send an Atapi Packet Command */
2275 struct wini *wn = w_wn;
2276 pvb_pair_t outbyte[6]; /* vector for sys_voutb() */
2277 int s;
2278
2279 if (wn->state & IGNORING) return ERR;
2280
2281 /* Select Master/Slave drive */
2282 if ((s=sys_outb(wn->base_cmd + REG_DRIVE, wn->ldhpref)) != OK)
2283 panic(w_name(),"Couldn't select master/ slave drive",s);
2284
2285 if (!w_waitfor(STATUS_BSY | STATUS_DRQ, 0)) {
2286 printf("%s: atapi_sendpacket: drive not ready\n", w_name());
2287 return(ERR);
2288 }
2289
2290 /* Schedule a wakeup call, some controllers are flaky. This is done with
2291 * a synchronous alarm. If a timeout occurs a SYN_ALARM message is sent
2292 * from HARDWARE, so that w_intr_wait() can call w_timeout() in case the
2293 * controller was not able to execute the command. Leftover timeouts are
2294 * simply ignored by the main loop.
2295 */
2296 sys_setalarm(wakeup_ticks, 0);
2297
2298 #if _WORD_SIZE > 2
2299 if (cnt > 0xFFFE) cnt = 0xFFFE; /* Max data per interrupt. */
2300 #endif
2301
2302 w_command = ATAPI_PACKETCMD;
2303 pv_set(outbyte[0], wn->base_cmd + REG_FEAT, 0);
2304 pv_set(outbyte[1], wn->base_cmd + REG_IRR, 0);
2305 pv_set(outbyte[2], wn->base_cmd + REG_SAMTAG, 0);
2306 pv_set(outbyte[3], wn->base_cmd + REG_CNT_LO, (cnt >> 0) & 0xFF);
2307 pv_set(outbyte[4], wn->base_cmd + REG_CNT_HI, (cnt >> 8) & 0xFF);
2308 pv_set(outbyte[5], wn->base_cmd + REG_COMMAND, w_command);
2309 if (atapi_debug) printf("cmd: %x ", w_command);
2310 if ((s=sys_voutb(outbyte,6)) != OK)
2311 panic(w_name(),"Couldn't write registers with sys_voutb()",s);
2312
2313 if (!w_waitfor(STATUS_BSY | STATUS_DRQ, STATUS_DRQ)) {
2314 printf("%s: timeout (BSY|DRQ -> DRQ)\n", w_name());
2315 return(ERR);
2316 }
2317 wn->w_status |= STATUS_ADMBSY; /* Command not at all done yet. */
2318
2319 /* Send the command packet to the device. */
2320 if ((s=sys_outsw(wn->base_cmd + REG_DATA, SELF, packet, ATAPI_PACKETSIZE)) != OK)
2321 panic(w_name(),"sys_outsw() failed", s);
2322
2323 {
2324 int p;
2325 if (atapi_debug) {
2326 printf("sent command:");
2327 for(p = 0; p < ATAPI_PACKETSIZE; p++) { printf(" %02x", packet[p]); }
2328 printf("\n");
2329 }
2330 }
2331 return(OK);
2332 }
2333
2334
2335 #endif /* ENABLE_ATAPI */
2336
2337 /*===========================================================================*
2338 * w_other *
2339 *===========================================================================*/
2340 PRIVATE int w_other(dr, m, safe)
2341 struct driver *dr;
2342 message *m;
2343 int safe;
2344 {
2345 int r, timeout, prev;
2346
2347 if (m->m_type != DEV_IOCTL_S )
2348 return EINVAL;
2349
2350 if (m->REQUEST == DIOCTIMEOUT) {
2351 if(safe) {
2352 r= sys_safecopyfrom(m->IO_ENDPT, (vir_bytes) m->IO_GRANT,
2353 0, (vir_bytes)&timeout, sizeof(timeout), D);
2354 } else {
2355 r= sys_datacopy(m->IO_ENDPT, (vir_bytes)m->ADDRESS,
2356 SELF, (vir_bytes)&timeout, sizeof(timeout));
2357 }
2358
2359 if(r != OK)
2360 return r;
2361
2362 if (timeout == 0) {
2363 /* Restore defaults. */
2364 timeout_ticks = DEF_TIMEOUT_TICKS;
2365 max_errors = MAX_ERRORS;
2366 wakeup_ticks = WAKEUP;
2367 w_silent = 0;
2368 } else if (timeout < 0) {
2369 return EINVAL;
2370 } else {
2371 prev = wakeup_ticks;
2372
2373 if (!w_standard_timeouts) {
2374 /* Set (lower) timeout, lower error
2375 * tolerance and set silent mode.
2376 */
2377 wakeup_ticks = timeout;
2378 max_errors = 3;
2379 w_silent = 1;
2380
2381 if (timeout_ticks > timeout)
2382 timeout_ticks = timeout;
2383 }
2384
2385 if(safe) {
2386 r= sys_safecopyto(m->IO_ENDPT,
2387 (vir_bytes) m->IO_GRANT,
2388 0, (vir_bytes)&prev, sizeof(prev), D);
2389 } else {
2390 r=sys_datacopy(SELF, (vir_bytes)&prev,
2391 m->IO_ENDPT, (vir_bytes)m->ADDRESS,
2392 sizeof(prev));
2393 }
2394
2395 if(r != OK)
2396 return r;
2397 }
2398
2399 return OK;
2400 } else if (m->REQUEST == DIOCOPENCT) {
2401 int count;
2402 if (w_prepare(m->DEVICE) == NIL_DEV) return ENXIO;
2403 count = w_wn->open_ct;
2404 if(safe) {
2405 r= sys_safecopyto(m->IO_ENDPT, (vir_bytes) m->IO_GRANT,
2406 0, (vir_bytes)&count, sizeof(count), D);
2407 } else {
2408 r=sys_datacopy(SELF, (vir_bytes)&count,
2409 m->IO_ENDPT, (vir_bytes)m->ADDRESS, sizeof(count));
2410 }
2411
2412 if(r != OK)
2413 return r;
2414
2415 return OK;
2416 }
2417 return EINVAL;
2418 }
2419
2420 /*===========================================================================*
2421 * w_hw_int *
2422 *===========================================================================*/
2423 PRIVATE int w_hw_int(dr, m)
2424 struct driver *dr;
2425 message *m;
2426 {
2427 /* Leftover interrupt(s) received; ack it/them. */
2428 ack_irqs(m->NOTIFY_ARG);
2429
2430 return OK;
2431 }
2432
2433
2434 /*===========================================================================*
2435 * ack_irqs *
2436 *===========================================================================*/
2437 PRIVATE void ack_irqs(unsigned int irqs)
2438 {
2439 unsigned int drive;
2440 unsigned long w_status;
2441
2442 for (drive = 0; drive < MAX_DRIVES && irqs; drive++) {
2443 if (!(wini[drive].state & IGNORING) && wini[drive].irq_need_ack &&
2444 (wini[drive].irq_mask & irqs)) {
2445 if (sys_inb((wini[drive].base_cmd + REG_STATUS),
2446 &w_status) != OK)
2447 {
2448 panic(w_name(), "couldn't ack irq on drive %d\n",
2449 drive);
2450 }
2451 wini[drive].w_status= w_status;
2452 if (sys_irqenable(&wini[drive].irq_hook_id) != OK)
2453 printf("couldn't re-enable drive %d\n", drive);
2454 irqs &= ~wini[drive].irq_mask;
2455 }
2456 }
2457 }
2458
2459
2460 #define STSTR(a) if (status & STATUS_ ## a) { strcat(str, #a); strcat(str, " "); }
2461 #define ERRSTR(a) if (e & ERROR_ ## a) { strcat(str, #a); strcat(str, " "); }
2462 char *strstatus(int status)
2463 {
2464 static char str[200];
2465 str[0] = '\0';
2466
2467 STSTR(BSY);
2468 STSTR(DRDY);
2469 STSTR(DMADF);
2470 STSTR(SRVCDSC);
2471 STSTR(DRQ);
2472 STSTR(CORR);
2473 STSTR(CHECK);
2474 return str;
2475 }
2476
2477 char *strerr(int e)
2478 {
2479 static char str[200];
2480 str[0] = '\0';
2481
2482 ERRSTR(BB);
2483 ERRSTR(ECC);
2484 ERRSTR(ID);
2485 ERRSTR(AC);
2486 ERRSTR(TK);
2487 ERRSTR(DM);
2488
2489 return str;
2490 }
2491
2492 #if ENABLE_ATAPI
2493
2494 /*===========================================================================*
2495 * atapi_intr_wait *
2496 *===========================================================================*/
2497 PRIVATE int atapi_intr_wait()
2498 {
2499 /* Wait for an interrupt and study the results. Returns a number of bytes
2500 * that need to be transferred, or an error code.
2501 */
2502 struct wini *wn = w_wn;
2503 pvb_pair_t inbyte[4]; /* vector for sys_vinb() */
2504 int s; /* status for sys_vinb() */
2505 int e;
2506 int len;
2507 int irr;
2508 int r;
2509 int phase;
2510
2511 w_intr_wait();
2512
2513 /* Request series of device I/O. */
2514 inbyte[0].port = wn->base_cmd + REG_ERROR;
2515 inbyte[1].port = wn->base_cmd + REG_CNT_LO;
2516 inbyte[2].port = wn->base_cmd + REG_CNT_HI;
2517 inbyte[3].port = wn->base_cmd + REG_IRR;
2518 if ((s=sys_vinb(inbyte, 4)) != OK)
2519 panic(w_name(),"ATAPI failed sys_vinb()", s);
2520 e = inbyte[0].value;
2521 len = inbyte[1].value;
2522 len |= inbyte[2].value << 8;
2523 irr = inbyte[3].value;
2524
2525 #if ATAPI_DEBUG
2526 printf("wn %p S=%x=%s E=%02x=%s L=%04x I=%02x\n", wn, wn->w_status, strstatus(wn->w_status), e, strerr(e), len, irr);
2527 #endif
2528 if (wn->w_status & (STATUS_BSY | STATUS_CHECK)) {
2529 if (atapi_debug) {
2530 printf("atapi fail: S=%x=%s E=%02x=%s L=%04x I=%02x\n", wn->w_status, strstatus(wn->w_status), e, strerr(e), len, irr);
2531 }
2532 return ERR;
2533 }
2534
2535 phase = (wn->w_status & STATUS_DRQ) | (irr & (IRR_COD | IRR_IO));
2536
2537 switch (phase) {
2538 case IRR_COD | IRR_IO:
2539 if (ATAPI_DEBUG) printf("ACD: Phase Command Complete\n");
2540 r = OK;
2541 break;
2542 case 0:
2543 if (ATAPI_DEBUG) printf("ACD: Phase Command Aborted\n");
2544 r = ERR;
2545 break;
2546 case STATUS_DRQ | IRR_COD:
2547 if (ATAPI_DEBUG) printf("ACD: Phase Command Out\n");
2548 r = ERR;
2549 break;
2550 case STATUS_DRQ:
2551 if (ATAPI_DEBUG) printf("ACD: Phase Data Out %d\n", len);
2552 r = len;
2553 break;
2554 case STATUS_DRQ | IRR_IO:
2555 if (ATAPI_DEBUG) printf("ACD: Phase Data In %d\n", len);
2556 r = len;
2557 break;
2558 default:
2559 if (ATAPI_DEBUG) printf("ACD: Phase Unknown\n");
2560 r = ERR;
2561 break;
2562 }
2563
2564 #if 0
2565 /* retry if the media changed */
2566 XXX while (phase == (IRR_IO | IRR_COD) && (wn->w_status & STATUS_CHECK)
2567 && (e & ERROR_SENSE) == SENSE_UATTN && --try > 0);
2568 #endif
2569
2570 wn->w_status |= STATUS_ADMBSY; /* Assume not done yet. */
2571 return(r);
2572 }
2573
2574 #endif /* ENABLE_ATAPI */
2575
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