minix/drivers/bus/i2c/arch/earm/omap_i2c_registers.h

   1 #ifndef _OMAP_I2C_REGISTERS_H
   2 #define _OMAP_I2C_REGISTERS_H
   3
   4 /* I2C Addresses for am335x (BeagleBone White / BeagleBone Black) */
   5
   6 /* IRQ Numbers */
   7 #define AM335X_I2C0_IRQ 70
   8 #define AM335X_I2C1_IRQ 71
   9 #define AM335X_I2C2_IRQ 30
  10
  11 /* Base Addresses */
  12 #define AM335X_I2C0_BASE 0x44e0b000
  13 #define AM335X_I2C1_BASE 0x4802a000
  14 #define AM335X_I2C2_BASE 0x4819c000
  15
  16 /* Size of I2C Register Address Range */
  17 #define AM335X_I2C0_SIZE 0x1000
  18 #define AM335X_I2C1_SIZE 0x1000
  19 #define AM335X_I2C2_SIZE 0x1000
  20
  21 /* Register Offsets */
  22 #define AM335X_I2C_REVNB_LO        0x00
  23 #define AM335X_I2C_REVNB_HI        0x04
  24 #define AM335X_I2C_SYSC            0x10
  25 #define AM335X_I2C_IRQSTATUS_RAW   0x24
  26 #define AM335X_I2C_IRQSTATUS       0x28
  27 #define AM335X_I2C_IRQENABLE_SET   0x2c
  28 #define AM335X_I2C_IRQENABLE_CLR   0x30
  29 #define AM335X_I2C_WE              0x34
  30 #define AM335X_I2C_DMARXENABLE_SET 0x38
  31 #define AM335X_I2C_DMATXENABLE_SET 0x3c
  32 #define AM335X_I2C_DMARXENABLE_CLR 0x40
  33 #define AM335X_I2C_DMATXENABLE_CLR 0x44
  34 #define AM335X_I2C_DMARXWAKE_EN    0x48
  35 #define AM335X_I2C_DMATXWAKE_EN    0x4c
  36 #define AM335X_I2C_SYSS            0x90
  37 #define AM335X_I2C_BUF             0x94
  38 #define AM335X_I2C_CNT             0x98
  39 #define AM335X_I2C_DATA            0x9c
  40 #define AM335X_I2C_CON             0xa4
  41 #define AM335X_I2C_OA              0xa8
  42 #define AM335X_I2C_SA              0xac
  43 #define AM335X_I2C_PSC             0xb0
  44 #define AM335X_I2C_SCLL            0xb4
  45 #define AM335X_I2C_SCLH            0xb8
  46 #define AM335X_I2C_SYSTEST         0xbc
  47 #define AM335X_I2C_BUFSTAT         0xc0
  48 #define AM335X_I2C_OA1             0xc4
  49 #define AM335X_I2C_OA2             0xc8
  50 #define AM335X_I2C_OA3             0xcc
  51 #define AM335X_I2C_ACTOA           0xd0
  52 #define AM335X_I2C_SBLOCK          0xd4
  53
  54 /* Constants */
  55 #define AM335X_FUNCTIONAL_CLOCK 96000000 /* 96 MHz */
  56 #define AM335X_MODULE_CLOCK 12000000    /* 12 MHz */
  57
  58 /* I2C_REV value found on the BeagleBone / BeagleBone Black */
  59 #define AM335X_REV_MAJOR 0x00
  60 #define AM335X_REV_MINOR 0x0b
  61
  62 /* I2C Addresses for dm37xx (BeagleBoard-xM) */
  63
  64 /* IRQ Numbers */
  65 #define DM37XX_I2C0_IRQ 56
  66 #define DM37XX_I2C1_IRQ 57
  67 #define DM37XX_I2C2_IRQ 61
  68
  69 /* Base Addresses */
  70 #define DM37XX_I2C0_BASE 0x48070000
  71 #define DM37XX_I2C1_BASE 0x48072000
  72 #define DM37XX_I2C2_BASE 0x48060000
  73
  74 /* Size of I2C Register Address Range */
  75 #define DM37XX_I2C0_SIZE 0x1000
  76 #define DM37XX_I2C1_SIZE 0x1000
  77 #define DM37XX_I2C2_SIZE 0x1000
  78
  79 /* Register Offsets */
  80 #define DM37XX_I2C_REV     0x00
  81 #define DM37XX_I2C_IE      0x04
  82 #define DM37XX_I2C_STAT    0x08
  83 #define DM37XX_I2C_WE      0x0C
  84 #define DM37XX_I2C_SYSS    0x10
  85 #define DM37XX_I2C_BUF     0x14
  86 #define DM37XX_I2C_CNT     0x18
  87 #define DM37XX_I2C_DATA    0x1c
  88 #define DM37XX_I2C_SYSC    0x20
  89 #define DM37XX_I2C_CON     0x24
  90 #define DM37XX_I2C_OA0     0x28
  91 #define DM37XX_I2C_SA      0x2c
  92 #define DM37XX_I2C_PSC     0x30
  93 #define DM37XX_I2C_SCLL    0x34
  94 #define DM37XX_I2C_SCLH    0x38
  95 #define DM37XX_I2C_SYSTEST 0x3c
  96 #define DM37XX_I2C_BUFSTAT 0x40
  97 #define DM37XX_I2C_OA1     0x44
  98 #define DM37XX_I2C_OA2     0x48
  99 #define DM37XX_I2C_OA3     0x4c
 100 #define DM37XX_I2C_ACTOA   0x50
 101 #define DM37XX_I2C_SBLOCK  0x54
 102
 103 /* Constants */
 104 #define DM37XX_FUNCTIONAL_CLOCK 96000000 /* 96 MHz */
 105 #define DM37XX_MODULE_CLOCK 19200000    /* 19.2 MHz */
 106
 107 #define DM37XX_REV_MAJOR 0x04
 108 #define DM37XX_REV_MINOR 0x00
 109
 110 /* Shared Values */
 111
 112 #define BUS_SPEED_100KHz 100000 /* 100 KHz */
 113 #define BUS_SPEED_400KHz 400000 /* 400 KHz */
 114 #define I2C_OWN_ADDRESS 0x01
 115
 116 /* Masks */
 117
 118 #define MAX_I2C_SA_MASK (0x3ff) /* Highest 10 bit address -- 9..0 */
 119
 120 /* Bit Offsets within Registers (only those used are listed) */
 121
 122 /* Same offsets for both dm37xx and am335x */
 123
 124 #define I2C_EN 15 /* I2C_CON */
 125 #define MST    10 /* I2C_CON */
 126 #define TRX     9 /* I2C_CON */
 127 #define XSA     8 /* I2C_CON */
 128 #define STP     1 /* I2C_CON */
 129 #define STT     0 /* I2C_CON */
 130
 131 #define CLKACTIVITY_S 9 /* I2C_SYSC */
 132 #define CLKACTIVITY_I 8 /* I2C_SYSC */
 133 #define SMART_WAKE_UP 4 /* I2C_SYSC */
 134 #define NO_IDLE_MODE 3 /* I2C_SYSC */
 135 #define SRST     1 /* I2C_SYSC */
 136 #define AUTOIDLE 0 /* I2C_SYSC */
 137
 138 #define RDONE 0 /* I2C_SYSS */
 139
 140 #define RXFIFO_CLR 14 /* I2C_BUF */
 141 #define TXFIFO_CLR  6 /* I2C_BUF */
 142
 143 #define BB   12 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */
 144 #define ROVR 11 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */
 145 #define AERR  7 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */
 146 #define XRDY  4 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */
 147 #define RRDY  3 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */
 148 #define ARDY  2 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */
 149 #define NACK  1 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */
 150 #define AL    0 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */
 151
 152 #endif /* _OMAP_I2C_REGISTERS_H */