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Remove building with NOCRYPTO option
[minix3.git] / minix / drivers / net / fxp / fxp.h
blob5c64f222dfec18c8115b52b7b7d2e88291d3a3f6
1 /*
2 ibm/fxp.h
3
4 Registers and datastructures of the Intel 82557, 82558, 82559, 82550,
5 and 82562 fast ethernet controllers.
6
7 Created: Nov 2004 by Philip Homburg <philip@f-mnx.phicoh.com>
8 */
9
10 #ifndef _FXP_FXP_H
11 #define _FXP_FXP_H
12
13 #define VERBOSE 0 /* display output during intialization */
14
15 /* Revisions in PCI_REV */
16 #define FXP_REV_82557A 0x01
17 #define FXP_REV_82557B 0x02
18 #define FXP_REV_82557C 0x03
19 #define FXP_REV_82558A 0x04
20 #define FXP_REV_82558B 0x05
21 #define FXP_REV_82559A 0x06
22 #define FXP_REV_82559B 0x07
23 #define FXP_REV_82559C 0x08
24 #define FXP_REV_82559ERA 0x09
25 #define FXP_REV_82550_1 0x0C
26 #define FXP_REV_82550_2 0x0D
27 #define FXP_REV_82550_3 0x0E
28 #define FXP_REV_82551_1 0x0F
29 #define FXP_REV_82551_2 0x10
30 #define FXP_REV_82801CAM 0x42
31 #define FXP_REV_82801DB 0x81
32 #define FXP_REV_82550_4 0x83
33
34 /* Control/Status Registers (CSR). The first 8 bytes are called
35 * System Control Block (SCB)
36 */
37 #define SCB_STATUS 0x00 /* Lower half of the SCB status word. CU and
38 * RU status.
39 */
40 #define SS_CUS_MASK 0xC0 /* CU Status */
41 #define SS_CU_IDLE 0x00 /* Idle */
42 #define SS_CU_SUSP 0x40 /* Suspended */
43 #define SS_CU_LPQA 0x80 /* LPQ Active */
44 #define SS_CU_HQPA 0xC0 /* HQP Active */
45 #define SS_RUS_MASK 0x3C /* RU Status */
46 #define SS_RU_IDLE 0x00 /* Idle */
47 #define SS_RU_SUSP 0x04 /* Suspended */
48 #define SS_RU_NORES 0x08 /* No Resources */
49 #define SS_RU_READY 0x10 /* Ready */
50 /* Other values are reserved */
51 #define SS_RESERVED 0x03 /* Reserved */
52 #define SCB_INT_STAT 0x01 /* Upper half of the SCB status word.
53 * Interrupt status. Also used to acknoledge
54 * interrupts.
55 */
56 #define SIS_CX 0x80 /* CU command with interrupt bit set. On
57 * 82557 also TNO Interrupt.
58 */
59 #define SIS_FR 0x40 /* Frame Received */
60 #define SIS_CNA 0x20 /* CU Not Active */
61 #define SIS_RNR 0x10 /* RU Not Ready */
62 #define SIS_MDI 0x08 /* MDI read/write cycle completed */
63 #define SIS_SWI 0x04 /* Software Interrupt */
64 #define SIS_RES 0x02 /* Reserved */
65 #define SIS_FCP 0x01 /* Flow Control Pause Interrupt (82558 and
66 * later, reserved on 82557)
67 */
68 #define SCB_CMD 0x02 /* Lower half of the SCB command word. CU and
69 * RU commands.
70 */
71 #define SC_CUC_MASK 0xF0
72 #define SC_CU_NOP 0x00 /* NOP */
73 #define SC_CU_START 0x10 /* Start CU */
74 #define SC_CU_RESUME 0x20 /* Resume CU */
75 #define SC_CU_LOAD_DCA 0x40 /* Load Dump Counters Address */
76 #define SC_CU_DUMP_SC 0x50 /* Dump Statistical Counters */
77 #define SC_CU_LOAD_BASE 0x60 /* Load CU Base */
78 #define SC_CU_DUMP_RSET_SC 0x70 /* Dump and Reset Counters */
79 #define SC_CU_STATIC_RESUME 0xA0 /* Static Resume, 82558 and
80 * above
81 */
82 #define SC_RESERVED 0x08 /* Reserved */
83 #define SC_RUC_MASK 0x07 /* RU Command Mask */
84 #define SC_RU_NOP 0x00 /* NOP */
85 #define SC_RU_START 0x01 /* Start RU */
86 #define SC_RU_RESUME 0x02 /* Resume RU */
87 #define SC_RU_DMA_REDIR 0x03 /* DMA Redirect */
88 #define SC_RU_ABORT 0x04 /* Abort RU */
89 #define SC_RU_LOAD_HDR 0x05 /* Load Header Data Size */
90 #define SC_RU_LOAD_BASE 0x06 /* Load RU Base */
91 #define SCB_INT_MASK 0x03 /* Upper half of the SCB command word.
92 * Interrupt mask. Can also be used to
93 * generate a 'software' interrupt.
94 */
95 /* The following 6 mask bits are not valid on
96 * the 82557.
97 */
98 #define SIM_CX 0x80 /* Mask CX */
99 #define SIM_FR 0x40 /* Mask FR */
100 #define SIM_CNA 0x20 /* Mask CNA */
101 #define SIM_RNR 0x10 /* Mask RNR */
102 #define SIM_ER 0x08 /* Mask ER */
103 #define SIM_FCP 0x04 /* Mask FCP */
104 #define SIM_SI 0x02 /* Generate Software Interrupt */
105 #define SIM_M 0x01 /* Mask all interrupts */
106 #define SCB_POINTER 0x04 /* A 32-bit (pointer) argument for CU and RU
107 * commands.
108 */
109 #define CSR_PORT 0x08 /* Control functions that bypass the SCB */
110 #define CP_PTR_MASK 0xFFFFFFF0 /* Argument pointer */
111 #define CP_CMD_MASK 0x0000000F /* Commands bits */
112 #define CP_CMD_SOFT_RESET 0x00000000 /* Software reset */
113 #define CSR_PORT_RESET_DELAY 10 /* Wait for reset to
114 * complete. In micro
115 * seconds.
116 */
117 #define CP_CMD_SELF_TEST 0x00000001 /* Self test */
118 #define CP_CMD_SEL_RESET 0x00000002 /* Selective reset */
119 #define CP_CMD_DUMP 0x00000003 /* Dump */
120 #define CP_CMD_DUMP_WAKEUP 0x00000007 /* Dump and wake-up,
121 * 82559 and later.
122 */
123 #define CSR_RESERVED 0x0C /* reserved, 16-bits */
124 #define CSR_EEPROM 0x0E /* EEPROM Control Register */
125 #define CE_RESERVED 0xF0 /* Reserved */
126 #define CE_EEDO 0x08 /* Serial Data Out (of the EEPROM) */
127 #define CE_EEDI 0x04 /* Serial Data In (to the EEPROM) */
128 #define CE_EECS 0x02 /* Chip Select */
129 #define CE_EESK 0x01 /* Serial Clock */
130 #define CSR_RESERVED1 0x0F /* Reserved */
131 #define CSR_MDI_CTL 0x10 /* MDI Control Register, 32-bits */
132 #define CM_RESERVED 0xC0000000 /* Reserved */
133 #define CM_IE 0x20000000 /* Enable Interrupt */
134 #define CM_READY 0x10000000 /* Command completed */
135 #define CM_OPCODE_MASK 0x0C000000 /* Opcode */
136 #define CM_WRITE 0x04000000 /* Write */
137 #define CM_READ 0x08000000 /* Read */
138 #define CM_PHYADDR_MASK 0x03E00000 /* Which PHY */
139 #define CM_PHYADDR_SHIFT 21
140 #define CM_REG_MASK 0x001F0000 /* Which register in the PHY */
141 #define CM_REG_SHIFT 16
142 #define CM_DATA_MASK 0x0000FFFF /* Data to be read or written */
143
144 /* Control Block List (CBL) commands */
145 #define CBL_NOP 0 /* No-operation */
146 #define CBL_AIS 1 /* Individual Address Setup */
147 #define CBL_CONF 2 /* Configure NIC */
148 #define CBL_MAS 3 /* Multicast Address Setup */
149 #define CBL_XMIT 4 /* Transmit */
150 #define CBL_LM 5 /* Load Microcode */
151 #define CBL_DUMP 6 /* Dump Internal Registers */
152 #define CBL_DIAG 7 /* Diagnose Command */
153
154 /* Common command fields */
155 #define CBL_C_CMD_MASK 0x0007 /* Command bits */
156 #define CBL_C_EL 0x8000 /* End of CBL */
157 #define CBL_C_S 0x4000 /* Suspend after the completion of the CB */
158 #define CBL_C_I 0x2000 /* Request CX Interrupt */
159 #define CBL_C_RES 0x1FF8 /* Reserved */
160
161 /* Command flags */
162 #define CBL_F_C 0x8000 /* Command has completed */
163 #define CBL_F_RES1 0x4000 /* Reserved */
164 #define CBL_F_OK 0x2000 /* Command was executed without errors */
165 #define CBL_F_RES0 0x1FFF /* Reserved */
166
167 /* Individual Address Setup (1) */
168 struct ias
169 {
170 u16_t ias_status;
171 u16_t ias_command;
172 u32_t ias_linkaddr;
173 u8_t ias_ethaddr[6];
174 u8_t ias_reserved[2];
175 };
176
177 /* Configure (2) */
178 #define CC_BYTES_NR 22 /* Number of configuration bytes */
179 struct cbl_conf
180 {
181 u16_t cc_status;
182 u16_t cc_command;
183 u32_t cc_linkaddr;
184 u8_t cc_bytes[CC_BYTES_NR];
185 };
186
187 /* Byte 0 */
188 #define CCB0_RES 0xC0 /* Reserved (0) */
189 #define CCB0_BYTECOUNT 0x3F /* Byte Count (typically either 8 or 22) */
190
191 /* Byte 1 */
192 #define CCB1_RES 0x80 /* Reserved (0) */
193 #define CCB1_TXFIFO_LIM 0x70 /* Transmit FIFO Limit, in DWORDS */
194 #define CTL_DEFAULT 0x00 /* 0 bytes */
195 #define CCB1_RXFIFO_LIM 0x0F /* Receive FIFO Limit */
196 #define CRL_DEFAULT 0x08 /* 32 bytes on 82557, 64 bytes on
197 * 82558/82559.
198 */
199
200 /* Byte 2 */
201 #define CCB2_AIFS 0xFF /* Adaptive IFS */
202 #define CAI_DEFAULT 0
203
204 /* Byte 3 */
205 /* Reserved (must be 0) on 82557 */
206 #define CCB3_RES 0xF0 /* Reserved (0) */
207 #define CCB3_TWCL 0x08 /* Terminate Write on Cache Line */
208 #define CCB3_RAE 0x04 /* Read Alignment Enable */
209 #define CCB3_TE 0x02 /* Type Enable??? */
210 #define CCB3_MWIE 0x01 /* Memory Write and Invalidate (MWI) Enable
211 * Additionally the MWI bit in the PCI
212 * command register has to be set.
213 * Recommended by Intel.
214 */
215
216 /* Byte 4 */
217 #define CCB4_RES 0x80 /* Reserved (0) */
218 #define CCB4_RXDMA_MAX 0x7F /* Receive DMA Maximum Byte Count */
219
220 /* Byte 5 */
221 #define CCB5_DMBCE 0x80 /* DMA Maximum Byte Count Enable */
222 #define CCB5_TXDMA_MAX 0x7F /* Transmit DMA Maximum Byte Count */
223
224 /* Byte 6 */
225 #define CCB6_SBF 0x80 /* Save Bad Frames */
226 #define CCB6_DORF 0x40 /* (Do not) Discard Overrun Receive Frame,
227 * Set this bit to keep them.
228 */
229 #define CCB6_ESC 0x20 /* Extended Statistical Counter. Reserved
230 * on 82557, must be set to 1.
231 * Clear this bit to get more counters.
232 */
233 #define CCB6_ETCB 0x10 /* Extended Transmit CB. Reserved on 82557,
234 * must be set to 1.
235 * Clear this bit to use Extended TxCBs.
236 */
237 #define CCB6_CI_INT 0x08 /* CPU Idle (CI) Interrupt. Generate a
238 * CI Int (bit set) or a CNA Int (bit clear)
239 * when the CU goes to the idle state (or
240 * to suspended for CNA).
241 */
242 #define CCB6_TNO_INT 0x04 /* Enable TNO Interrupt (82557 only) */
243 #define CCB6_TCOSC 0x04 /* TCO Statistical Counter (82559 only) */
244 #define CCB6_RES 0x02 /* Reserved, must be set to 1. Called "disable
245 * direct rcv dma mode" by the FreeBSD
246 * driver.
247 */
248 #define CCB6_LSCB 0x01 /* Late SCB Update. Only on 82557. */
249
250 /* Byte 7 */
251 #define CCB7_DTBD 0x80 /* Dynamic TBD. Reserved on 82557, should be
252 * be set to 0.
253 */
254 #define CCB7_2FFIFO 0x40 /* (At Most) Two Frames in FIFO. Reserved on
255 * 82557, should be set to 0.
256 */
257 #define CCB7_RES 0x38 /* Reserved (0) */
258 #define CCB7_UR 0x06 /* Underrun Retry */
259 #define CUR_0 0x00 /* No re-transmission */
260 #define CUR_1 0x02 /* One re-transmission */
261 #define CUR_2 0x04 /* Two re-transmissions, 1st retry with
262 * 512 bytes.
263 */
264 #define CUR_3 0x06 /* Tree re-transmissions, 1st retry
265 * with 512 bytes, 2nd retry with 1024.
266 */
267 #define CCB7_DSRF 0x01 /* Discard Short Receive Frames. */
268
269 /* Byte 8 */
270 #define CCB8_CSMAD 0x80 /* CSMA Disable. Reserved on 82557, should be
271 * set to zero.
272 */
273 #define CCB8_RES 0x7E /* Reserved (0) */
274 #define CCB8_503_MII 0x01 /* 503 mode or MII mode. Reserved on 82558
275 * and 82559, should be set to 1.
276 */
277
278 /* Byte 9 */
279 #define CCB9_MMWE 0x80 /* Multicast Match Wake Enable. 82558 B-step
280 * only, should be set to zero on other
281 * devices.
282 */
283 #define CCB9_AWE 0x40 /* ARP Wake-up Enable. 82558 B-step only,
284 * should be set to zero on other devices.
285 */
286 #define CCB9_LSCWE 0x20 /* Link Status Change Wake Enable. Available
287 * on 82558 B-step and 82559. Should be
288 * set to zero on 82557 and 82558 A-step
289 */
290 #define CCB9_VARP 0x10 /* VLAN ARP (82558 B-step) or VLAN TCO (82559).
291 * Should be zero on 82557 and 82558 A-step
292 */
293 #define CCB9_RES 0x0E /* Reserved (0) */
294 #define CCB9_TUC 0x01 /* TCP/UDP Checksum. 82559 only, should be
295 * zero on other devices.
296 */
297
298 /* Byte 10 */
299 #define CCB10_LOOPBACK 0xC0 /* Loopback mode */
300 #define CLB_NORMAL 0x00 /* Normal operation */
301 #define CLB_INTERNAL 0x40 /* Internal loopback */
302 #define CLB_RESERVED 0x80 /* Reserved */
303 #define CLB_EXTERNAL 0xC0 /* External loopback */
304 #define CCB10_PAL 0x30 /* Pre-amble length */
305 #define CPAL_1 0x00 /* 1 byte */
306 #define CPAL_3 0x10 /* 3 bytes */
307 #define CPAL_7 0x20 /* 7 bytes */
308 #define CPAL_15 0x30 /* 15 bytes */
309 #define CPAL_DEFAULT CPAL_7
310 #define CCB10_NSAI 0x08 /* No Source Address Insertion */
311 #define CCB10_RES1 0x06 /* Reserved, should be set to 1 */
312 #define CCB10_RES0 0x01 /* Reserved (0) */
313
314 /* Byte 11 */
315 #define CCB11_RES 0xF8 /* Reserved (0) */
316 #define CCB11_LINPRIO 0x07 /* Linear Priority. 82557 only,
317 * should be zero on other devices.
318 */
319
320 /* Byte 12 */
321 #define CCB12_IS 0xF0 /* Interframe spacing in multiples of
322 * 16 bit times.
323 */
324 #define CIS_DEFAULT 0x60 /* 96 (6 in register) */
325 #define CCB12_RES 0x0E /* Reserved (0) */
326 #define CCB12_LPM 0x01 /* Linear Priority Mode. 82557 only,
327 * should be zero on other devices.
328 */
329
330 /* Byte 13, 4th byte of IP address for ARP frame filtering. Only valid on
331 * 82558 B-step. Should be 0 on other devices.
332 */
333 #define CCB13_DEFAULT 0x00
334 /* Byte 14, 3rd byte of IP address for ARP fram efiltering. Only valid on
335 * 82558 B-step. Should be 0xF2 on other devices.
336 */
337 #define CCB14_DEFAULT 0xF2
338
339 /* Byte 15 */
340 #define CCB15_CRSCDT 0x80 /* CRS or CDT. */
341 #define CCB15_RES1 0x40 /* Reserved, should be set to one. */
342 #define CCB15_CRC16 0x20 /* 16-bit CRC. Only on 82559,
343 * should be zero on other devices
344 */
345 #define CCB15_IUL 0x10 /* Ignore U/L. Reserved on 82557 and
346 * should be set to zero.
347 */
348 #define CCB15_RES2 0x08 /* Reserved, should be set to one. */
349 #define CCB15_WAW 0x04 /* Wait After Win. Reserved on 82557,
350 * should be set to zero.
351 */
352 #define CCB15_BD 0x02 /* Broadcast disable */
353 #define CCB15_PM 0x01 /* Promiscuous mode */
354
355 /* Byte 16. FC Delay Least Significant Byte. Reserved on the 82557 and
356 * should be set to zero.
357 */
358 #define CCB16_DEFAULT 0x00
359
360 /* Byte 17. FC Delay Most Significant Byte. This byte is reserved on the
361 * 82557 and should be set to 0x40.
362 */
363 #define CCB17_DEFAULT 0x40
364
365 /* Byte 18 */
366 #define CCB18_RES1 0x80 /* Reserved, should be set to 1 */
367 #define CCB18_PFCT 0x70 /* Priority Flow Control Threshold.
368 * Reserved on the 82557 and should
369 * be set to 1. All bits 1 (disabled)
370 * is the recommended default.
371 */
372 #define CCB18_LROK 0x08 /* Long Receive OK. Reserved on the
373 * 82557 and should be set to zero.
374 * Required for VLANs.
375 */
376 #define CCB18_RCRCT 0x04 /* Receive CRC Transfer */
377 #define CCB18_PE 0x02 /* Padding Enable */
378 #define CCB18_SE 0x01 /* Stripping Enable */
379
380 /* Byte 19 */
381 #define CCB19_FDPE 0x80 /* Full Duplex Pin Enable */
382 #define CCB19_FFD 0x40 /* Force Full Duplex */
383 #define CCB19_RFC 0x20 /* Reject FC. Reserved on the 82557
384 * and should be set to zero.
385 */
386 #define CCB19_FDRSTAFC 0x10 /* Full Duplex Restart Flow Control.
387 * Reserved on the 82557 and should be
388 * set to zero.
389 */
390 #define CCB19_FDRSTOFC 0x08 /* Full Duplex Restop Flow Control.
391 * Reserved on the 82557 and should be
392 * set to zero.
393 */
394 #define CCB19_FDTFCD 0x04 /* Full Duplex Transmit Flow Control
395 * Disable. Reserved on the 82557 and
396 * should be set to zero.
397 */
398 #define CCB19_MPWD 0x02 /* Magic Packet Wake-up Disable.
399 * Reserved on the 82557 and 82559ER
400 * and should be set to zero.
401 */
402 #define CCB19_AW 0x01 /* Address Wake-up (82558 A-step) and
403 * IA Match Wake Enable (82558 B-step)
404 * Reserved on the 82557 and 82559 and
405 * should be set to zero.
406 */
407
408 /* Byte 20 */
409 #define CCB20_RES 0x80 /* Reserved (0) */
410 #define CCB20_MIA 0x40 /* Multiple IA */
411 #define CCB20_PFCL 0x20 /* Priority FC Location. Reserved on
412 * the 82557 and should be set to 1.
413 */
414 #define CCB20_RES1 0x1F /* Reserved, should be set to 1 */
415
416 /* Byte 21 */
417 #define CCB21_RES 0xF0 /* Reserved (0) */
418 #define CCB21_MA 0x08 /* Multicast All */
419 #define CCB21_RES1_MASK 0x07 /* Reserved, should be set to 5 */
420 #define CCB21_RES21 0x05
421
422 /* Transmit (4) */
423 struct tx
424 {
425 u16_t tx_status;
426 u16_t tx_command;
427 u32_t tx_linkaddr;
428 u32_t tx_tbda;
429 u16_t tx_size;
430 u8_t tx_tthresh;
431 u8_t tx_ntbd;
432 u8_t tx_buf[NDEV_ETH_PACKET_MAX_TAGGED];
433 };
434
435 #define TXS_C 0x8000 /* Transmit DMA has completed */
436 #define TXS_RES 0x4000 /* Reserved */
437 #define TXS_OK 0x2000 /* Command was executed without error */
438 #define TXS_U 0x1000 /* This or previous frame encoutered underrun */
439 #define TXS_RES1 0x0FFF /* Reserved (0) */
440
441 #define TXC_EL 0x8000 /* End of List */
442 #define TXC_S 0x4000 /* Suspend after this CB */
443 #define TXC_I 0x2000 /* Interrupt after this CB */
444 #define TXC_CID_MASK 0x1F00 /* CNA Interrupt Delay */
445 #define TXC_RES 0x00E0 /* Reserved (0) */
446 #define TXC_NC 0x0010 /* No CRC and Source Address Insertion */
447 #define TXC_SF 0x0008 /* Not in Simplified Mode */
448 #define TXC_CMD 0x0007 /* Command */
449
450 #define TXSZ_EOF 0x8000 /* End of Frame */
451 #define TXSZ_RES 0x4000 /* Reserved (0) */
452 #define TXSZ_COUNT 0x3FFF /* Transmit Byte Count */
453
454 #define TX_TBDA_NIL 0xFFFFFFFF /* Null Pointer for TBD Array */
455
456 #define TXTT_MIN 0x01 /* Minimum for Transmit Threshold */
457 #define TXTT_MAX 0xE0 /* Maximum for Transmit Threshold */
458
459 /* Statistical Counters */
460 struct sc
461 {
462 u32_t sc_tx_good; /* Transmit Good Frames */
463 u32_t sc_tx_maxcol; /* Transmit Maximum Collisions errors */
464 u32_t sc_tx_latecol; /* Transmit Late Collisions errors */
465 u32_t sc_tx_underrun; /* Transmit Underrun errors */
466 u32_t sc_tx_crs; /* Transmit Lost Carrier Sense */
467 u32_t sc_tx_defered; /* Transmit Defered */
468 u32_t sc_tx_scol; /* Transmit Single Collision */
469 u32_t sc_tx_mcol; /* Transmit Multiple Collisions */
470 u32_t sc_tx_totcol; /* Transmit Total Collisions */
471 u32_t sc_rx_good; /* Receive Good Frames */
472 u32_t sc_rx_crc; /* Receive CRC errors */
473 u32_t sc_rx_align; /* Receive Alignment errors */
474 u32_t sc_rx_resource; /* Receive Resource errors */
475 u32_t sc_rx_overrun; /* Receive Overrun errors */
476 u32_t sc_rx_cd; /* Receive Collision Detect errors */
477 u32_t sc_rx_short; /* Receive Short Frame errors */
478
479 /* Short form ends here. The magic number will
480 * be stored in the next field.
481 */
482
483 u32_t sc_tx_fcp; /* Transmit Flow Control Pause */
484 u32_t sc_rx_fcp; /* Receive Flow Control Pause */
485 u32_t sc_rx_fcu; /* Receive Flow Control Unsupported */
486
487 /* Longer form (82558 and later) ends here.
488 * The magic number will be stored in the
489 * next field.
490 */
491
492 u32_t sc_tx_tco; /* Transmit TCO frames */
493 u32_t sc_rx_tco; /* Receive TCO frames */
494 u32_t sc_magic; /* Dump of counters completed */
495 };
496
497 #define SCM_DSC 0x0000A005 /* Magic for SC_CU_DUMP_SC command */
498 #define SCM_DRSC 0x0000A007 /* Magic for SC_CU_DUMP_RSET_SC cmd */
499
500 /* Receive Frame Descriptor (RFD) */
501 struct rfd
502 {
503 u16_t rfd_status;
504 u16_t rfd_command;
505 u32_t rfd_linkaddr;
506 u32_t rfd_reserved;
507 u16_t rfd_res;
508 u16_t rfd_size;
509 u8_t rfd_buf[NDEV_ETH_PACKET_MAX_TAGGED];
510 };
511
512 #define RFDS_C 0x8000 /* Frame Reception Completed */
513 #define RFDS_RES 0x4000 /* Reserved (0) */
514 #define RFDS_OK 0x2000 /* Frame received without any errors */
515 #define RFDS_RES1 0x1000 /* Reserved */
516 #define RFDS_CRCERR 0x0800 /* CRC error */
517 #define RFDS_ALIGNERR 0x0400 /* Alignment error */
518 #define RFDS_OUTOFBUF 0x0200 /* Ran out of buffer space (frame is frager
519 * than supplied buffer).
520 */
521 #define RFDS_DMAOVR 0x0100 /* DMA overrun failure */
522 #define RFDS_TOOSHORT 0x0080 /* Frame Too Short */
523 #define RFDS_RES2 0x0040 /* Reserved */
524 #define RFDS_TYPED 0x0020 /* Frame Is Typed (Type/Length field is 0 or
525 * >1500)
526 */
527 #define RFDS_RXERR 0x0010 /* Receive Error */
528 #define RFDS_RES3 0x0008 /* Reserved */
529 #define RFDS_NOAM 0x0004 /* No Address Match */
530 #define RFDS_NOAIAM 0x0002 /* No IA Address Match */
531 #define RFDS_RXCOL 0x0001 /* Collition Detected During Reception (82557
532 * and 82558 only)
533 */
534 #define RFDS_TCO 0x0001 /* TCO Packet (82559 and later) */
535
536 #define RFDC_EL 0x8000 /* End of List */
537 #define RFDC_S 0x4000 /* Suspend */
538 #define RFDC_RES 0x3FE0 /* Reserved (0) */
539 #define RFDC_H 0x0010 /* Header RFD */
540 #define RFDC_SF 0x0008 /* (Not) Simplified Mode */
541 #define RFDC_RES1 0x0007 /* Reserved (0) */
542
543 #define RFDR_EOF 0x8000 /* End of Frame (all data is in the buffer) */
544 #define RFDR_F 0x4000 /* Finished updating the count field */
545 #define RFDR_COUNT 0x3FFF /* Actual Count */
546
547 #define RFDSZ_RES 0xC000 /* Reserved (0) */
548 #define RFDSZ_SIZE 0x3FFF /* Buffer Size */
549
550 /* EEPROM commands */
551 #define EEPROM_READ_PREFIX 0x6 /* Read command */
552 #define EEPROM_PREFIX_LEN 3 /* Start bit and two command bits */
553
554 /* EEPROM timing parameters */
555 #define EECS_DELAY 1 /* Keep EECS low for at least EECS_DELAY
556 * microseconds
557 */
558 #define EESK_PERIOD 4 /* A cycle of driving EESK high followed by
559 * driving EESK low should take at least
560 * EESK_PERIOD microseconds
561 */
562
563 /* Special registers in the 82555 (and compatible) PHYs. Should be moved
564 * to a separate file if other drivers need this too.
565 */
566 #define MII_SCR 0x10 /* Status and Control Register */
567 #define MII_SCR_FC 0x8000 /* Flow Control */
568 #define MII_SCR_T4E 0x4000 /* Enable T4 unless auto-negotiation */
569 #define MII_SCR_CRSDC 0x2000 /* RX100 CRS Disconnect */
570 #define MII_SCR_RES 0x1000 /* Reserved */
571 #define MII_SCR_RCVSYNC 0x0800 /* RCV De-Serializer in sync */
572 #define MII_SCR_100DOWN 0x0400 /* 100Base-T Power Down */
573 #define MII_SCR_10DOWN 0x0200 /* 10Base-T Power Down */
574 #define MII_SCR_POLARITY 0x0100 /* 10Base-T Polarity */
575 #define MII_SCR_RES_1 0x00F8 /* Reserved */
576 #define MII_SCR_T4 0x0004 /* 100Base-T4 negotiated */
577 #define MII_SCR_100 0x0002 /* 100 Mbps negotiated */
578 #define MII_SCR_FD 0x0001 /* Full Duplex negotiated */
579
580 /*
581 * $PchId: fxp.h,v 1.1 2004/11/23 14:34:03 philip Exp $
582 */
583
584 #endif
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