sys/arch/arm/include/cpuconf.h

   1 /*      $NetBSD: cpuconf.h,v 1.25 2015/07/08 15:18:04 skrll Exp $       */
   2
   3 /*
   4  * Copyright (c) 2002 Wasabi Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed for the NetBSD Project by
  20  *      Wasabi Systems, Inc.
  21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  22  *    or promote products derived from this software without specific prior
  23  *    written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef _ARM_CPUCONF_H_
  39 #define _ARM_CPUCONF_H_
  40
  41 #if defined(_KERNEL_OPT)
  42 #include "opt_cputypes.h"
  43 #include "opt_cpuoptions.h"
  44 #endif /* _KERNEL_OPT */
  45
  46 #if defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270)
  47 #define __CPU_XSCALE_PXA2XX
  48 #endif
  49
  50 #ifdef CPU_XSCALE_PXA2X0
  51 #warning option CPU_XSCALE_PXA2X0 is obsolete. Use CPU_XSCALE_PXA250 and/or CPU_XSCALE_PXA270.
  52 #endif
  53
  54 /*
  55  * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF
  56  * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE
  57  * YOU ARE ADDING SUPPORT FOR.
  58  */
  59
  60 #if 0
  61 /*
  62  * Step 1: Count the number of CPU types configured into the kernel.
  63  */
  64 #if defined(_KERNEL_OPT)
  65 #define CPU_NTYPES      (defined(CPU_ARM2) + defined(CPU_ARM250) +      \
  66                          defined(CPU_ARM3) +                            \
  67                          defined(CPU_ARM6) + defined(CPU_ARM7) +        \
  68                          defined(CPU_ARM7TDMI) +                        \
  69                          defined(CPU_ARM8) + defined(CPU_ARM9) +        \
  70                          defined(CPU_ARM9E) +                           \
  71                          defined(CPU_ARM10) +                           \
  72                          defined(CPU_ARM11) +                           \
  73                          defined(CPU_ARM1136) +                         \
  74                          defined(CPU_ARM1176) +                         \
  75                          defined(CPU_ARM11MPCORE) +                     \
  76                          defined(CPU_CORTEX) +                          \
  77                          defined(CPU_CORTEXA8) +                        \
  78                          defined(CPU_CORTEXA9) +                        \
  79                          defined(CPU_SA110) + defined(CPU_SA1100) +     \
  80                          defined(CPU_SA1110) +                          \
  81                          defined(CPU_FA526) +                           \
  82                          defined(CPU_IXP12X0) +                         \
  83                          defined(CPU_XSCALE) +                          \
  84                          defined(CPU_SHEEVA))
  85 #else
  86 #define CPU_NTYPES      2
  87 #endif /* _KERNEL_OPT */
  88 #endif
  89
  90 /*
  91  * Step 2: Determine which ARM architecture versions are configured.
  92  */
  93 #if !defined(_KERNEL_OPT) ||                                            \
  94     (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3))
  95 #define ARM_ARCH_2      1
  96 #else
  97 #define ARM_ARCH_2      0
  98 #endif
  99
 100 #if !defined(_KERNEL_OPT) ||                                            \
 101     (defined(CPU_ARM6) || defined(CPU_ARM7))
 102 #define ARM_ARCH_3      1
 103 #else
 104 #define ARM_ARCH_3      0
 105 #endif
 106
 107 #if !defined(_KERNEL_OPT) ||                                            \
 108     (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \
 109      defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_FA526) || \
 110      defined(CPU_SA1110) || defined(CPU_IXP12X0))
 111 #define ARM_ARCH_4      1
 112 #else
 113 #define ARM_ARCH_4      0
 114 #endif
 115
 116 #if !defined(_KERNEL_OPT) ||                                            \
 117     (defined(CPU_ARM9E) || defined(CPU_ARM10) ||                        \
 118      defined(CPU_XSCALE) || defined(CPU_SHEEVA))
 119 #define ARM_ARCH_5      1
 120 #else
 121 #define ARM_ARCH_5      0
 122 #endif
 123
 124 #if defined(CPU_ARM11) || defined(CPU_ARM11MPCORE)
 125 #define ARM_ARCH_6      1
 126 #else
 127 #define ARM_ARCH_6      0
 128 #endif
 129
 130 #if defined(CPU_CORTEX) || defined(CPU_PJ4B)
 131 #define ARM_ARCH_7      1
 132 #else
 133 #define ARM_ARCH_7      0
 134 #endif
 135
 136 #define ARM_NARCH       (ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + \
 137                          ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7)
 138 #if ARM_NARCH == 0
 139 #error ARM_NARCH is 0
 140 #endif
 141
 142 #if ARM_ARCH_5 || ARM_ARCH_6 || ARM_ARCH_7
 143 /*
 144  * We could support Thumb code on v4T, but the lack of clean interworking
 145  * makes that hard.
 146  */
 147 #define THUMB_CODE
 148 #endif
 149
 150 /*
 151  * Step 3: Define which MMU classes are configured:
 152  *
 153  *      ARM_MMU_MEMC            Prehistoric, external memory controller
 154  *                              and MMU for ARMv2 CPUs.
 155  *
 156  *      ARM_MMU_GENERIC         Generic ARM MMU, compatible with ARM6.
 157  *
 158  *      ARM_MMU_SA1             StrongARM SA-1 MMU.  Compatible with generic
 159  *                              ARM MMU, but has no write-through cache mode.
 160  *
 161  *      ARM_MMU_XSCALE          XScale MMU.  Compatible with generic ARM
 162  *                              MMU, but also has several extensions which
 163  *                              require different PTE layout to use.
 164  *
 165  *      ARM_MMU_V6C             ARM v6 MMU in backward compatible mode.
 166  *                              Compatible with generic ARM MMU, but
 167  *                              also has several extensions which
 168  *                              require different PTE layouts to use.
 169  *                              XP bit in CP15 control reg is cleared.
 170  *
 171  *      ARM_MMU_V6N             ARM v6 MMU with XP bit of CP15 control reg
 172  *                              set.  New features such as shared-bit
 173  *                              and excute-never bit are available.
 174  *                              Multiprocessor support needs this mode.
 175  *
 176  *      ARM_MMU_V7              ARM v7 MMU.
 177  */
 178 #if !defined(_KERNEL_OPT) ||                                            \
 179     (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3))
 180 #define ARM_MMU_MEMC            1
 181 #else
 182 #define ARM_MMU_MEMC            0
 183 #endif
 184
 185 #if !defined(_KERNEL_OPT) ||                                            \
 186     (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \
 187      defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) ||    \
 188      defined(CPU_ARM10) || defined(CPU_FA526)) || defined(CPU_SHEEVA)
 189 #define ARM_MMU_GENERIC         1
 190 #else
 191 #define ARM_MMU_GENERIC         0
 192 #endif
 193
 194 #if !defined(_KERNEL_OPT) ||                                            \
 195     (defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\
 196      defined(CPU_IXP12X0))
 197 #define ARM_MMU_SA1             1
 198 #else
 199 #define ARM_MMU_SA1             0
 200 #endif
 201
 202 #if !defined(_KERNEL_OPT) ||                                            \
 203     defined(CPU_XSCALE)
 204 #define ARM_MMU_XSCALE          1
 205 #else
 206 #define ARM_MMU_XSCALE          0
 207 #endif
 208
 209 #if !defined(_KERNEL_OPT) ||                                            \
 210         (defined(CPU_ARM11) && defined(ARM11_COMPAT_MMU))
 211 #define ARM_MMU_V6C             1
 212 #else
 213 #define ARM_MMU_V6C             0
 214 #endif
 215
 216 #if !defined(_KERNEL_OPT) ||                                            \
 217         (defined(CPU_ARM11) && !defined(ARM11_COMPAT_MMU))
 218 #define ARM_MMU_V6N             1
 219 #else
 220 #define ARM_MMU_V6N             0
 221 #endif
 222
 223 #define ARM_MMU_V6      (ARM_MMU_V6C + ARM_MMU_V6N)
 224
 225 #if !defined(_KERNEL_OPT) ||                                            \
 226          defined(CPU_ARMV7)
 227 #define ARM_MMU_V7              1
 228 #else
 229 #define ARM_MMU_V7              0
 230 #endif
 231
 232 /*
 233  * Can we use the ASID support in armv6+ MMUs?
 234  */
 235 #if !defined(_LOCORE)
 236 #define ARM_MMU_EXTENDED        ((ARM_MMU_MEMC + ARM_MMU_GENERIC        \
 237                                   + ARM_MMU_SA1 + ARM_MMU_XSCALE        \
 238                                   + ARM_MMU_V6C) == 0                   \
 239                                  && (ARM_MMU_V6N + ARM_MMU_V7) > 0)
 240 #if ARM_MMU_EXTENDED == 0
 241 #undef ARM_MMU_EXTENDED
 242 #endif
 243 #endif
 244
 245 #define ARM_NMMUS               (ARM_MMU_MEMC + ARM_MMU_GENERIC +       \
 246                                  ARM_MMU_SA1 + ARM_MMU_XSCALE +         \
 247                                  ARM_MMU_V6N + ARM_MMU_V6C + ARM_MMU_V7)
 248 #if ARM_NMMUS == 0
 249 #error ARM_NMMUS is 0
 250 #endif
 251
 252 /*
 253  * Step 4: Define features that may be present on a subset of CPUs
 254  *
 255  *      ARM_XSCALE_PMU          Performance Monitoring Unit on 80200 and 80321
 256  */
 257
 258 #if !defined(_KERNEL_OPT) ||                                            \
 259     (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321))
 260 #define ARM_XSCALE_PMU  1
 261 #else
 262 #define ARM_XSCALE_PMU  0
 263 #endif
 264
 265 #endif /* _ARM_CPUCONF_H_ */