1 /* $NetBSD: vfpreg.h,v 1.14 2015/02/09 07:55:52 slp Exp $ */
4 * Copyright (c) 2008 ARM Ltd
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16 * products derived from this software without specific prior written
19 * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR
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32 #ifndef _ARM_VFPREG_H_
33 #define _ARM_VFPREG_H_
37 #define VFP_FPSID_IMP_MSK 0xff000000 /* Implementer */
38 #define VFP_FPSID_IMP_ARM 0x41000000 /* Implementer: ARM */
39 #define VFP_FPSID_SW 0x00800000 /* VFP implemented in SW */
40 #define VFP_FPSID_FMT_MSK 0x00600000 /* FLDMX/FSTMX Format */
41 #define VFP_FPSID_FMT_1 0x00000000 /* Standard format 1 */
42 #define VFP_FPSID_FMT_2 0x00200000 /* Standard format 2 */
43 #define VFP_FPSID_FMT_WEIRD 0x00600000 /* Non-standard format */
44 #define VFP_FPSID_SP 0x00100000 /* Only single precision */
45 #define VFP_FPSID_ARCH_MSK 0x000f0000 /* Architecture */
46 #define VFP_FPSID_ARCH_V1 0x00000000 /* Arch VFPv1 */
47 #define VFP_FPSID_ARCH_V2 0x00010000 /* Arch VFPv2 */
48 #define VFP_FPSID_ARCH_V3_2 0x00020000 /* Arch VFPv3 (subarch v2) */
49 #define VFP_FPSID_ARCH_V3 0x00030000 /* Arch VFPv3 (no subarch) */
50 #define VFP_FPSID_ARCH_V3_3 0x00040000 /* Arch VFPv3 (subarch v3) */
51 #define VFP_FPSID_PART_MSK 0x0000ff00 /* Part number */
52 #define VFP_FPSID_PART_VFP10 0x00001000 /* VFP10 */
53 #define VFP_FPSID_PART_VFP11 0x00002000 /* VFP11 */
54 #define VFP_FPSID_PART_VFP30 0x00003000 /* VFP30 */
55 #define VFP_FPSID_VAR_MSK 0x000000f0 /* Variant */
56 #define VFP_FPSID_VAR_ARM10 0x000000a0 /* Variant ARM10 */
57 #define VFP_FPSID_VAR_ARM11 0x000000b0 /* Variant ARM11 */
58 #define VFP_FPSID_REV_MSK 0x0000000f /* Revision */
60 #define FPU_VFP10_ARM10E 0x410001a0 /* Really a VFPv2 part */
61 #define FPU_VFP11_ARM11 0x410120b0
62 #define FPU_VFP_CORTEXA5 0x41023050
63 #define FPU_VFP_CORTEXA7 0x41023070
64 #define FPU_VFP_CORTEXA8 0x410330c0
65 #define FPU_VFP_CORTEXA9 0x41033090
66 #define FPU_VFP_CORTEXA15 0x410330f0
67 #define FPU_VFP_CORTEXA15_QEMU 0x410430f0
68 #define FPU_VFP_MV88SV58XX 0x56022090
70 #define VFP_FPEXC_EX 0x80000000 /* EXception status bit */
71 #define VFP_FPEXC_EN 0x40000000 /* VFP Enable bit */
72 #define VFP_FPEXC_DEX 0x20000000 /* Defined sync EXception bit */
73 #define VFP_FPEXC_FP2V 0x10000000 /* FPinst2 instruction Valid */
74 #define VFP_FPEXC_VV 0x08000000 /* Vecitr Valid */
75 #define VFP_FPEXC_TFV 0x04000000 /* Trapped Fault Valid */
76 #define VFP_FPEXC_VECITR 0x00000700 /* VECtor ITeRation count */
77 #define VFP_FPEXC_IDF 0x00000080 /* Input Denormal flag */
78 #define VFP_FPEXC_IXF 0x00000010 /* Potential inexact flag */
79 #define VFP_FPEXC_UFF 0x00000008 /* Potential underflow flag */
80 #define VFP_FPEXC_OFF 0x00000004 /* Potential overflow flag */
81 #define VFP_FPEXC_DZF 0x00000002 /* Potential DivByZero flag */
82 #define VFP_FPEXC_IOF 0x00000001 /* Potential inv. op. flag */
83 #define VFP_FPEXC_FSUM 0x000000ff /* all flag bits */
85 #define VFP_FPSCR_N 0x80000000 /* set if compare <= result */
86 #define VFP_FPSCR_Z 0x40000000 /* set if compare = result */
87 #define VFP_FPSCR_C 0x20000000 /* set if compare (=,>=,UNORD) result */
88 #define VFP_FPSCR_V 0x10000000 /* set if compare UNORD result */
89 #define VFP_FPSCR_QC 0x08000000 /* Cumulative saturation (SIMD) */
90 #define VFP_FPSCR_AHP 0x04000000 /* Alternative Half-Precision */
91 #define VFP_FPSCR_DN 0x02000000 /* Default NaN mode */
92 #define VFP_FPSCR_FZ 0x01000000 /* Flush-to-zero mode */
93 #define VFP_FPSCR_RMODE 0x00c00000 /* Rounding Mode */
94 #define VFP_FPSCR_RZ 0x00c00000 /* round towards zero (RZ) */
95 #define VFP_FPSCR_RM 0x00800000 /* round towards +INF (RP) */
96 #define VFP_FPSCR_RP 0x00400000 /* round towards -INF (RM) */
97 #define VFP_FPSCR_RN 0x00000000 /* round to nearest (RN) */
98 #define VFP_FPSCR_STRIDE 0x00300000 /* Vector Stride */
99 #define VFP_FPSCR_LEN 0x00070000 /* Vector Length */
100 #define VFP_FPSCR_IDE 0x00008000 /* Inout Subnormal Exception Enable */
101 #define VFP_FPSCR_ESUM 0x00001f00 /* IXE|UFE|OFE|DZE|IOE */
102 #define VFP_FPSCR_IXE 0x00001000 /* Inexact Exception Enable */
103 #define VFP_FPSCR_UFE 0x00000800 /* Underflow Exception Enable */
104 #define VFP_FPSCR_OFE 0x00000400 /* Overflow Exception Enable */
105 #define VFP_FPSCR_DZE 0x00000200 /* DivByZero Exception Enable */
106 #define VFP_FPSCR_IOE 0x00000100 /* Invalid Operation Cumulative Flag */
107 #define VFP_FPSCR_IDC 0x00000080 /* Input Subnormal Cumlative Flag */
108 #define VFP_FPSCR_CSUM 0x0000001f /* IXC|UFC|OFC|DZC|IOC */
109 #define VFP_FPSCR_IXC 0x00000010 /* Inexact Cumulative Flag */
110 #define VFP_FPSCR_UFC 0x00000008 /* Underflow Cumulative Flag */
111 #define VFP_FPSCR_OFC 0x00000004 /* Overflow Cumulative Flag */
112 #define VFP_FPSCR_DZC 0x00000002 /* DivByZero Cumulative Flag */
113 #define VFP_FPSCR_IOC 0x00000001 /* Invalid Operation Cumulative Flag */
115 #endif /* _ARM_VFPREG_H_ */
