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use shorter ata timeout for identify commands when running from cd
[minix3.git] / drivers / at_wini / at_wini.c
blob3111a928c4e4cf56c25429192a46220113ad2893
1 /* This file contains the device dependent part of a driver for the IBM-AT
2 * winchester controller. Written by Adri Koppes.
3 *
4 * The file contains one entry point:
5 *
6 * at_winchester_task: main entry when system is brought up
7 *
8 * Changes:
9 * Aug 19, 2005 ATA PCI support, supports SATA (Ben Gras)
10 * Nov 18, 2004 moved AT disk driver to user-space (Jorrit N. Herder)
11 * Aug 20, 2004 watchdogs replaced by sync alarms (Jorrit N. Herder)
12 * Mar 23, 2000 added ATAPI CDROM support (Michael Temari)
13 * May 14, 2000 d-d/i rewrite (Kees J. Bot)
14 * Apr 13, 1992 device dependent/independent split (Kees J. Bot)
15 */
16
17 #include "at_wini.h"
18
19 #include <minix/sysutil.h>
20 #include <minix/keymap.h>
21 #include <sys/ioc_disk.h>
22 #include <ibm/pci.h>
23
24 #define ATAPI_DEBUG 0 /* To debug ATAPI code. */
25
26 /* I/O Ports used by winchester disk controllers. */
27
28 /* Read and write registers */
29 #define REG_CMD_BASE0 0x1F0 /* command base register of controller 0 */
30 #define REG_CMD_BASE1 0x170 /* command base register of controller 1 */
31 #define REG_CTL_BASE0 0x3F6 /* control base register of controller 0 */
32 #define REG_CTL_BASE1 0x376 /* control base register of controller 1 */
33
34 #define PCI_CTL_OFF 2 /* Offset of control registers from BAR2 */
35 #define PCI_DMA_2ND_OFF 8 /* Offset of DMA registers from BAR4 for
36 * secondary channel
37 */
38
39 #define REG_DATA 0 /* data register (offset from the base reg.) */
40 #define REG_PRECOMP 1 /* start of write precompensation */
41 #define REG_COUNT 2 /* sectors to transfer */
42 #define REG_SECTOR 3 /* sector number */
43 #define REG_CYL_LO 4 /* low byte of cylinder number */
44 #define REG_CYL_HI 5 /* high byte of cylinder number */
45 #define REG_LDH 6 /* lba, drive and head */
46 #define LDH_DEFAULT 0xA0 /* ECC enable, 512 bytes per sector */
47 #define LDH_LBA 0x40 /* Use LBA addressing */
48 #define LDH_DEV 0x10 /* Drive 1 iff set */
49 #define ldh_init(drive) (LDH_DEFAULT | ((drive) << 4))
50
51 /* Read only registers */
52 #define REG_STATUS 7 /* status */
53 #define STATUS_BSY 0x80 /* controller busy */
54 #define STATUS_RDY 0x40 /* drive ready */
55 #define STATUS_WF 0x20 /* write fault */
56 #define STATUS_SC 0x10 /* seek complete (obsolete) */
57 #define STATUS_DRQ 0x08 /* data transfer request */
58 #define STATUS_CRD 0x04 /* corrected data */
59 #define STATUS_IDX 0x02 /* index pulse */
60 #define STATUS_ERR 0x01 /* error */
61 #define STATUS_ADMBSY 0x100 /* administratively busy (software) */
62 #define REG_ERROR 1 /* error code */
63 #define ERROR_BB 0x80 /* bad block */
64 #define ERROR_ECC 0x40 /* bad ecc bytes */
65 #define ERROR_ID 0x10 /* id not found */
66 #define ERROR_AC 0x04 /* aborted command */
67 #define ERROR_TK 0x02 /* track zero error */
68 #define ERROR_DM 0x01 /* no data address mark */
69
70 /* Write only registers */
71 #define REG_COMMAND 7 /* command */
72 #define CMD_IDLE 0x00 /* for w_command: drive idle */
73 #define CMD_RECALIBRATE 0x10 /* recalibrate drive */
74 #define CMD_READ 0x20 /* read data */
75 #define CMD_READ_EXT 0x24 /* read data (LBA48 addressed) */
76 #define CMD_READ_DMA_EXT 0x25 /* read data using DMA (w/ LBA48) */
77 #define CMD_WRITE 0x30 /* write data */
78 #define CMD_WRITE_EXT 0x34 /* write data (LBA48 addressed) */
79 #define CMD_WRITE_DMA_EXT 0x35 /* write data using DMA (w/ LBA48) */
80 #define CMD_READVERIFY 0x40 /* read verify */
81 #define CMD_FORMAT 0x50 /* format track */
82 #define CMD_SEEK 0x70 /* seek cylinder */
83 #define CMD_DIAG 0x90 /* execute device diagnostics */
84 #define CMD_SPECIFY 0x91 /* specify parameters */
85 #define CMD_READ_DMA 0xC8 /* read data using DMA */
86 #define CMD_WRITE_DMA 0xCA /* write data using DMA */
87 #define ATA_IDENTIFY 0xEC /* identify drive */
88 /* #define REG_CTL 0x206 */ /* control register */
89 #define REG_CTL 0 /* control register */
90 #define CTL_NORETRY 0x80 /* disable access retry */
91 #define CTL_NOECC 0x40 /* disable ecc retry */
92 #define CTL_EIGHTHEADS 0x08 /* more than eight heads */
93 #define CTL_RESET 0x04 /* reset controller */
94 #define CTL_INTDISABLE 0x02 /* disable interrupts */
95 #define REG_CTL_ALTSTAT 0 /* alternate status register */
96
97 /* Identify words */
98 #define ID_GENERAL 0x00 /* General configuration information */
99 #define ID_GEN_NOT_ATA 0x8000 /* Not an ATA device */
100 #define ID_CAPABILITIES 0x31 /* Capabilities (49)*/
101 #define ID_CAP_LBA 0x0200 /* LBA supported */
102 #define ID_CAP_DMA 0x0100 /* DMA supported */
103 #define ID_FIELD_VALIDITY 0x35 /* Field Validity (53) */
104 #define ID_FV_88 0x04 /* Word 88 is valid (UDMA) */
105 #define ID_MULTIWORD_DMA 0x3f /* Multiword DMA (63) */
106 #define ID_MWDMA_2_SEL 0x0400 /* Mode 2 is selected */
107 #define ID_MWDMA_1_SEL 0x0200 /* Mode 1 is selected */
108 #define ID_MWDMA_0_SEL 0x0100 /* Mode 0 is selected */
109 #define ID_MWDMA_2_SUP 0x0004 /* Mode 2 is supported */
110 #define ID_MWDMA_1_SUP 0x0002 /* Mode 1 is supported */
111 #define ID_MWDMA_0_SUP 0x0001 /* Mode 0 is supported */
112 #define ID_CSS 0x53 /* Command Sets Supported (83) */
113 #define ID_CSS_LBA48 0x0400
114 #define ID_ULTRA_DMA 0x58 /* Ultra DMA (88) */
115 #define ID_UDMA_5_SEL 0x2000 /* Mode 5 is selected */
116 #define ID_UDMA_4_SEL 0x1000 /* Mode 4 is selected */
117 #define ID_UDMA_3_SEL 0x0800 /* Mode 3 is selected */
118 #define ID_UDMA_2_SEL 0x0400 /* Mode 2 is selected */
119 #define ID_UDMA_1_SEL 0x0200 /* Mode 1 is selected */
120 #define ID_UDMA_0_SEL 0x0100 /* Mode 0 is selected */
121 #define ID_UDMA_5_SUP 0x0020 /* Mode 5 is supported */
122 #define ID_UDMA_4_SUP 0x0010 /* Mode 4 is supported */
123 #define ID_UDMA_3_SUP 0x0008 /* Mode 3 is supported */
124 #define ID_UDMA_2_SUP 0x0004 /* Mode 2 is supported */
125 #define ID_UDMA_1_SUP 0x0002 /* Mode 1 is supported */
126 #define ID_UDMA_0_SUP 0x0001 /* Mode 0 is supported */
127
128 /* DMA registers */
129 #define DMA_COMMAND 0 /* Command register */
130 #define DMA_CMD_WRITE 0x08 /* PCI bus master writes */
131 #define DMA_CMD_START 0x01 /* Start Bus Master */
132 #define DMA_STATUS 2 /* Status register */
133 #define DMA_ST_D1_DMACAP 0x40 /* Drive 1 is DMA capable */
134 #define DMA_ST_D0_DMACAP 0x20 /* Drive 0 is DMA capable */
135 #define DMA_ST_INT 0x04 /* Interrupt */
136 #define DMA_ST_ERROR 0x02 /* Error */
137 #define DMA_ST_BM_ACTIVE 0x01 /* Bus Master IDE Active */
138 #define DMA_PRDTP 4 /* PRD Table Pointer */
139
140 /* Check for the presence of LBA48 only on drives that are 'big'. */
141 #define LBA48_CHECK_SIZE 0x0f000000
142 #define LBA_MAX_SIZE 0x0fffffff /* Highest sector size for
143 * regular LBA.
144 */
145
146 #if ENABLE_ATAPI
147 #define ERROR_SENSE 0xF0 /* sense key mask */
148 #define SENSE_NONE 0x00 /* no sense key */
149 #define SENSE_RECERR 0x10 /* recovered error */
150 #define SENSE_NOTRDY 0x20 /* not ready */
151 #define SENSE_MEDERR 0x30 /* medium error */
152 #define SENSE_HRDERR 0x40 /* hardware error */
153 #define SENSE_ILRQST 0x50 /* illegal request */
154 #define SENSE_UATTN 0x60 /* unit attention */
155 #define SENSE_DPROT 0x70 /* data protect */
156 #define SENSE_ABRT 0xb0 /* aborted command */
157 #define SENSE_MISCOM 0xe0 /* miscompare */
158 #define ERROR_MCR 0x08 /* media change requested */
159 #define ERROR_ABRT 0x04 /* aborted command */
160 #define ERROR_EOM 0x02 /* end of media detected */
161 #define ERROR_ILI 0x01 /* illegal length indication */
162 #define REG_FEAT 1 /* features */
163 #define FEAT_OVERLAP 0x02 /* overlap */
164 #define FEAT_DMA 0x01 /* dma */
165 #define REG_IRR 2 /* interrupt reason register */
166 #define IRR_REL 0x04 /* release */
167 #define IRR_IO 0x02 /* direction for xfer */
168 #define IRR_COD 0x01 /* command or data */
169 #define REG_SAMTAG 3
170 #define REG_CNT_LO 4 /* low byte of cylinder number */
171 #define REG_CNT_HI 5 /* high byte of cylinder number */
172 #define REG_DRIVE 6 /* drive select */
173 #endif
174
175 #define REG_STATUS 7 /* status */
176 #define STATUS_BSY 0x80 /* controller busy */
177 #define STATUS_DRDY 0x40 /* drive ready */
178 #define STATUS_DMADF 0x20 /* dma ready/drive fault */
179 #define STATUS_SRVCDSC 0x10 /* service or dsc */
180 #define STATUS_DRQ 0x08 /* data transfer request */
181 #define STATUS_CORR 0x04 /* correctable error occurred */
182 #define STATUS_CHECK 0x01 /* check error */
183
184 #ifdef ENABLE_ATAPI
185 #define ATAPI_PACKETCMD 0xA0 /* packet command */
186 #define ATAPI_IDENTIFY 0xA1 /* identify drive */
187 #define SCSI_READ10 0x28 /* read from disk */
188 #define SCSI_SENSE 0x03 /* sense request */
189
190 #define CD_SECTOR_SIZE 2048 /* sector size of a CD-ROM */
191 #endif /* ATAPI */
192
193 /* Interrupt request lines. */
194 #define NO_IRQ 0 /* no IRQ set yet */
195
196 #define ATAPI_PACKETSIZE 12
197 #define SENSE_PACKETSIZE 18
198
199 /* Common command block */
200 struct command {
201 u8_t precomp; /* REG_PRECOMP, etc. */
202 u8_t count;
203 u8_t sector;
204 u8_t cyl_lo;
205 u8_t cyl_hi;
206 u8_t ldh;
207 u8_t command;
208
209 /* The following at for LBA48 */
210 u8_t count_prev;
211 u8_t sector_prev;
212 u8_t cyl_lo_prev;
213 u8_t cyl_hi_prev;
214 };
215
216 /* Error codes */
217 #define ERR (-1) /* general error */
218 #define ERR_BAD_SECTOR (-2) /* block marked bad detected */
219
220 /* Some controllers don't interrupt, the clock will wake us up. */
221 #define WAKEUP_SECS 32 /* drive may be out for 31 seconds max */
222 #define WAKEUP_TICKS (WAKEUP_SECS*HZ)
223
224 /* Miscellaneous. */
225 #define MAX_DRIVES 8
226 #define COMPAT_DRIVES 4
227 #if _WORD_SIZE > 2
228 #define MAX_SECS 256 /* controller can transfer this many sectors */
229 #else
230 #define MAX_SECS 127 /* but not to a 16 bit process */
231 #endif
232 #define MAX_ERRORS 4 /* how often to try rd/wt before quitting */
233 #define NR_MINORS (MAX_DRIVES * DEV_PER_DRIVE)
234 #define SUB_PER_DRIVE (NR_PARTITIONS * NR_PARTITIONS)
235 #define NR_SUBDEVS (MAX_DRIVES * SUB_PER_DRIVE)
236 #define DELAY_USECS 1000 /* controller timeout in microseconds */
237 #define DELAY_TICKS 1 /* controller timeout in ticks */
238 #define DEF_TIMEOUT_TICKS 300 /* controller timeout in ticks */
239 #define RECOVERY_USECS 500000 /* controller recovery time in microseconds */
240 #define RECOVERY_TICKS 30 /* controller recovery time in ticks */
241 #define INITIALIZED 0x01 /* drive is initialized */
242 #define DEAF 0x02 /* controller must be reset */
243 #define SMART 0x04 /* drive supports ATA commands */
244 #if ENABLE_ATAPI
245 #define ATAPI 0x08 /* it is an ATAPI device */
246 #else
247 #define ATAPI 0 /* don't bother with ATAPI; optimise out */
248 #endif
249 #define IDENTIFIED 0x10 /* w_identify done successfully */
250 #define IGNORING 0x20 /* w_identify failed once */
251
252 /* Timeouts and max retries. */
253 int timeout_ticks = DEF_TIMEOUT_TICKS, max_errors = MAX_ERRORS;
254 long w_standard_timeouts = 0, w_pci_debug = 0, w_instance = 0,
255 disable_dma = 0, atapi_debug = 0, w_identify_wakeup_ticks = WAKEUP_TICKS,
256 wakeup_ticks = WAKEUP_TICKS;
257
258 int w_testing = 0, w_silent = 0;
259
260 int w_next_drive = 0;
261
262 /* Variables. */
263
264 /* The struct wini is indexed by controller first, then drive (0-3).
265 * Controller 0 is always the 'compatability' ide controller, at
266 * the fixed locations, whether present or not.
267 */
268 PRIVATE struct wini { /* main drive struct, one entry per drive */
269 unsigned state; /* drive state: deaf, initialized, dead */
270 unsigned short w_status; /* device status register */
271 unsigned base_cmd; /* command base register */
272 unsigned base_ctl; /* control base register */
273 unsigned base_dma; /* dma base register */
274 unsigned irq; /* interrupt request line */
275 unsigned irq_mask; /* 1 << irq */
276 unsigned irq_need_ack; /* irq needs to be acknowledged */
277 int irq_hook_id; /* id of irq hook at the kernel */
278 int lba48; /* supports lba48 */
279 int dma; /* supports dma */
280 unsigned lcylinders; /* logical number of cylinders (BIOS) */
281 unsigned lheads; /* logical number of heads */
282 unsigned lsectors; /* logical number of sectors per track */
283 unsigned pcylinders; /* physical number of cylinders (translated) */
284 unsigned pheads; /* physical number of heads */
285 unsigned psectors; /* physical number of sectors per track */
286 unsigned ldhpref; /* top four bytes of the LDH (head) register */
287 unsigned precomp; /* write precompensation cylinder / 4 */
288 unsigned max_count; /* max request for this drive */
289 unsigned open_ct; /* in-use count */
290 struct device part[DEV_PER_DRIVE]; /* disks and partitions */
291 struct device subpart[SUB_PER_DRIVE]; /* subpartitions */
292 } wini[MAX_DRIVES], *w_wn;
293
294 PRIVATE int w_device = -1;
295 PRIVATE int w_controller = -1;
296 PRIVATE int w_major = -1;
297 PRIVATE char w_id_string[40];
298
299 PRIVATE int win_tasknr; /* my task number */
300 PRIVATE int w_command; /* current command in execution */
301 PRIVATE u8_t w_byteval; /* used for SYS_IRQCTL */
302 PRIVATE int w_drive; /* selected drive */
303 PRIVATE int w_controller; /* selected controller */
304 PRIVATE struct device *w_dv; /* device's base and size */
305
306 /* Unfortunately, DMA_SECTORS and DMA_BUF_SIZE are already defined libdriver
307 * for 'tmp_buf'.
308 */
309 #define ATA_DMA_SECTORS 64
310 #define ATA_DMA_BUF_SIZE (ATA_DMA_SECTORS*SECTOR_SIZE)
311
312 PRIVATE char dma_buf[ATA_DMA_BUF_SIZE];
313 PRIVATE phys_bytes dma_buf_phys;
314
315 #define N_PRDTE 1024 /* Should be enough for large requests */
316
317 PRIVATE struct prdte
318 {
319 u32_t prdte_base;
320 u16_t prdte_count;
321 u8_t prdte_reserved;
322 u8_t prdte_flags;
323 } prdt[N_PRDTE];
324 PRIVATE phys_bytes prdt_phys;
325
326 #define PRDTE_FL_EOT 0x80 /* End of table */
327
328 /* Some IDE devices announce themselves as RAID controllers */
329 PRIVATE struct
330 {
331 u16_t vendor;
332 u16_t device;
333 } raid_table[]=
334 {
335 { 0x1106, 0x3149 }, /* VIA VT6420 */
336 { 0, 0 } /* end of list */
337 };
338
339 FORWARD _PROTOTYPE( void init_params, (void) );
340 FORWARD _PROTOTYPE( void init_drive, (struct wini *w, int base_cmd,
341 int base_ctl, int base_dma, int irq, int ack, int hook,
342 int drive) );
343 FORWARD _PROTOTYPE( void init_params_pci, (int) );
344 FORWARD _PROTOTYPE( int w_do_open, (struct driver *dp, message *m_ptr) );
345 FORWARD _PROTOTYPE( struct device *w_prepare, (int dev) );
346 FORWARD _PROTOTYPE( int w_identify, (void) );
347 FORWARD _PROTOTYPE( char *w_name, (void) );
348 FORWARD _PROTOTYPE( int w_specify, (void) );
349 FORWARD _PROTOTYPE( int w_io_test, (void) );
350 FORWARD _PROTOTYPE( int w_transfer, (int proc_nr, int opcode, u64_t position,
351 iovec_t *iov, unsigned nr_req, int safe));
352 FORWARD _PROTOTYPE( int com_out, (struct command *cmd) );
353 FORWARD _PROTOTYPE( int com_out_ext, (struct command *cmd) );
354 FORWARD _PROTOTYPE( void setup_dma, (unsigned *sizep, int proc_nr,
355 iovec_t *iov, int do_write, int *do_copyoutp, int safe) );
356 FORWARD _PROTOTYPE( void w_need_reset, (void) );
357 FORWARD _PROTOTYPE( void ack_irqs, (unsigned int) );
358 FORWARD _PROTOTYPE( int w_do_close, (struct driver *dp, message *m_ptr) );
359 FORWARD _PROTOTYPE( int w_other, (struct driver *dp, message *m_ptr, int));
360 FORWARD _PROTOTYPE( int w_hw_int, (struct driver *dp, message *m_ptr) );
361 FORWARD _PROTOTYPE( int com_simple, (struct command *cmd) );
362 FORWARD _PROTOTYPE( void w_timeout, (void) );
363 FORWARD _PROTOTYPE( int w_reset, (void) );
364 FORWARD _PROTOTYPE( void w_intr_wait, (void) );
365 FORWARD _PROTOTYPE( int at_intr_wait, (void) );
366 FORWARD _PROTOTYPE( int w_waitfor, (int mask, int value) );
367 FORWARD _PROTOTYPE( int w_waitfor_dma, (int mask, int value) );
368 FORWARD _PROTOTYPE( void w_geometry, (struct partition *entry) );
369 #if ENABLE_ATAPI
370 FORWARD _PROTOTYPE( int atapi_sendpacket, (u8_t *packet, unsigned cnt) );
371 FORWARD _PROTOTYPE( int atapi_intr_wait, (void) );
372 FORWARD _PROTOTYPE( int atapi_open, (void) );
373 FORWARD _PROTOTYPE( void atapi_close, (void) );
374 FORWARD _PROTOTYPE( int atapi_transfer, (int proc_nr, int opcode,
375 u64_t position, iovec_t *iov, unsigned nr_req, int safe));
376 #endif
377
378 /* Entry points to this driver. */
379 PRIVATE struct driver w_dtab = {
380 w_name, /* current device's name */
381 w_do_open, /* open or mount request, initialize device */
382 w_do_close, /* release device */
383 do_diocntl, /* get or set a partition's geometry */
384 w_prepare, /* prepare for I/O on a given minor device */
385 w_transfer, /* do the I/O */
386 nop_cleanup, /* nothing to clean up */
387 w_geometry, /* tell the geometry of the disk */
388 nop_signal, /* no cleanup needed on shutdown */
389 nop_alarm, /* ignore leftover alarms */
390 nop_cancel, /* ignore CANCELs */
391 nop_select, /* ignore selects */
392 w_other, /* catch-all for unrecognized commands and ioctls */
393 w_hw_int /* leftover hardware interrupts */
394 };
395
396 /*===========================================================================*
397 * at_winchester_task *
398 *===========================================================================*/
399 PUBLIC int main(int argc, char *argv[])
400 {
401 /* Install signal handlers. Ask PM to transform signal into message. */
402 struct sigaction sa;
403
404 sa.sa_handler = SIG_MESS;
405 sigemptyset(&sa.sa_mask);
406 sa.sa_flags = 0;
407 if (sigaction(SIGTERM,&sa,NULL)<0) panic("AT","sigaction failed", errno);
408
409 /* Set special disk parameters then call the generic main loop. */
410 env_setargs(argc, argv);
411 init_params();
412 signal(SIGTERM, SIG_IGN);
413 driver_task(&w_dtab);
414 return(OK);
415 }
416
417 /*===========================================================================*
418 * init_params *
419 *===========================================================================*/
420 PRIVATE void init_params()
421 {
422 /* This routine is called at startup to initialize the drive parameters. */
423
424 u16_t parv[2];
425 unsigned int vector, size;
426 int drive, nr_drives;
427 struct wini *wn;
428 u8_t params[16];
429 int s;
430 long wakeup_secs;
431
432 /* Boot variables. */
433 env_parse("ata_std_timeout", "d", 0, &w_standard_timeouts, 0, 1);
434 env_parse("ata_pci_debug", "d", 0, &w_pci_debug, 0, 1);
435 env_parse("ata_instance", "d", 0, &w_instance, 0, 8);
436 env_parse("ata_no_dma", "d", 0, &disable_dma, 0, 1);
437 env_parse("ata_id_timeout", "d", 0, &wakeup_secs, 1, 60);
438 env_parse("atapi_debug", "d", 0, &atapi_debug, 0, 1);
439
440 w_identify_wakeup_ticks = wakeup_secs * HZ;
441
442 if(w_identify_wakeup_ticks <= 0) {
443 printf("changing wakeup from %d to %d ticks.\n",
444 w_identify_wakeup_ticks, WAKEUP_TICKS);
445 w_identify_wakeup_ticks = WAKEUP_TICKS;
446 }
447
448 if (disable_dma)
449 printf("DMA for ATA devices is disabled.\n");
450
451 s= sys_umap(SELF, D, (vir_bytes)dma_buf, sizeof(dma_buf), &dma_buf_phys);
452 if (s != 0)
453 panic("at_wini", "can't map dma buffer", s);
454
455 s= sys_umap(SELF, D, (vir_bytes)prdt, sizeof(prdt), &prdt_phys);
456 if (s != 0)
457 panic("at_wini", "can't map prd table", s);
458
459 if (w_instance == 0) {
460 /* Get the number of drives from the BIOS data area */
461 s=sys_readbios(NR_HD_DRIVES_ADDR, params, NR_HD_DRIVES_SIZE);
462 if (s != OK)
463 panic(w_name(), "Couldn't read BIOS", s);
464 if ((nr_drives = params[0]) > 2) nr_drives = 2;
465
466 for (drive = 0, wn = wini; drive < COMPAT_DRIVES; drive++, wn++) {
467 if (drive < nr_drives) {
468 /* Copy the BIOS parameter vector */
469 vector = (drive == 0) ? BIOS_HD0_PARAMS_ADDR :
470 BIOS_HD1_PARAMS_ADDR;
471 size = (drive == 0) ? BIOS_HD0_PARAMS_SIZE :
472 BIOS_HD1_PARAMS_SIZE;
473 s=sys_readbios(vector, parv, size);
474 if (s != OK)
475 panic(w_name(), "Couldn't read BIOS", s);
476
477 /* Calculate the address of the parameters and copy them */
478 s=sys_readbios(hclick_to_physb(parv[1]) + parv[0],
479 params, 16L);
480 if (s != OK)
481 panic(w_name(),"Couldn't copy parameters", s);
482
483 /* Copy the parameters to the structures of the drive */
484 wn->lcylinders = bp_cylinders(params);
485 wn->lheads = bp_heads(params);
486 wn->lsectors = bp_sectors(params);
487 wn->precomp = bp_precomp(params) >> 2;
488 }
489
490 /* Fill in non-BIOS parameters. */
491 init_drive(wn,
492 drive < 2 ? REG_CMD_BASE0 : REG_CMD_BASE1,
493 drive < 2 ? REG_CTL_BASE0 : REG_CTL_BASE1,
494 0 /* no DMA */, NO_IRQ, 0, 0, drive);
495 w_next_drive++;
496 }
497 }
498
499 /* Look for controllers on the pci bus. Skip none the first instance,
500 * skip one and then 2 for every instance, for every next instance.
501 */
502 if (w_instance == 0)
503 init_params_pci(0);
504 else
505 init_params_pci(w_instance*2-1);
506
507 }
508
509 #define ATA_IF_NOTCOMPAT1 (1L << 0)
510 #define ATA_IF_NOTCOMPAT2 (1L << 2)
511
512 /*===========================================================================*
513 * init_drive *
514 *===========================================================================*/
515 PRIVATE void init_drive(struct wini *w, int base_cmd, int base_ctl,
516 int base_dma, int irq, int ack, int hook, int drive)
517 {
518 w->state = 0;
519 w->w_status = 0;
520 w->base_cmd = base_cmd;
521 w->base_ctl = base_ctl;
522 w->base_dma = base_dma;
523 w->irq = irq;
524 w->irq_mask = 1 << irq;
525 w->irq_need_ack = ack;
526 w->irq_hook_id = hook;
527 w->ldhpref = ldh_init(drive);
528 w->max_count = MAX_SECS << SECTOR_SHIFT;
529 w->lba48 = 0;
530 w->dma = 0;
531 }
532
533 /*===========================================================================*
534 * init_params_pci *
535 *===========================================================================*/
536 PRIVATE void init_params_pci(int skip)
537 {
538 int i, r, devind, drive;
539 int irq, irq_hook, raid;
540 u8_t bcr, scr, interface;
541 u16_t vid, did;
542 u32_t base_dma, t3;
543
544 pci_init();
545 for(drive = w_next_drive; drive < MAX_DRIVES; drive++)
546 wini[drive].state = IGNORING;
547 for(r = pci_first_dev(&devind, &vid, &did); r != 0;
548 r = pci_next_dev(&devind, &vid, &did)) {
549
550 raid= 0;
551
552 /* Except class 01h (mass storage), subclass be 01h (ATA).
553 * Also check listed RAID controllers.
554 */
555 bcr= pci_attr_r8(devind, PCI_BCR);
556 scr= pci_attr_r8(devind, PCI_SCR);
557 interface= pci_attr_r8(devind, PCI_PIFR);
558 t3= ((bcr << 16) | (scr << 8) | interface);
559 if (bcr == PCI_BCR_MASS_STORAGE && scr == PCI_MS_IDE)
560 ; /* Okay */
561 else if (t3 == PCI_T3_RAID)
562 {
563 for (i= 0; raid_table[i].vendor != 0; i++)
564 {
565 if (raid_table[i].vendor == vid &&
566 raid_table[i].device == did)
567 {
568 break;
569 }
570 }
571 if (raid_table[i].vendor == 0)
572 {
573 printf(
574 "atapci skipping unsupported RAID controller 0x%04x / 0x%04x\n",
575 vid, did);
576 continue;
577 }
578 printf("found supported RAID controller\n");
579 raid= 1;
580 }
581 else
582 continue; /* Unsupported device class */
583
584 pci_reserve(devind);
585
586 /* Found a controller.
587 * Programming interface register tells us more.
588 */
589 irq = pci_attr_r8(devind, PCI_ILR);
590
591 /* Any non-compat drives? */
592 if (raid || (interface & (ATA_IF_NOTCOMPAT1 | ATA_IF_NOTCOMPAT2))) {
593 int s;
594
595 if (w_next_drive >= MAX_DRIVES)
596 {
597 /* We can't accept more drives, but have to search for
598 * controllers operating in compatibility mode.
599 */
600 continue;
601 }
602
603 irq_hook = irq;
604 if (skip > 0) {
605 if (w_pci_debug)
606 {
607 printf(
608 "atapci skipping controller (remain %d)\n",
609 skip);
610 }
611 skip--;
612 continue;
613 }
614 if ((s=sys_irqsetpolicy(irq, 0, &irq_hook)) != OK) {
615 printf("atapci: couldn't set IRQ policy %d\n", irq);
616 continue;
617 }
618 if ((s=sys_irqenable(&irq_hook)) != OK) {
619 printf("atapci: couldn't enable IRQ line %d\n", irq);
620 continue;
621 }
622 }
623
624 base_dma = pci_attr_r32(devind, PCI_BAR_5) & 0xfffffffc;
625
626 /* Primary channel not in compatability mode? */
627 if (raid || (interface & ATA_IF_NOTCOMPAT1)) {
628 u32_t base_cmd, base_ctl;
629
630 base_cmd = pci_attr_r32(devind, PCI_BAR) & 0xfffffffc;
631 base_ctl = pci_attr_r32(devind, PCI_BAR_2) & 0xfffffffc;
632 if (base_cmd != REG_CMD_BASE0 && base_cmd != REG_CMD_BASE1) {
633 init_drive(&wini[w_next_drive],
634 base_cmd, base_ctl+PCI_CTL_OFF,
635 base_dma, irq, 1, irq_hook, 0);
636 init_drive(&wini[w_next_drive+1],
637 base_cmd, base_ctl+PCI_CTL_OFF,
638 base_dma, irq, 1, irq_hook, 1);
639 if (w_pci_debug)
640 printf("atapci %d: 0x%x 0x%x irq %d\n", devind, base_cmd, base_ctl, irq);
641 w_next_drive += 2;
642 } else printf("atapci: ignored drives on primary channel, base %x\n", base_cmd);
643 }
644 else
645 {
646 /* Update base_dma for compatibility device */
647 for (i= 0; i<MAX_DRIVES; i++)
648 {
649 if (wini[i].base_cmd == REG_CMD_BASE0)
650 wini[i].base_dma= base_dma;
651 }
652 }
653
654 /* Secondary channel not in compatability mode? */
655 if (raid || (interface & ATA_IF_NOTCOMPAT2)) {
656 u32_t base_cmd, base_ctl;
657
658 base_cmd = pci_attr_r32(devind, PCI_BAR_3) & 0xfffffffc;
659 base_ctl = pci_attr_r32(devind, PCI_BAR_4) & 0xfffffffc;
660 if (base_dma != 0)
661 base_dma += PCI_DMA_2ND_OFF;
662 if (base_cmd != REG_CMD_BASE0 && base_cmd != REG_CMD_BASE1) {
663 init_drive(&wini[w_next_drive],
664 base_cmd, base_ctl+PCI_CTL_OFF, base_dma,
665 irq, 1, irq_hook, 2);
666 init_drive(&wini[w_next_drive+1],
667 base_cmd, base_ctl+PCI_CTL_OFF, base_dma,
668 irq, 1, irq_hook, 3);
669 if (w_pci_debug)
670 printf("atapci %d: 0x%x 0x%x irq %d\n", devind, base_cmd, base_ctl, irq);
671 w_next_drive += 2;
672 } else printf("atapci: ignored drives on secondary channel, base %x\n", base_cmd);
673 }
674 else
675 {
676 /* Update base_dma for compatibility device */
677 for (i= 0; i<MAX_DRIVES; i++)
678 {
679 if (wini[i].base_cmd == REG_CMD_BASE1 && base_dma != 0)
680 wini[i].base_dma= base_dma+PCI_DMA_2ND_OFF;
681 }
682 }
683 }
684 }
685
686 /*===========================================================================*
687 * w_do_open *
688 *===========================================================================*/
689 PRIVATE int w_do_open(dp, m_ptr)
690 struct driver *dp;
691 message *m_ptr;
692 {
693 /* Device open: Initialize the controller and read the partition table. */
694
695 struct wini *wn;
696
697 if (w_prepare(m_ptr->DEVICE) == NIL_DEV) return(ENXIO);
698
699 wn = w_wn;
700
701 /* If we've probed it before and it failed, don't probe it again. */
702 if (wn->state & IGNORING) return ENXIO;
703
704 /* If we haven't identified it yet, or it's gone deaf,
705 * (re-)identify it.
706 */
707 if (!(wn->state & IDENTIFIED) || (wn->state & DEAF)) {
708 /* Try to identify the device. */
709 if (w_identify() != OK) {
710 #if VERBOSE
711 printf("%s: probe failed\n", w_name());
712 #endif
713 if (wn->state & DEAF) w_reset();
714 wn->state = IGNORING;
715 return(ENXIO);
716 }
717 /* Do a test transaction unless it's a CD drive (then
718 * we can believe the controller, and a test may fail
719 * due to no CD being in the drive). If it fails, ignore
720 * the device forever.
721 */
722 if (!(wn->state & ATAPI) && w_io_test() != OK) {
723 wn->state |= IGNORING;
724 return(ENXIO);
725 }
726
727 #if VERBOSE
728 printf("%s: AT driver detected ", w_name());
729 if (wn->state & (SMART|ATAPI)) {
730 printf("%.40s\n", w_id_string);
731 } else {
732 printf("%ux%ux%u\n", wn->pcylinders, wn->pheads, wn->psectors);
733 }
734 #endif
735 }
736
737 #if ENABLE_ATAPI
738 if ((wn->state & ATAPI) && (m_ptr->COUNT & W_BIT))
739 return(EACCES);
740 #endif
741
742 /* Partition the drive if it's being opened for the first time,
743 * or being opened after being closed.
744 */
745 if (wn->open_ct == 0) {
746 #if ENABLE_ATAPI
747 if (wn->state & ATAPI) {
748 int r;
749 if ((r = atapi_open()) != OK) return(r);
750 }
751 #endif
752
753 /* Partition the disk. */
754 partition(&w_dtab, w_drive * DEV_PER_DRIVE, P_PRIMARY, wn->state & ATAPI);
755 }
756 wn->open_ct++;
757 return(OK);
758 }
759
760 /*===========================================================================*
761 * w_prepare *
762 *===========================================================================*/
763 PRIVATE struct device *w_prepare(int device)
764 {
765 /* Prepare for I/O on a device. */
766 struct wini *prev_wn;
767 prev_wn = w_wn;
768 w_device = device;
769
770 if (device < NR_MINORS) { /* d0, d0p[0-3], d1, ... */
771 w_drive = device / DEV_PER_DRIVE; /* save drive number */
772 w_wn = &wini[w_drive];
773 w_dv = &w_wn->part[device % DEV_PER_DRIVE];
774 } else
775 if ((unsigned) (device -= MINOR_d0p0s0) < NR_SUBDEVS) {/*d[0-7]p[0-3]s[0-3]*/
776 w_drive = device / SUB_PER_DRIVE;
777 w_wn = &wini[w_drive];
778 w_dv = &w_wn->subpart[device % SUB_PER_DRIVE];
779 } else {
780 w_device = -1;
781 return(NIL_DEV);
782 }
783 return(w_dv);
784 }
785
786 /*===========================================================================*
787 * w_identify *
788 *===========================================================================*/
789 PRIVATE int w_identify()
790 {
791 /* Find out if a device exists, if it is an old AT disk, or a newer ATA
792 * drive, a removable media device, etc.
793 */
794
795 struct wini *wn = w_wn;
796 struct command cmd;
797 int i, s;
798 int id_dma, ultra_dma;
799 u32_t dma_base;
800 u16_t w;
801 unsigned long dma_status;
802 unsigned long size;
803 int prev_wakeup;
804 int r;
805 #define id_byte(n) (&tmp_buf[2 * (n)])
806 #define id_word(n) (((u16_t) id_byte(n)[0] << 0) \
807 |((u16_t) id_byte(n)[1] << 8))
808 #define id_longword(n) (((u32_t) id_byte(n)[0] << 0) \
809 |((u32_t) id_byte(n)[1] << 8) \
810 |((u32_t) id_byte(n)[2] << 16) \
811 |((u32_t) id_byte(n)[3] << 24))
812
813 /* Try to identify the device. */
814 cmd.ldh = wn->ldhpref;
815 cmd.command = ATA_IDENTIFY;
816
817 /* Execute *_IDENTIFY with configured *_IDENTIFY timeout. */
818 prev_wakeup = wakeup_ticks;
819 wakeup_ticks = w_identify_wakeup_ticks;
820 r = com_simple(&cmd);
821
822 if (r == OK && w_waitfor(STATUS_DRQ, STATUS_DRQ) &&
823 !(wn->w_status & (STATUS_ERR|STATUS_WF))) {
824
825 /* Device information. */
826 if ((s=sys_insw(wn->base_cmd + REG_DATA, SELF, tmp_buf, SECTOR_SIZE)) != OK)
827 panic(w_name(),"Call to sys_insw() failed", s);
828
829 #if 0
830 if (id_word(0) & ID_GEN_NOT_ATA)
831 {
832 printf("%s: not an ATA device?\n", w_name());
833 wakeup_ticks = prev_wakeup;
834 return ERR;
835 }
836 #endif
837
838 /* This is an ATA device. */
839 wn->state |= SMART;
840
841 /* Why are the strings byte swapped??? */
842 for (i = 0; i < 40; i++) w_id_string[i] = id_byte(27)[i^1];
843
844 /* Preferred CHS translation mode. */
845 wn->pcylinders = id_word(1);
846 wn->pheads = id_word(3);
847 wn->psectors = id_word(6);
848 size = (u32_t) wn->pcylinders * wn->pheads * wn->psectors;
849
850 w= id_word(ID_CAPABILITIES);
851 if ((w & ID_CAP_LBA) && size > 512L*1024*2) {
852 /* Drive is LBA capable and is big enough to trust it to
853 * not make a mess of it.
854 */
855 wn->ldhpref |= LDH_LBA;
856 size = id_longword(60);
857
858 w= id_word(ID_CSS);
859 if (size < LBA48_CHECK_SIZE)
860 {
861 /* No need to check for LBA48 */
862 }
863 else if (w & ID_CSS_LBA48) {
864 /* Drive is LBA48 capable (and LBA48 is turned on). */
865 if (id_longword(102)) {
866 /* If no. of sectors doesn't fit in 32 bits,
867 * trunacte to this. So it's LBA32 for now.
868 * This can still address devices up to 2TB
869 * though.
870 */
871 size = ULONG_MAX;
872 } else {
873 /* Actual number of sectors fits in 32 bits. */
874 size = id_longword(100);
875 }
876 wn->lba48 = 1;
877 }
878
879 /* Check for DMA. Assume that only LBA capable devices can do
880 * DMA.
881 */
882 w= id_word(ID_CAPABILITIES);
883 id_dma= !!(w & ID_CAP_DMA);
884 w= id_byte(ID_FIELD_VALIDITY)[0];
885 ultra_dma= !!(w & ID_FV_88);
886 dma_base= wn->base_dma;
887 if (dma_base)
888 {
889 if (sys_inb(dma_base + DMA_STATUS, &dma_status) != OK)
890 {
891 panic(w_name(),
892 "unable to read DMA status register",
893 NO_NUM);
894 }
895 }
896 if (disable_dma)
897 ; /* DMA is disabled */
898 else if (id_dma && dma_base)
899 {
900 w= id_word(ID_MULTIWORD_DMA);
901 if (w & (ID_MWDMA_2_SUP|ID_MWDMA_1_SUP|ID_MWDMA_0_SUP))
902 {
903 printf(
904 "%s: multiword DMA modes supported:%s%s%s\n",
905 w_name(),
906 (w & ID_MWDMA_0_SUP) ? " 0" : "",
907 (w & ID_MWDMA_1_SUP) ? " 1" : "",
908 (w & ID_MWDMA_2_SUP) ? " 2" : "");
909 }
910 if (w & (ID_MWDMA_0_SEL|ID_MWDMA_1_SEL|ID_MWDMA_2_SEL))
911 {
912 printf(
913 "%s: multiword DMA mode selected:%s%s%s\n",
914 w_name(),
915 (w & ID_MWDMA_0_SEL) ? " 0" : "",
916 (w & ID_MWDMA_1_SEL) ? " 1" : "",
917 (w & ID_MWDMA_2_SEL) ? " 2" : "");
918 }
919 if (ultra_dma)
920 {
921 w= id_word(ID_ULTRA_DMA);
922 if (w & (ID_UDMA_0_SUP|ID_UDMA_1_SUP|
923 ID_UDMA_2_SUP|ID_UDMA_3_SUP|
924 ID_UDMA_4_SUP|ID_UDMA_5_SUP))
925 {
926 printf(
927 "%s: Ultra DMA modes supported:%s%s%s%s%s%s\n",
928 w_name(),
929 (w & ID_UDMA_0_SUP) ? " 0" : "",
930 (w & ID_UDMA_1_SUP) ? " 1" : "",
931 (w & ID_UDMA_2_SUP) ? " 2" : "",
932 (w & ID_UDMA_3_SUP) ? " 3" : "",
933 (w & ID_UDMA_4_SUP) ? " 4" : "",
934 (w & ID_UDMA_5_SUP) ? " 5" : "");
935 }
936 if (w & (ID_UDMA_0_SEL|ID_UDMA_1_SEL|
937 ID_UDMA_2_SEL|ID_UDMA_3_SEL|
938 ID_UDMA_4_SEL|ID_UDMA_5_SEL))
939 {
940 printf(
941 "%s: Ultra DMA mode selected:%s%s%s%s%s%s\n",
942 w_name(),
943 (w & ID_UDMA_0_SEL) ? " 0" : "",
944 (w & ID_UDMA_1_SEL) ? " 1" : "",
945 (w & ID_UDMA_2_SEL) ? " 2" : "",
946 (w & ID_UDMA_3_SEL) ? " 3" : "",
947 (w & ID_UDMA_4_SEL) ? " 4" : "",
948 (w & ID_UDMA_5_SEL) ? " 5" : "");
949 }
950 }
951 wn->dma= 1;
952 }
953 else if (id_dma || dma_base)
954 {
955 printf("id_dma %d, dma_base 0x%x\n", id_dma, dma_base);
956 }
957 else
958 printf("no DMA support\n");
959
960 #if 0
961 if (wn->dma && wn == &wini[0])
962 {
963 printf("disabling DMA for drive 0\n");
964 wn->dma= 0;
965 }
966 #endif
967 }
968
969 if (wn->lcylinders == 0) {
970 /* No BIOS parameters? Then make some up. */
971 wn->lcylinders = wn->pcylinders;
972 wn->lheads = wn->pheads;
973 wn->lsectors = wn->psectors;
974 while (wn->lcylinders > 1024) {
975 wn->lheads *= 2;
976 wn->lcylinders /= 2;
977 }
978 }
979 #if ENABLE_ATAPI
980 } else
981 if (cmd.command = ATAPI_IDENTIFY,
982 com_simple(&cmd) == OK && w_waitfor(STATUS_DRQ, STATUS_DRQ) &&
983 !(wn->w_status & (STATUS_ERR|STATUS_WF))) {
984 /* An ATAPI device. */
985 wn->state |= ATAPI;
986
987 /* Device information. */
988 if ((s=sys_insw(wn->base_cmd + REG_DATA, SELF, tmp_buf, 512)) != OK)
989 panic(w_name(),"Call to sys_insw() failed", s);
990
991 /* Why are the strings byte swapped??? */
992 for (i = 0; i < 40; i++) w_id_string[i] = id_byte(27)[i^1];
993
994 size = 0; /* Size set later. */
995 #endif
996 } else {
997 /* Not an ATA device; no translations, no special features. Don't
998 * touch it unless the BIOS knows about it.
999 */
1000 if (wn->lcylinders == 0) {
1001 wakeup_ticks = prev_wakeup;
1002 return(ERR);
1003 } /* no BIOS parameters */
1004 wn->pcylinders = wn->lcylinders;
1005 wn->pheads = wn->lheads;
1006 wn->psectors = wn->lsectors;
1007 size = (u32_t) wn->pcylinders * wn->pheads * wn->psectors;
1008 }
1009
1010 /* Restore wakeup_ticks. */
1011 wakeup_ticks = prev_wakeup;
1012
1013 /* Size of the whole drive */
1014 wn->part[0].dv_size = mul64u(size, SECTOR_SIZE);
1015
1016 /* Reset/calibrate (where necessary) */
1017 if (w_specify() != OK && w_specify() != OK) {
1018 return(ERR);
1019 }
1020
1021 if (wn->irq == NO_IRQ) {
1022 /* Everything looks OK; register IRQ so we can stop polling. */
1023 wn->irq = w_drive < 2 ? AT_WINI_0_IRQ : AT_WINI_1_IRQ;
1024 wn->irq_hook_id = wn->irq; /* id to be returned if interrupt occurs */
1025 if ((s=sys_irqsetpolicy(wn->irq, IRQ_REENABLE, &wn->irq_hook_id)) != OK)
1026 panic(w_name(), "couldn't set IRQ policy", s);
1027 if ((s=sys_irqenable(&wn->irq_hook_id)) != OK)
1028 panic(w_name(), "couldn't enable IRQ line", s);
1029 }
1030 wn->state |= IDENTIFIED;
1031 return(OK);
1032 }
1033
1034 /*===========================================================================*
1035 * w_name *
1036 *===========================================================================*/
1037 PRIVATE char *w_name()
1038 {
1039 /* Return a name for the current device. */
1040 static char name[] = "AT0-D0";
1041
1042 name[2] = '0' + w_instance;
1043 name[5] = '0' + w_drive;
1044 return name;
1045 }
1046
1047 /*===========================================================================*
1048 * w_io_test *
1049 *===========================================================================*/
1050 PRIVATE int w_io_test(void)
1051 {
1052 int r, save_dev;
1053 int save_timeout, save_errors, save_wakeup;
1054 iovec_t iov;
1055 #ifdef CD_SECTOR_SIZE
1056 static char buf[CD_SECTOR_SIZE];
1057 #else
1058 static char buf[SECTOR_SIZE];
1059 #endif
1060
1061 iov.iov_addr = (vir_bytes) buf;
1062 iov.iov_size = sizeof(buf);
1063 save_dev = w_device;
1064
1065 /* Reduce timeout values for this test transaction. */
1066 save_timeout = timeout_ticks;
1067 save_errors = max_errors;
1068 save_wakeup = wakeup_ticks;
1069
1070 if (!w_standard_timeouts) {
1071 timeout_ticks = HZ * 4;
1072 wakeup_ticks = HZ * 6;
1073 max_errors = 3;
1074 }
1075
1076 w_testing = 1;
1077
1078 /* Try I/O on the actual drive (not any (sub)partition). */
1079 if (w_prepare(w_drive * DEV_PER_DRIVE) == NIL_DEV)
1080 panic(w_name(), "Couldn't switch devices", NO_NUM);
1081
1082 r = w_transfer(SELF, DEV_GATHER_S, cvu64(0), &iov, 1, 0);
1083
1084 /* Switch back. */
1085 if (w_prepare(save_dev) == NIL_DEV)
1086 panic(w_name(), "Couldn't switch back devices", NO_NUM);
1087
1088 /* Restore parameters. */
1089 timeout_ticks = save_timeout;
1090 max_errors = save_errors;
1091 wakeup_ticks = save_wakeup;
1092 w_testing = 0;
1093
1094 /* Test if everything worked. */
1095 if (r != OK || iov.iov_size != 0) {
1096 return ERR;
1097 }
1098
1099 /* Everything worked. */
1100
1101 return OK;
1102 }
1103
1104 /*===========================================================================*
1105 * w_specify *
1106 *===========================================================================*/
1107 PRIVATE int w_specify()
1108 {
1109 /* Routine to initialize the drive after boot or when a reset is needed. */
1110
1111 struct wini *wn = w_wn;
1112 struct command cmd;
1113
1114 if ((wn->state & DEAF) && w_reset() != OK) {
1115 return(ERR);
1116 }
1117
1118 if (!(wn->state & ATAPI)) {
1119 /* Specify parameters: precompensation, number of heads and sectors. */
1120 cmd.precomp = wn->precomp;
1121 cmd.count = wn->psectors;
1122 cmd.ldh = w_wn->ldhpref | (wn->pheads - 1);
1123 cmd.command = CMD_SPECIFY; /* Specify some parameters */
1124
1125 /* Output command block and see if controller accepts the parameters. */
1126 if (com_simple(&cmd) != OK) return(ERR);
1127
1128 if (!(wn->state & SMART)) {
1129 /* Calibrate an old disk. */
1130 cmd.sector = 0;
1131 cmd.cyl_lo = 0;
1132 cmd.cyl_hi = 0;
1133 cmd.ldh = w_wn->ldhpref;
1134 cmd.command = CMD_RECALIBRATE;
1135
1136 if (com_simple(&cmd) != OK) return(ERR);
1137 }
1138 }
1139 wn->state |= INITIALIZED;
1140 return(OK);
1141 }
1142
1143 /*===========================================================================*
1144 * do_transfer *
1145 *===========================================================================*/
1146 PRIVATE int do_transfer(struct wini *wn, unsigned int precomp,
1147 unsigned int count, unsigned int sector,
1148 unsigned int opcode, int do_dma)
1149 {
1150 struct command cmd;
1151 unsigned int sector_high;
1152 unsigned secspcyl = wn->pheads * wn->psectors;
1153 int do_lba48;
1154
1155 sector_high= 0; /* For future extensions */
1156
1157 do_lba48= 0;
1158 if (sector >= LBA48_CHECK_SIZE || sector_high != 0)
1159 {
1160 if (wn->lba48)
1161 do_lba48= 1;
1162 else if (sector > LBA_MAX_SIZE || sector_high != 0)
1163 {
1164 /* Strange sector count for LBA device */
1165 return EIO;
1166 }
1167 }
1168
1169 cmd.precomp = precomp;
1170 cmd.count = count;
1171 if (do_dma)
1172 {
1173 cmd.command = opcode == DEV_SCATTER_S ? CMD_WRITE_DMA :
1174 CMD_READ_DMA;
1175 }
1176 else
1177 cmd.command = opcode == DEV_SCATTER_S ? CMD_WRITE : CMD_READ;
1178
1179 if (do_lba48) {
1180 if (do_dma)
1181 {
1182 cmd.command = ((opcode == DEV_SCATTER_S) ?
1183 CMD_WRITE_DMA_EXT : CMD_READ_DMA_EXT);
1184 }
1185 else
1186 {
1187 cmd.command = ((opcode == DEV_SCATTER_S) ?
1188 CMD_WRITE_EXT : CMD_READ_EXT);
1189 }
1190 cmd.count_prev= (count >> 8);
1191 cmd.sector = (sector >> 0) & 0xFF;
1192 cmd.cyl_lo = (sector >> 8) & 0xFF;
1193 cmd.cyl_hi = (sector >> 16) & 0xFF;
1194 cmd.sector_prev= (sector >> 24) & 0xFF;
1195 cmd.cyl_lo_prev= (sector_high) & 0xFF;
1196 cmd.cyl_hi_prev= (sector_high >> 8) & 0xFF;
1197 cmd.ldh = wn->ldhpref;
1198
1199 return com_out_ext(&cmd);
1200 } else if (wn->ldhpref & LDH_LBA) {
1201 cmd.sector = (sector >> 0) & 0xFF;
1202 cmd.cyl_lo = (sector >> 8) & 0xFF;
1203 cmd.cyl_hi = (sector >> 16) & 0xFF;
1204 cmd.ldh = wn->ldhpref | ((sector >> 24) & 0xF);
1205 } else {
1206 int cylinder, head, sec;
1207 cylinder = sector / secspcyl;
1208 head = (sector % secspcyl) / wn->psectors;
1209 sec = sector % wn->psectors;
1210 cmd.sector = sec + 1;
1211 cmd.cyl_lo = cylinder & BYTE;
1212 cmd.cyl_hi = (cylinder >> 8) & BYTE;
1213 cmd.ldh = wn->ldhpref | head;
1214 }
1215
1216 return com_out(&cmd);
1217 }
1218
1219 /*===========================================================================*
1220 * w_transfer *
1221 *===========================================================================*/
1222 PRIVATE int w_transfer(proc_nr, opcode, position, iov, nr_req, safe)
1223 int proc_nr; /* process doing the request */
1224 int opcode; /* DEV_GATHER_S or DEV_SCATTER_S */
1225 u64_t position; /* offset on device to read or write */
1226 iovec_t *iov; /* pointer to read or write request vector */
1227 unsigned nr_req; /* length of request vector */
1228 int safe; /* iov contains addresses (0) or grants? */
1229 {
1230 struct wini *wn = w_wn;
1231 iovec_t *iop, *iov_end = iov + nr_req;
1232 int n, r, s, errors, do_dma, do_write, do_copyout;
1233 unsigned long v, block, w_status;
1234 u64_t dv_size = w_dv->dv_size;
1235 unsigned cylinder, head, sector, nbytes;
1236 unsigned dma_buf_offset;
1237 size_t addr_offset = 0;
1238
1239 #if ENABLE_ATAPI
1240 if (w_wn->state & ATAPI) {
1241 return atapi_transfer(proc_nr, opcode, position, iov, nr_req, safe);
1242 }
1243 #endif
1244
1245 /* Check disk address. */
1246 if (rem64u(position, SECTOR_SIZE) != 0) return(EINVAL);
1247
1248 errors = 0;
1249
1250 while (nr_req > 0) {
1251 /* How many bytes to transfer? */
1252 nbytes = 0;
1253 for (iop = iov; iop < iov_end; iop++) nbytes += iop->iov_size;
1254 if ((nbytes & SECTOR_MASK) != 0) return(EINVAL);
1255
1256 /* Which block on disk and how close to EOF? */
1257 if (cmp64(position, dv_size) >= 0) return(OK); /* At EOF */
1258 if (cmp64(add64ul(position, nbytes), dv_size) > 0)
1259 nbytes = diff64(dv_size, position);
1260 block = div64u(add64(w_dv->dv_base, position), SECTOR_SIZE);
1261
1262 do_dma= wn->dma;
1263 do_write= (opcode == DEV_SCATTER_S);
1264
1265 if (nbytes >= wn->max_count) {
1266 /* The drive can't do more then max_count at once. */
1267 nbytes = wn->max_count;
1268 }
1269
1270 /* First check to see if a reinitialization is needed. */
1271 if (!(wn->state & INITIALIZED) && w_specify() != OK) return(EIO);
1272
1273 if (do_dma)
1274 {
1275 setup_dma(&nbytes, proc_nr, iov, do_write, &do_copyout, safe);
1276 #if 0
1277 printf("nbytes = %d\n", nbytes);
1278 #endif
1279 }
1280
1281 /* Tell the controller to transfer nbytes bytes. */
1282 r = do_transfer(wn, wn->precomp, (nbytes >> SECTOR_SHIFT),
1283 block, opcode, do_dma);
1284
1285 if (opcode == DEV_SCATTER_S) {
1286 /* The specs call for a 400 ns wait after issuing the command.
1287 * Reading the alternate status register is the suggested
1288 * way to implement this wait.
1289 */
1290 if (sys_inb((wn->base_ctl+REG_CTL_ALTSTAT), &w_status) != OK)
1291 panic(w_name(), "couldn't get status", NO_NUM);
1292 }
1293
1294 if (do_dma)
1295 {
1296 /* Wait for the interrupt, check DMA status and optionally
1297 * copy out.
1298 */
1299
1300 if ((r = at_intr_wait()) != OK)
1301 {
1302 /* Don't retry if sector marked bad or too many
1303 * errors.
1304 */
1305 if (r == ERR_BAD_SECTOR || ++errors == max_errors) {
1306 w_command = CMD_IDLE;
1307 return(EIO);
1308 }
1309 continue;
1310 }
1311
1312 /* Wait for DMA_ST_INT to get set */
1313 w_waitfor_dma(DMA_ST_INT, DMA_ST_INT);
1314
1315 r= sys_inb(wn->base_dma + DMA_STATUS, &v);
1316 if (r != 0) panic("at_wini", "w_transfer: sys_inb failed", r);
1317
1318 #if 0
1319 printf("dma_status: 0x%x\n", v);
1320 #endif
1321 if (!(v & DMA_ST_INT))
1322 {
1323 /* DMA did not complete successfully */
1324 if (v & DMA_ST_BM_ACTIVE)
1325 panic(w_name(), "DMA did not complete", NO_NUM);
1326 else if (v & DMA_ST_ERROR)
1327 {
1328 printf("at_wini: DMA error\n");
1329 r= EIO;
1330 break;
1331 }
1332 else
1333 {
1334 #if 0
1335 printf("DMA buffer too small\n");
1336 #endif
1337 panic(w_name(), "DMA buffer too small", NO_NUM);
1338 }
1339 }
1340 else if (v & DMA_ST_BM_ACTIVE)
1341 panic(w_name(), "DMA buffer too large", NO_NUM);
1342
1343 dma_buf_offset= 0;
1344 while (r == OK && nbytes > 0)
1345 {
1346 n= iov->iov_size;
1347 if (n > nbytes)
1348 n= nbytes;
1349
1350 if (do_copyout)
1351 {
1352 if(safe) {
1353 s= sys_safecopyto(proc_nr, iov->iov_addr,
1354 addr_offset,
1355 (vir_bytes)dma_buf+dma_buf_offset, n, D);
1356 } else {
1357 s= sys_vircopy(SELF, D,
1358 (vir_bytes)dma_buf+dma_buf_offset,
1359 proc_nr, D,
1360 iov->iov_addr + addr_offset, n);
1361 }
1362 if (s != OK)
1363 {
1364 panic(w_name(),
1365 "w_transfer: sys_vircopy failed",
1366 s);
1367 }
1368 }
1369
1370 /* Book the bytes successfully transferred. */
1371 nbytes -= n;
1372 position= add64ul(position, n);
1373 if ((iov->iov_size -= n) == 0) {
1374 iov++; nr_req--; addr_offset = 0;
1375 }
1376 dma_buf_offset += n;
1377 }
1378 }
1379
1380 while (r == OK && nbytes > 0) {
1381 /* For each sector, wait for an interrupt and fetch the data
1382 * (read), or supply data to the controller and wait for an
1383 * interrupt (write).
1384 */
1385
1386 if (opcode == DEV_GATHER_S) {
1387 /* First an interrupt, then data. */
1388 if ((r = at_intr_wait()) != OK) {
1389 /* An error, send data to the bit bucket. */
1390 if (w_wn->w_status & STATUS_DRQ) {
1391 if ((s=sys_insw(wn->base_cmd+REG_DATA,
1392 SELF, tmp_buf,
1393 SECTOR_SIZE)) != OK)
1394 {
1395 panic(w_name(),
1396 "Call to sys_insw() failed",
1397 s);
1398 }
1399 }
1400 break;
1401 }
1402 }
1403
1404 /* Wait for busy to clear. */
1405 if (!w_waitfor(STATUS_BSY, 0)) { r = ERR; break; }
1406
1407 /* Wait for data transfer requested. */
1408 if (!w_waitfor(STATUS_DRQ, STATUS_DRQ)) { r = ERR; break; }
1409
1410 /* Copy bytes to or from the device's buffer. */
1411 if (opcode == DEV_GATHER_S) {
1412 if(safe) {
1413 s=sys_safe_insw(wn->base_cmd + REG_DATA, proc_nr,
1414 (void *) (iov->iov_addr), addr_offset,
1415 SECTOR_SIZE);
1416 } else {
1417 s=sys_insw(wn->base_cmd + REG_DATA, proc_nr,
1418 (void *) (iov->iov_addr + addr_offset),
1419 SECTOR_SIZE);
1420 }
1421 if(s != OK) {
1422 panic(w_name(),"Call to sys_insw() failed", s);
1423 }
1424 } else {
1425 if(safe) {
1426 s=sys_safe_outsw(wn->base_cmd + REG_DATA, proc_nr,
1427 (void *) (iov->iov_addr), addr_offset,
1428 SECTOR_SIZE);
1429 } else {
1430 s=sys_outsw(wn->base_cmd + REG_DATA, proc_nr,
1431 (void *) (iov->iov_addr + addr_offset),
1432 SECTOR_SIZE);
1433 }
1434
1435 if(s != OK) {
1436 panic(w_name(),"Call to sys_outsw() failed",
1437 s);
1438 }
1439
1440 /* Data sent, wait for an interrupt. */
1441 if ((r = at_intr_wait()) != OK) break;
1442 }
1443
1444 /* Book the bytes successfully transferred. */
1445 nbytes -= SECTOR_SIZE;
1446 position= add64u(position, SECTOR_SIZE);
1447 addr_offset += SECTOR_SIZE;
1448 if ((iov->iov_size -= SECTOR_SIZE) == 0) {
1449 iov++;
1450 nr_req--;
1451 addr_offset = 0;
1452 }
1453 }
1454
1455 /* Any errors? */
1456 if (r != OK) {
1457 /* Don't retry if sector marked bad or too many errors. */
1458 if (r == ERR_BAD_SECTOR || ++errors == max_errors) {
1459 w_command = CMD_IDLE;
1460 return(EIO);
1461 }
1462 }
1463 }
1464
1465 w_command = CMD_IDLE;
1466 return(OK);
1467 }
1468
1469 /*===========================================================================*
1470 * com_out *
1471 *===========================================================================*/
1472 PRIVATE int com_out(cmd)
1473 struct command *cmd; /* Command block */
1474 {
1475 /* Output the command block to the winchester controller and return status */
1476
1477 struct wini *wn = w_wn;
1478 unsigned base_cmd = wn->base_cmd;
1479 unsigned base_ctl = wn->base_ctl;
1480 pvb_pair_t outbyte[7]; /* vector for sys_voutb() */
1481 int s; /* status for sys_(v)outb() */
1482
1483 if (w_wn->state & IGNORING) return ERR;
1484
1485 if (!w_waitfor(STATUS_BSY, 0)) {
1486 printf("%s: controller not ready\n", w_name());
1487 return(ERR);
1488 }
1489
1490 /* Select drive. */
1491 if ((s=sys_outb(base_cmd + REG_LDH, cmd->ldh)) != OK)
1492 panic(w_name(),"Couldn't write register to select drive",s);
1493
1494 if (!w_waitfor(STATUS_BSY, 0)) {
1495 printf("%s: com_out: drive not ready\n", w_name());
1496 return(ERR);
1497 }
1498
1499 /* Schedule a wakeup call, some controllers are flaky. This is done with
1500 * a synchronous alarm. If a timeout occurs a SYN_ALARM message is sent
1501 * from HARDWARE, so that w_intr_wait() can call w_timeout() in case the
1502 * controller was not able to execute the command. Leftover timeouts are
1503 * simply ignored by the main loop.
1504 */
1505 sys_setalarm(wakeup_ticks, 0);
1506
1507 wn->w_status = STATUS_ADMBSY;
1508 w_command = cmd->command;
1509 pv_set(outbyte[0], base_ctl + REG_CTL, wn->pheads >= 8 ? CTL_EIGHTHEADS : 0);
1510 pv_set(outbyte[1], base_cmd + REG_PRECOMP, cmd->precomp);
1511 pv_set(outbyte[2], base_cmd + REG_COUNT, cmd->count);
1512 pv_set(outbyte[3], base_cmd + REG_SECTOR, cmd->sector);
1513 pv_set(outbyte[4], base_cmd + REG_CYL_LO, cmd->cyl_lo);
1514 pv_set(outbyte[5], base_cmd + REG_CYL_HI, cmd->cyl_hi);
1515 pv_set(outbyte[6], base_cmd + REG_COMMAND, cmd->command);
1516 if ((s=sys_voutb(outbyte,7)) != OK)
1517 panic(w_name(),"Couldn't write registers with sys_voutb()",s);
1518 return(OK);
1519 }
1520
1521 /*===========================================================================*
1522 * com_out_ext *
1523 *===========================================================================*/
1524 PRIVATE int com_out_ext(cmd)
1525 struct command *cmd; /* Command block */
1526 {
1527 /* Output the command block to the winchester controller and return status */
1528
1529 struct wini *wn = w_wn;
1530 unsigned base_cmd = wn->base_cmd;
1531 unsigned base_ctl = wn->base_ctl;
1532 pvb_pair_t outbyte[11]; /* vector for sys_voutb() */
1533 int s; /* status for sys_(v)outb() */
1534 unsigned long w_status;
1535
1536 if (w_wn->state & IGNORING) return ERR;
1537
1538 if (!w_waitfor(STATUS_BSY, 0)) {
1539 printf("%s: controller not ready\n", w_name());
1540 return(ERR);
1541 }
1542
1543 /* Select drive. */
1544 if ((s=sys_outb(base_cmd + REG_LDH, cmd->ldh)) != OK)
1545 panic(w_name(),"Couldn't write register to select drive",s);
1546
1547 if (!w_waitfor(STATUS_BSY, 0)) {
1548 printf("%s: com_out: drive not ready\n", w_name());
1549 return(ERR);
1550 }
1551
1552 /* Schedule a wakeup call, some controllers are flaky. This is done with
1553 * a synchronous alarm. If a timeout occurs a SYN_ALARM message is sent
1554 * from HARDWARE, so that w_intr_wait() can call w_timeout() in case the
1555 * controller was not able to execute the command. Leftover timeouts are
1556 * simply ignored by the main loop.
1557 */
1558 sys_setalarm(wakeup_ticks, 0);
1559
1560 wn->w_status = STATUS_ADMBSY;
1561 w_command = cmd->command;
1562 pv_set(outbyte[0], base_ctl + REG_CTL, 0);
1563 pv_set(outbyte[1], base_cmd + REG_COUNT, cmd->count_prev);
1564 pv_set(outbyte[2], base_cmd + REG_SECTOR, cmd->sector_prev);
1565 pv_set(outbyte[3], base_cmd + REG_CYL_LO, cmd->cyl_lo_prev);
1566 pv_set(outbyte[4], base_cmd + REG_CYL_HI, cmd->cyl_hi_prev);
1567 pv_set(outbyte[5], base_cmd + REG_COUNT, cmd->count);
1568 pv_set(outbyte[6], base_cmd + REG_SECTOR, cmd->sector);
1569 pv_set(outbyte[7], base_cmd + REG_CYL_LO, cmd->cyl_lo);
1570 pv_set(outbyte[8], base_cmd + REG_CYL_HI, cmd->cyl_hi);
1571
1572 pv_set(outbyte[10], base_cmd + REG_COMMAND, cmd->command);
1573 if ((s=sys_voutb(outbyte, 11)) != OK)
1574 panic(w_name(),"Couldn't write registers with sys_voutb()",s);
1575
1576 return(OK);
1577 }
1578
1579 /*===========================================================================*
1580 * setup_dma *
1581 *===========================================================================*/
1582 PRIVATE void setup_dma(sizep, proc_nr, iov, do_write, do_copyoutp, safe)
1583 unsigned *sizep;
1584 int proc_nr;
1585 iovec_t *iov;
1586 int do_write;
1587 int *do_copyoutp;
1588 int safe;
1589 {
1590 phys_bytes phys, user_phys;
1591 unsigned n, offset, size;
1592 int i, j, r, bad;
1593 unsigned long v;
1594 struct wini *wn = w_wn;
1595
1596 /* First try direct scatter/gather to the supplied buffers */
1597 size= *sizep;
1598 i= 0; /* iov index */
1599 j= 0; /* prdt index */
1600 bad= 0;
1601 offset= 0; /* Offset in current iov */
1602
1603 #if 0
1604 printf("setup_dma: proc_nr %d\n", proc_nr);
1605 #endif
1606
1607 while (size > 0)
1608 {
1609 #if 0
1610 printf(
1611 "setup_dma: iov[%d]: addr 0x%x, size %d offset %d, size %d\n",
1612 i, iov[i].iov_addr, iov[i].iov_size, offset, size);
1613 #endif
1614
1615 n= iov[i].iov_size-offset;
1616 if (n > size)
1617 n= size;
1618 if (n == 0 || (n & 1))
1619 panic("at_wini", "bad size in iov", iov[i].iov_size);
1620 if(safe) {
1621 r= sys_umap(proc_nr, GRANT_SEG, iov[i].iov_addr, n,&user_phys);
1622 user_phys += offset;
1623 } else {
1624 r= sys_umap(proc_nr, D, iov[i].iov_addr+offset, n, &user_phys);
1625 }
1626 if (r != 0)
1627 panic("at_wini", "can't map user buffer", r);
1628 if (user_phys & 1)
1629 {
1630 /* Buffer is not aligned */
1631 printf("setup_dma: user buffer is not aligned\n");
1632 bad= 1;
1633 break;
1634 }
1635
1636 /* vector is not allowed to cross a 64K boundary */
1637 if (user_phys/0x10000 != (user_phys+n-1)/0x10000)
1638 n= ((user_phys/0x10000)+1)*0x10000 - user_phys;
1639
1640 /* vector is not allowed to be bigger than 64K, but we get that
1641 * for free.
1642 */
1643
1644 if (j >= N_PRDTE)
1645 {
1646 /* Too many entries */
1647 bad= 1;
1648 break;
1649 }
1650
1651 prdt[j].prdte_base= user_phys;
1652 prdt[j].prdte_count= n;
1653 prdt[j].prdte_reserved= 0;
1654 prdt[j].prdte_flags= 0;
1655 j++;
1656
1657 offset += n;
1658 if (offset >= iov[i].iov_size)
1659 {
1660 i++;
1661 offset= 0;
1662 }
1663
1664 size -= n;
1665 }
1666
1667 if (!bad)
1668 {
1669 if (j <= 0 || j > N_PRDTE)
1670 panic("at_wini", "bad prdt index", j);
1671 prdt[j-1].prdte_flags |= PRDTE_FL_EOT;
1672
1673 #if 0
1674 for (i= 0; i<j; i++)
1675 {
1676 printf("prdt[%d]: base 0x%x, size %d, flags 0x%x\n",
1677 i, prdt[i].prdte_base, prdt[i].prdte_count,
1678 prdt[i].prdte_flags);
1679 }
1680 #endif
1681 }
1682
1683 /* The caller needs to perform a copy-out from the dma buffer if
1684 * this is a read request and we can't DMA directly to the user's
1685 * buffers.
1686 */
1687 *do_copyoutp= (!do_write && bad);
1688
1689 if (bad)
1690 {
1691 /* Adjust request size */
1692 size= *sizep;
1693 if (size > ATA_DMA_BUF_SIZE)
1694 *sizep= size= ATA_DMA_BUF_SIZE;
1695
1696 if (do_write)
1697 {
1698 /* Copy-in */
1699 for (offset= 0; offset < size; offset += n)
1700 {
1701 n= size-offset;
1702 if (n > iov->iov_size)
1703 n= iov->iov_size;
1704
1705 if(safe) {
1706 r= sys_safecopyfrom(proc_nr, iov->iov_addr,
1707 0, (vir_bytes)dma_buf+offset, n, D);
1708 } else {
1709 r= sys_vircopy(proc_nr, D, iov->iov_addr,
1710 SELF, D, (vir_bytes)dma_buf+offset,
1711 n);
1712 }
1713 if (r != OK)
1714 {
1715 panic(w_name(),
1716 "setup_dma: sys_vircopy failed",
1717 r);
1718 }
1719 iov++;
1720 }
1721 }
1722
1723 /* Fill-in the physical region descriptor table */
1724 phys= dma_buf_phys;
1725 if (phys & 1)
1726 {
1727 /* Two byte alignment is required */
1728 panic("at_wini", "bad buffer alignment in setup_dma",
1729 phys);
1730 }
1731 for (j= 0; j<N_PRDTE; i++)
1732 {
1733 if (size == 0)
1734 {
1735 panic("at_wini", "bad size in setup_dma",
1736 size);
1737 }
1738 if (size & 1)
1739 {
1740 /* Two byte alignment is required for size */
1741 panic("at_wini",
1742 "bad size alignment in setup_dma",
1743 size);
1744 }
1745 n= size;
1746
1747 /* Buffer is not allowed to cross a 64K boundary */
1748 if (phys / 0x10000 != (phys+n-1) / 0x10000)
1749 {
1750 n= ((phys/0x10000)+1)*0x10000 - phys;
1751 }
1752 prdt[j].prdte_base= phys;
1753 prdt[j].prdte_count= n;
1754 prdt[j].prdte_reserved= 0;
1755 prdt[j].prdte_flags= 0;
1756
1757 size -= n;
1758 if (size == 0)
1759 {
1760 prdt[j].prdte_flags |= PRDTE_FL_EOT;
1761 break;
1762 }
1763 }
1764 if (size != 0)
1765 panic("at_wini", "size to large for prdt", NO_NUM);
1766
1767 #if 0
1768 for (i= 0; i<=j; i++)
1769 {
1770 printf("prdt[%d]: base 0x%x, size %d, flags 0x%x\n",
1771 i, prdt[i].prdte_base, prdt[i].prdte_count,
1772 prdt[i].prdte_flags);
1773 }
1774 #endif
1775 }
1776
1777 /* Stop bus master operation */
1778 r= sys_outb(wn->base_dma + DMA_COMMAND, 0);
1779 if (r != 0) panic("at_wini", "setup_dma: sys_outb failed", r);
1780
1781 /* Verify that the bus master is not active */
1782 r= sys_inb(wn->base_dma + DMA_STATUS, &v);
1783 if (r != 0) panic("at_wini", "setup_dma: sys_inb failed", r);
1784 if (v & DMA_ST_BM_ACTIVE)
1785 panic("at_wini", "Bus master IDE active", NO_NUM);
1786
1787 if (prdt_phys & 3)
1788 panic("at_wini", "prdt not aligned", prdt_phys);
1789 r= sys_outl(wn->base_dma + DMA_PRDTP, prdt_phys);
1790 if (r != 0) panic("at_wini", "setup_dma: sys_outl failed", r);
1791
1792 /* Clear interrupt and error flags */
1793 r= sys_outb(wn->base_dma + DMA_STATUS, DMA_ST_INT | DMA_ST_ERROR);
1794 if (r != 0) panic("at_wini", "setup_dma: sys_outb failed", r);
1795
1796 /* Assume disk reads. Start DMA */
1797 v= DMA_CMD_START;
1798 if (!do_write)
1799 {
1800 /* Disk reads generate PCI write cycles. */
1801 v |= DMA_CMD_WRITE;
1802 }
1803 r= sys_outb(wn->base_dma + DMA_COMMAND, v);
1804 if (r != 0) panic("at_wini", "setup_dma: sys_outb failed", r);
1805
1806 #if 0
1807 r= sys_inb(wn->base_dma + DMA_STATUS, &v);
1808 if (r != 0) panic("at_wini", "setup_dma: sys_inb failed", r);
1809 printf("dma status: 0x%x\n", v);
1810 #endif
1811 }
1812
1813
1814 /*===========================================================================*
1815 * w_need_reset *
1816 *===========================================================================*/
1817 PRIVATE void w_need_reset()
1818 {
1819 /* The controller needs to be reset. */
1820 struct wini *wn;
1821 int dr = 0;
1822
1823 for (wn = wini; wn < &wini[MAX_DRIVES]; wn++, dr++) {
1824 if (wn->base_cmd == w_wn->base_cmd) {
1825 wn->state |= DEAF;
1826 wn->state &= ~INITIALIZED;
1827 }
1828 }
1829 }
1830
1831 /*===========================================================================*
1832 * w_do_close *
1833 *===========================================================================*/
1834 PRIVATE int w_do_close(dp, m_ptr)
1835 struct driver *dp;
1836 message *m_ptr;
1837 {
1838 /* Device close: Release a device. */
1839 if (w_prepare(m_ptr->DEVICE) == NIL_DEV)
1840 return(ENXIO);
1841 w_wn->open_ct--;
1842 #if ENABLE_ATAPI
1843 if (w_wn->open_ct == 0 && (w_wn->state & ATAPI)) atapi_close();
1844 #endif
1845 return(OK);
1846 }
1847
1848 /*===========================================================================*
1849 * com_simple *
1850 *===========================================================================*/
1851 PRIVATE int com_simple(cmd)
1852 struct command *cmd; /* Command block */
1853 {
1854 /* A simple controller command, only one interrupt and no data-out phase. */
1855 int r;
1856
1857 if (w_wn->state & IGNORING) return ERR;
1858
1859 if ((r = com_out(cmd)) == OK) r = at_intr_wait();
1860 w_command = CMD_IDLE;
1861 return(r);
1862 }
1863
1864 /*===========================================================================*
1865 * w_timeout *
1866 *===========================================================================*/
1867 PRIVATE void w_timeout(void)
1868 {
1869 struct wini *wn = w_wn;
1870
1871 switch (w_command) {
1872 case CMD_IDLE:
1873 break; /* fine */
1874 case CMD_READ:
1875 case CMD_READ_EXT:
1876 case CMD_WRITE:
1877 case CMD_WRITE_EXT:
1878 /* Impossible, but not on PC's: The controller does not respond. */
1879
1880 /* Limiting multisector I/O seems to help. */
1881 if (wn->max_count > 8 * SECTOR_SIZE) {
1882 wn->max_count = 8 * SECTOR_SIZE;
1883 } else {
1884 wn->max_count = SECTOR_SIZE;
1885 }
1886 /*FALL THROUGH*/
1887 default:
1888 /* Some other command. */
1889 if (w_testing) wn->state |= IGNORING; /* Kick out this drive. */
1890 else if (!w_silent) printf("%s: timeout on command 0x%02x\n",
1891 w_name(), w_command);
1892 w_need_reset();
1893 wn->w_status = 0;
1894 }
1895 }
1896
1897 /*===========================================================================*
1898 * w_reset *
1899 *===========================================================================*/
1900 PRIVATE int w_reset()
1901 {
1902 /* Issue a reset to the controller. This is done after any catastrophe,
1903 * like the controller refusing to respond.
1904 */
1905 int s;
1906 struct wini *wn = w_wn;
1907
1908 /* Don't bother if this drive is forgotten. */
1909 if (w_wn->state & IGNORING) return ERR;
1910
1911 /* Wait for any internal drive recovery. */
1912 tickdelay(RECOVERY_TICKS);
1913
1914 /* Strobe reset bit */
1915 if ((s=sys_outb(wn->base_ctl + REG_CTL, CTL_RESET)) != OK)
1916 panic(w_name(),"Couldn't strobe reset bit",s);
1917 tickdelay(DELAY_TICKS);
1918 if ((s=sys_outb(wn->base_ctl + REG_CTL, 0)) != OK)
1919 panic(w_name(),"Couldn't strobe reset bit",s);
1920 tickdelay(DELAY_TICKS);
1921
1922 /* Wait for controller ready */
1923 if (!w_waitfor(STATUS_BSY, 0)) {
1924 printf("%s: reset failed, drive busy\n", w_name());
1925 return(ERR);
1926 }
1927
1928 /* The error register should be checked now, but some drives mess it up. */
1929
1930 for (wn = wini; wn < &wini[MAX_DRIVES]; wn++) {
1931 if (wn->base_cmd == w_wn->base_cmd) {
1932 wn->state &= ~DEAF;
1933 if (w_wn->irq_need_ack) {
1934 /* Make sure irq is actually enabled.. */
1935 sys_irqenable(&w_wn->irq_hook_id);
1936 }
1937 }
1938 }
1939
1940
1941 return(OK);
1942 }
1943
1944 /*===========================================================================*
1945 * w_intr_wait *
1946 *===========================================================================*/
1947 PRIVATE void w_intr_wait()
1948 {
1949 /* Wait for a task completion interrupt. */
1950
1951 int r;
1952 unsigned long w_status;
1953 message m;
1954
1955 if (w_wn->irq != NO_IRQ) {
1956 /* Wait for an interrupt that sets w_status to "not busy".
1957 * (w_timeout() also clears w_status.)
1958 */
1959 while (w_wn->w_status & (STATUS_ADMBSY|STATUS_BSY)) {
1960 int rr;
1961 if((rr=receive(ANY, &m)) != OK)
1962 panic("at_wini", "receive(ANY) failed", rr);
1963 switch(m.m_type) {
1964 case SYN_ALARM:
1965 /* Timeout. */
1966 w_timeout(); /* a.o. set w_status */
1967 break;
1968 case HARD_INT:
1969 /* Interrupt. */
1970 r= sys_inb(w_wn->base_cmd + REG_STATUS, &w_status);
1971 if (r != 0)
1972 panic("at_wini", "sys_inb failed", r);
1973 w_wn->w_status= w_status;
1974 ack_irqs(m.NOTIFY_ARG);
1975 break;
1976 case DEV_PING:
1977 /* RS monitor ping. */
1978 notify(m.m_source);
1979 break;
1980 default:
1981 /* unhandled message.
1982 * queue it and handle it in the libdriver loop.
1983 */
1984 mq_queue(&m);
1985 }
1986 }
1987 } else {
1988 /* Interrupt not yet allocated; use polling. */
1989 (void) w_waitfor(STATUS_BSY, 0);
1990 }
1991 }
1992
1993 /*===========================================================================*
1994 * at_intr_wait *
1995 *===========================================================================*/
1996 PRIVATE int at_intr_wait()
1997 {
1998 /* Wait for an interrupt, study the status bits and return error/success. */
1999 int r, s;
2000 unsigned long inbval;
2001
2002 w_intr_wait();
2003 if ((w_wn->w_status & (STATUS_BSY | STATUS_WF | STATUS_ERR)) == 0) {
2004 r = OK;
2005 } else {
2006 if ((s=sys_inb(w_wn->base_cmd + REG_ERROR, &inbval)) != OK)
2007 panic(w_name(),"Couldn't read register",s);
2008 if ((w_wn->w_status & STATUS_ERR) && (inbval & ERROR_BB)) {
2009 r = ERR_BAD_SECTOR; /* sector marked bad, retries won't help */
2010 } else {
2011 r = ERR; /* any other error */
2012 }
2013 }
2014 w_wn->w_status |= STATUS_ADMBSY; /* assume still busy with I/O */
2015 return(r);
2016 }
2017
2018 /*===========================================================================*
2019 * w_waitfor *
2020 *===========================================================================*/
2021 PRIVATE int w_waitfor(mask, value)
2022 int mask; /* status mask */
2023 int value; /* required status */
2024 {
2025 /* Wait until controller is in the required state. Return zero on timeout.
2026 * An alarm that set a timeout flag is used. TIMEOUT is in micros, we need
2027 * ticks. Disabling the alarm is not needed, because a static flag is used
2028 * and a leftover timeout cannot do any harm.
2029 */
2030 unsigned long w_status;
2031 clock_t t0, t1;
2032 int s;
2033
2034 getuptime(&t0);
2035 do {
2036 if ((s=sys_inb(w_wn->base_cmd + REG_STATUS, &w_status)) != OK)
2037 panic(w_name(),"Couldn't read register",s);
2038 w_wn->w_status= w_status;
2039 if ((w_wn->w_status & mask) == value) {
2040 return 1;
2041 }
2042 } while ((s=getuptime(&t1)) == OK && (t1-t0) < timeout_ticks );
2043 if (OK != s) printf("AT_WINI: warning, get_uptime failed: %d\n",s);
2044
2045 w_need_reset(); /* controller gone deaf */
2046 return(0);
2047 }
2048
2049 /*===========================================================================*
2050 * w_waitfor_dma *
2051 *===========================================================================*/
2052 PRIVATE int w_waitfor_dma(mask, value)
2053 int mask; /* status mask */
2054 int value; /* required status */
2055 {
2056 /* Wait until controller is in the required state. Return zero on timeout.
2057 * An alarm that set a timeout flag is used. TIMEOUT is in micros, we need
2058 * ticks. Disabling the alarm is not needed, because a static flag is used
2059 * and a leftover timeout cannot do any harm.
2060 */
2061 unsigned long w_status;
2062 clock_t t0, t1;
2063 int s;
2064
2065 getuptime(&t0);
2066 do {
2067 if ((s=sys_inb(w_wn->base_dma + DMA_STATUS, &w_status)) != OK)
2068 panic(w_name(),"Couldn't read register",s);
2069 if ((w_status & mask) == value) {
2070 return 1;
2071 }
2072 } while ((s=getuptime(&t1)) == OK && (t1-t0) < timeout_ticks );
2073 if (OK != s) printf("AT_WINI: warning, get_uptime failed: %d\n",s);
2074
2075 return(0);
2076 }
2077
2078 /*===========================================================================*
2079 * w_geometry *
2080 *===========================================================================*/
2081 PRIVATE void w_geometry(entry)
2082 struct partition *entry;
2083 {
2084 struct wini *wn = w_wn;
2085
2086 if (wn->state & ATAPI) { /* Make up some numbers. */
2087 entry->cylinders = div64u(wn->part[0].dv_size, SECTOR_SIZE) / (64*32);
2088 entry->heads = 64;
2089 entry->sectors = 32;
2090 } else { /* Return logical geometry. */
2091 entry->cylinders = wn->lcylinders;
2092 entry->heads = wn->lheads;
2093 entry->sectors = wn->lsectors;
2094 }
2095 }
2096
2097 #if ENABLE_ATAPI
2098 /*===========================================================================*
2099 * atapi_open *
2100 *===========================================================================*/
2101 PRIVATE int atapi_open()
2102 {
2103 /* Should load and lock the device and obtain its size. For now just set the
2104 * size of the device to something big. What is really needed is a generic
2105 * SCSI layer that does all this stuff for ATAPI and SCSI devices (kjb). (XXX)
2106 */
2107 w_wn->part[0].dv_size = mul64u(800L*1024, 1024);
2108 return(OK);
2109 }
2110
2111 /*===========================================================================*
2112 * atapi_close *
2113 *===========================================================================*/
2114 PRIVATE void atapi_close()
2115 {
2116 /* Should unlock the device. For now do nothing. (XXX) */
2117 }
2118
2119 void sense_request(void)
2120 {
2121 int r, i;
2122 static u8_t sense[100], packet[ATAPI_PACKETSIZE];
2123
2124 packet[0] = SCSI_SENSE;
2125 packet[1] = 0;
2126 packet[2] = 0;
2127 packet[3] = 0;
2128 packet[4] = SENSE_PACKETSIZE;
2129 packet[5] = 0;
2130 packet[7] = 0;
2131 packet[8] = 0;
2132 packet[9] = 0;
2133 packet[10] = 0;
2134 packet[11] = 0;
2135
2136 for(i = 0; i < SENSE_PACKETSIZE; i++) sense[i] = 0xff;
2137 r = atapi_sendpacket(packet, SENSE_PACKETSIZE);
2138 if (r != OK) { printf("request sense command failed\n"); return; }
2139 if (atapi_intr_wait() <= 0) { printf("WARNING: request response failed\n"); }
2140
2141 if (sys_insw(w_wn->base_cmd + REG_DATA, SELF, (void *) sense, SENSE_PACKETSIZE) != OK)
2142 printf("WARNING: sense reading failed\n");
2143
2144 printf("sense data:");
2145 for(i = 0; i < SENSE_PACKETSIZE; i++) printf(" %02x", sense[i]);
2146 printf("\n");
2147 }
2148
2149 /*===========================================================================*
2150 * atapi_transfer *
2151 *===========================================================================*/
2152 PRIVATE int atapi_transfer(proc_nr, opcode, position, iov, nr_req, safe)
2153 int proc_nr; /* process doing the request */
2154 int opcode; /* DEV_GATHER_S or DEV_SCATTER_S */
2155 u64_t position; /* offset on device to read or write */
2156 iovec_t *iov; /* pointer to read or write request vector */
2157 unsigned nr_req; /* length of request vector */
2158 int safe; /* use safecopies? */
2159 {
2160 struct wini *wn = w_wn;
2161 iovec_t *iop, *iov_end = iov + nr_req;
2162 int r, s, errors, fresh;
2163 u64_t pos;
2164 unsigned long block;
2165 u64_t dv_size = w_dv->dv_size;
2166 unsigned nbytes, nblocks, count, before, chunk;
2167 static u8_t packet[ATAPI_PACKETSIZE];
2168 size_t addr_offset = 0;
2169
2170 errors = fresh = 0;
2171
2172 while (nr_req > 0 && !fresh) {
2173 /* The Minix block size is smaller than the CD block size, so we
2174 * may have to read extra before or after the good data.
2175 */
2176 pos = add64(w_dv->dv_base, position);
2177 block = div64u(pos, CD_SECTOR_SIZE);
2178 before = rem64u(pos, CD_SECTOR_SIZE);
2179
2180 /* How many bytes to transfer? */
2181 nbytes = count = 0;
2182 for (iop = iov; iop < iov_end; iop++) {
2183 nbytes += iop->iov_size;
2184 if ((before + nbytes) % CD_SECTOR_SIZE == 0) count = nbytes;
2185 }
2186
2187 /* Does one of the memory chunks end nicely on a CD sector multiple? */
2188 if (count != 0) nbytes = count;
2189
2190 /* Data comes in as words, so we have to enforce even byte counts. */
2191 if ((before | nbytes) & 1) return(EINVAL);
2192
2193 /* Which block on disk and how close to EOF? */
2194 if (cmp64(position, dv_size) >= 0) return(OK); /* At EOF */
2195 if (cmp64(add64ul(position, nbytes), dv_size) > 0)
2196 nbytes = diff64(dv_size, position);
2197
2198 nblocks = (before + nbytes + CD_SECTOR_SIZE - 1) / CD_SECTOR_SIZE;
2199 if (ATAPI_DEBUG) {
2200 printf("block=%lu, before=%u, nbytes=%u, nblocks=%u\n",
2201 block, before, nbytes, nblocks);
2202 }
2203
2204 /* First check to see if a reinitialization is needed. */
2205 if (!(wn->state & INITIALIZED) && w_specify() != OK) return(EIO);
2206
2207 /* Build an ATAPI command packet. */
2208 packet[0] = SCSI_READ10;
2209 packet[1] = 0;
2210 packet[2] = (block >> 24) & 0xFF;
2211 packet[3] = (block >> 16) & 0xFF;
2212 packet[4] = (block >> 8) & 0xFF;
2213 packet[5] = (block >> 0) & 0xFF;
2214 packet[6] = 0;
2215 packet[7] = (nblocks >> 8) & 0xFF;
2216 packet[8] = (nblocks >> 0) & 0xFF;
2217 packet[9] = 0;
2218 packet[10] = 0;
2219 packet[11] = 0;
2220
2221 /* Tell the controller to execute the packet command. */
2222 r = atapi_sendpacket(packet, nblocks * CD_SECTOR_SIZE);
2223 if (r != OK) goto err;
2224
2225 /* Read chunks of data. */
2226 while ((r = atapi_intr_wait()) > 0) {
2227 count = r;
2228
2229 if (ATAPI_DEBUG) {
2230 printf("before=%u, nbytes=%u, count=%u\n",
2231 before, nbytes, count);
2232 }
2233
2234 while (before > 0 && count > 0) { /* Discard before. */
2235 chunk = before;
2236 if (chunk > count) chunk = count;
2237 if (chunk > DMA_BUF_SIZE) chunk = DMA_BUF_SIZE;
2238 if ((s=sys_insw(wn->base_cmd + REG_DATA, SELF, tmp_buf, chunk)) != OK)
2239 panic(w_name(),"Call to sys_insw() failed", s);
2240 before -= chunk;
2241 count -= chunk;
2242 }
2243
2244 while (nbytes > 0 && count > 0) { /* Requested data. */
2245 chunk = nbytes;
2246 if (chunk > count) chunk = count;
2247 if (chunk > iov->iov_size) chunk = iov->iov_size;
2248 if(safe) {
2249 s=sys_safe_insw(wn->base_cmd + REG_DATA, proc_nr,
2250 (void *) iov->iov_addr, addr_offset, chunk);
2251 } else {
2252 s=sys_insw(wn->base_cmd + REG_DATA, proc_nr,
2253 (void *) (iov->iov_addr + addr_offset), chunk);
2254 }
2255 if (s != OK)
2256 panic(w_name(),"Call to sys_insw() failed", s);
2257 position= add64ul(position, chunk);
2258 nbytes -= chunk;
2259 count -= chunk;
2260 addr_offset += chunk;
2261 fresh = 0;
2262 if ((iov->iov_size -= chunk) == 0) {
2263 iov++;
2264 nr_req--;
2265 fresh = 1; /* new element is optional */
2266 addr_offset = 0;
2267 }
2268 }
2269
2270 while (count > 0) { /* Excess data. */
2271 chunk = count;
2272 if (chunk > DMA_BUF_SIZE) chunk = DMA_BUF_SIZE;
2273 if ((s=sys_insw(wn->base_cmd + REG_DATA, SELF, tmp_buf, chunk)) != OK)
2274 panic(w_name(),"Call to sys_insw() failed", s);
2275 count -= chunk;
2276 }
2277 }
2278
2279 if (r < 0) {
2280 err: /* Don't retry if too many errors. */
2281 if (atapi_debug) sense_request();
2282 if (++errors == max_errors) {
2283 w_command = CMD_IDLE;
2284 if (atapi_debug) printf("giving up (%d)\n", errors);
2285 return(EIO);
2286 }
2287 if (atapi_debug) printf("retry (%d)\n", errors);
2288 }
2289 }
2290
2291 w_command = CMD_IDLE;
2292 return(OK);
2293 }
2294
2295 /*===========================================================================*
2296 * atapi_sendpacket *
2297 *===========================================================================*/
2298 PRIVATE int atapi_sendpacket(packet, cnt)
2299 u8_t *packet;
2300 unsigned cnt;
2301 {
2302 /* Send an Atapi Packet Command */
2303 struct wini *wn = w_wn;
2304 pvb_pair_t outbyte[6]; /* vector for sys_voutb() */
2305 int s;
2306
2307 if (wn->state & IGNORING) return ERR;
2308
2309 /* Select Master/Slave drive */
2310 if ((s=sys_outb(wn->base_cmd + REG_DRIVE, wn->ldhpref)) != OK)
2311 panic(w_name(),"Couldn't select master/ slave drive",s);
2312
2313 if (!w_waitfor(STATUS_BSY | STATUS_DRQ, 0)) {
2314 printf("%s: atapi_sendpacket: drive not ready\n", w_name());
2315 return(ERR);
2316 }
2317
2318 /* Schedule a wakeup call, some controllers are flaky. This is done with
2319 * a synchronous alarm. If a timeout occurs a SYN_ALARM message is sent
2320 * from HARDWARE, so that w_intr_wait() can call w_timeout() in case the
2321 * controller was not able to execute the command. Leftover timeouts are
2322 * simply ignored by the main loop.
2323 */
2324 sys_setalarm(wakeup_ticks, 0);
2325
2326 #if _WORD_SIZE > 2
2327 if (cnt > 0xFFFE) cnt = 0xFFFE; /* Max data per interrupt. */
2328 #endif
2329
2330 w_command = ATAPI_PACKETCMD;
2331 pv_set(outbyte[0], wn->base_cmd + REG_FEAT, 0);
2332 pv_set(outbyte[1], wn->base_cmd + REG_IRR, 0);
2333 pv_set(outbyte[2], wn->base_cmd + REG_SAMTAG, 0);
2334 pv_set(outbyte[3], wn->base_cmd + REG_CNT_LO, (cnt >> 0) & 0xFF);
2335 pv_set(outbyte[4], wn->base_cmd + REG_CNT_HI, (cnt >> 8) & 0xFF);
2336 pv_set(outbyte[5], wn->base_cmd + REG_COMMAND, w_command);
2337 if (atapi_debug) printf("cmd: %x ", w_command);
2338 if ((s=sys_voutb(outbyte,6)) != OK)
2339 panic(w_name(),"Couldn't write registers with sys_voutb()",s);
2340
2341 if (!w_waitfor(STATUS_BSY | STATUS_DRQ, STATUS_DRQ)) {
2342 printf("%s: timeout (BSY|DRQ -> DRQ)\n", w_name());
2343 return(ERR);
2344 }
2345 wn->w_status |= STATUS_ADMBSY; /* Command not at all done yet. */
2346
2347 /* Send the command packet to the device. */
2348 if ((s=sys_outsw(wn->base_cmd + REG_DATA, SELF, packet, ATAPI_PACKETSIZE)) != OK)
2349 panic(w_name(),"sys_outsw() failed", s);
2350
2351 {
2352 int p;
2353 if (atapi_debug) {
2354 printf("sent command:");
2355 for(p = 0; p < ATAPI_PACKETSIZE; p++) { printf(" %02x", packet[p]); }
2356 printf("\n");
2357 }
2358 }
2359 return(OK);
2360 }
2361
2362
2363 #endif /* ENABLE_ATAPI */
2364
2365 /*===========================================================================*
2366 * w_other *
2367 *===========================================================================*/
2368 PRIVATE int w_other(dr, m, safe)
2369 struct driver *dr;
2370 message *m;
2371 int safe;
2372 {
2373 int r, timeout, prev;
2374
2375 if (m->m_type != DEV_IOCTL_S )
2376 return EINVAL;
2377
2378 if (m->REQUEST == DIOCTIMEOUT) {
2379 if(safe) {
2380 r= sys_safecopyfrom(m->IO_ENDPT, (vir_bytes) m->IO_GRANT,
2381 0, (vir_bytes)&timeout, sizeof(timeout), D);
2382 } else {
2383 r= sys_datacopy(m->IO_ENDPT, (vir_bytes)m->ADDRESS,
2384 SELF, (vir_bytes)&timeout, sizeof(timeout));
2385 }
2386
2387 if(r != OK)
2388 return r;
2389
2390 if (timeout == 0) {
2391 /* Restore defaults. */
2392 timeout_ticks = DEF_TIMEOUT_TICKS;
2393 max_errors = MAX_ERRORS;
2394 wakeup_ticks = WAKEUP_TICKS;
2395 w_silent = 0;
2396 } else if (timeout < 0) {
2397 return EINVAL;
2398 } else {
2399 prev = wakeup_ticks;
2400
2401 if (!w_standard_timeouts) {
2402 /* Set (lower) timeout, lower error
2403 * tolerance and set silent mode.
2404 */
2405 wakeup_ticks = timeout;
2406 max_errors = 3;
2407 w_silent = 1;
2408
2409 if (timeout_ticks > timeout)
2410 timeout_ticks = timeout;
2411 }
2412
2413 if(safe) {
2414 r= sys_safecopyto(m->IO_ENDPT,
2415 (vir_bytes) m->IO_GRANT,
2416 0, (vir_bytes)&prev, sizeof(prev), D);
2417 } else {
2418 r=sys_datacopy(SELF, (vir_bytes)&prev,
2419 m->IO_ENDPT, (vir_bytes)m->ADDRESS,
2420 sizeof(prev));
2421 }
2422
2423 if(r != OK)
2424 return r;
2425 }
2426
2427 return OK;
2428 } else if (m->REQUEST == DIOCOPENCT) {
2429 int count;
2430 if (w_prepare(m->DEVICE) == NIL_DEV) return ENXIO;
2431 count = w_wn->open_ct;
2432 if(safe) {
2433 r= sys_safecopyto(m->IO_ENDPT, (vir_bytes) m->IO_GRANT,
2434 0, (vir_bytes)&count, sizeof(count), D);
2435 } else {
2436 r=sys_datacopy(SELF, (vir_bytes)&count,
2437 m->IO_ENDPT, (vir_bytes)m->ADDRESS, sizeof(count));
2438 }
2439
2440 if(r != OK)
2441 return r;
2442
2443 return OK;
2444 }
2445 return EINVAL;
2446 }
2447
2448 /*===========================================================================*
2449 * w_hw_int *
2450 *===========================================================================*/
2451 PRIVATE int w_hw_int(dr, m)
2452 struct driver *dr;
2453 message *m;
2454 {
2455 /* Leftover interrupt(s) received; ack it/them. */
2456 ack_irqs(m->NOTIFY_ARG);
2457
2458 return OK;
2459 }
2460
2461
2462 /*===========================================================================*
2463 * ack_irqs *
2464 *===========================================================================*/
2465 PRIVATE void ack_irqs(unsigned int irqs)
2466 {
2467 unsigned int drive;
2468 unsigned long w_status;
2469
2470 for (drive = 0; drive < MAX_DRIVES && irqs; drive++) {
2471 if (!(wini[drive].state & IGNORING) && wini[drive].irq_need_ack &&
2472 (wini[drive].irq_mask & irqs)) {
2473 if (sys_inb((wini[drive].base_cmd + REG_STATUS),
2474 &w_status) != OK)
2475 {
2476 panic(w_name(), "couldn't ack irq on drive %d\n",
2477 drive);
2478 }
2479 wini[drive].w_status= w_status;
2480 if (sys_irqenable(&wini[drive].irq_hook_id) != OK)
2481 printf("couldn't re-enable drive %d\n", drive);
2482 irqs &= ~wini[drive].irq_mask;
2483 }
2484 }
2485 }
2486
2487
2488 #define STSTR(a) if (status & STATUS_ ## a) { strcat(str, #a); strcat(str, " "); }
2489 #define ERRSTR(a) if (e & ERROR_ ## a) { strcat(str, #a); strcat(str, " "); }
2490 char *strstatus(int status)
2491 {
2492 static char str[200];
2493 str[0] = '\0';
2494
2495 STSTR(BSY);
2496 STSTR(DRDY);
2497 STSTR(DMADF);
2498 STSTR(SRVCDSC);
2499 STSTR(DRQ);
2500 STSTR(CORR);
2501 STSTR(CHECK);
2502 return str;
2503 }
2504
2505 char *strerr(int e)
2506 {
2507 static char str[200];
2508 str[0] = '\0';
2509
2510 ERRSTR(BB);
2511 ERRSTR(ECC);
2512 ERRSTR(ID);
2513 ERRSTR(AC);
2514 ERRSTR(TK);
2515 ERRSTR(DM);
2516
2517 return str;
2518 }
2519
2520 #if ENABLE_ATAPI
2521
2522 /*===========================================================================*
2523 * atapi_intr_wait *
2524 *===========================================================================*/
2525 PRIVATE int atapi_intr_wait()
2526 {
2527 /* Wait for an interrupt and study the results. Returns a number of bytes
2528 * that need to be transferred, or an error code.
2529 */
2530 struct wini *wn = w_wn;
2531 pvb_pair_t inbyte[4]; /* vector for sys_vinb() */
2532 int s; /* status for sys_vinb() */
2533 int e;
2534 int len;
2535 int irr;
2536 int r;
2537 int phase;
2538
2539 w_intr_wait();
2540
2541 /* Request series of device I/O. */
2542 inbyte[0].port = wn->base_cmd + REG_ERROR;
2543 inbyte[1].port = wn->base_cmd + REG_CNT_LO;
2544 inbyte[2].port = wn->base_cmd + REG_CNT_HI;
2545 inbyte[3].port = wn->base_cmd + REG_IRR;
2546 if ((s=sys_vinb(inbyte, 4)) != OK)
2547 panic(w_name(),"ATAPI failed sys_vinb()", s);
2548 e = inbyte[0].value;
2549 len = inbyte[1].value;
2550 len |= inbyte[2].value << 8;
2551 irr = inbyte[3].value;
2552
2553 #if ATAPI_DEBUG
2554 printf("wn %p S=%x=%s E=%02x=%s L=%04x I=%02x\n", wn, wn->w_status, strstatus(wn->w_status), e, strerr(e), len, irr);
2555 #endif
2556 if (wn->w_status & (STATUS_BSY | STATUS_CHECK)) {
2557 if (atapi_debug) {
2558 printf("atapi fail: S=%x=%s E=%02x=%s L=%04x I=%02x\n", wn->w_status, strstatus(wn->w_status), e, strerr(e), len, irr);
2559 }
2560 return ERR;
2561 }
2562
2563 phase = (wn->w_status & STATUS_DRQ) | (irr & (IRR_COD | IRR_IO));
2564
2565 switch (phase) {
2566 case IRR_COD | IRR_IO:
2567 if (ATAPI_DEBUG) printf("ACD: Phase Command Complete\n");
2568 r = OK;
2569 break;
2570 case 0:
2571 if (ATAPI_DEBUG) printf("ACD: Phase Command Aborted\n");
2572 r = ERR;
2573 break;
2574 case STATUS_DRQ | IRR_COD:
2575 if (ATAPI_DEBUG) printf("ACD: Phase Command Out\n");
2576 r = ERR;
2577 break;
2578 case STATUS_DRQ:
2579 if (ATAPI_DEBUG) printf("ACD: Phase Data Out %d\n", len);
2580 r = len;
2581 break;
2582 case STATUS_DRQ | IRR_IO:
2583 if (ATAPI_DEBUG) printf("ACD: Phase Data In %d\n", len);
2584 r = len;
2585 break;
2586 default:
2587 if (ATAPI_DEBUG) printf("ACD: Phase Unknown\n");
2588 r = ERR;
2589 break;
2590 }
2591
2592 #if 0
2593 /* retry if the media changed */
2594 XXX while (phase == (IRR_IO | IRR_COD) && (wn->w_status & STATUS_CHECK)
2595 && (e & ERROR_SENSE) == SENSE_UATTN && --try > 0);
2596 #endif
2597
2598 wn->w_status |= STATUS_ADMBSY; /* Assume not done yet. */
2599 return(r);
2600 }
2601
2602 #endif /* ENABLE_ATAPI */
2603
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