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"[PATCH] Fix leaks on /proc/{*/sched,sched_debug,timer_list,timer_stats}" and
[mmotm.git] / arch / arm / mach-davinci / da850.c
blobfcf74e62423046bf74387c11d4fc6d5bf13fea49
1 /*
2 * TI DA850/OMAP-L138 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-davinci/da830.c
7 * Original Copyrights follow:
8 *
9 * 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14 #include <linux/init.h>
15 #include <linux/clk.h>
16 #include <linux/cpufreq.h>
17 #include <linux/regulator/consumer.h>
18
19 #include <asm/mach/map.h>
20
21 #include <mach/psc.h>
22 #include <mach/irqs.h>
23 #include <mach/cputype.h>
24 #include <mach/common.h>
25 #include <mach/time.h>
26 #include <mach/da8xx.h>
27 #include <mach/cpufreq.h>
28
29 #include "clock.h"
30 #include "mux.h"
31
32 /* SoC specific clock flags */
33 #define DA850_CLK_ASYNC3 BIT(16)
34
35 #define DA850_PLL1_BASE 0x01e1a000
36 #define DA850_TIMER64P2_BASE 0x01f0c000
37 #define DA850_TIMER64P3_BASE 0x01f0d000
38
39 #define DA850_REF_FREQ 24000000
40
41 #define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
42 #define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
43
44 static int da850_set_armrate(struct clk *clk, unsigned long rate);
45 static int da850_round_armrate(struct clk *clk, unsigned long rate);
46 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
47
48 static struct pll_data pll0_data = {
49 .num = 1,
50 .phys_base = DA8XX_PLL0_BASE,
51 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
52 };
53
54 static struct clk ref_clk = {
55 .name = "ref_clk",
56 .rate = DA850_REF_FREQ,
57 };
58
59 static struct clk pll0_clk = {
60 .name = "pll0",
61 .parent = &ref_clk,
62 .pll_data = &pll0_data,
63 .flags = CLK_PLL,
64 .set_rate = da850_set_pll0rate,
65 };
66
67 static struct clk pll0_aux_clk = {
68 .name = "pll0_aux_clk",
69 .parent = &pll0_clk,
70 .flags = CLK_PLL | PRE_PLL,
71 };
72
73 static struct clk pll0_sysclk2 = {
74 .name = "pll0_sysclk2",
75 .parent = &pll0_clk,
76 .flags = CLK_PLL,
77 .div_reg = PLLDIV2,
78 };
79
80 static struct clk pll0_sysclk3 = {
81 .name = "pll0_sysclk3",
82 .parent = &pll0_clk,
83 .flags = CLK_PLL,
84 .div_reg = PLLDIV3,
85 };
86
87 static struct clk pll0_sysclk4 = {
88 .name = "pll0_sysclk4",
89 .parent = &pll0_clk,
90 .flags = CLK_PLL,
91 .div_reg = PLLDIV4,
92 };
93
94 static struct clk pll0_sysclk5 = {
95 .name = "pll0_sysclk5",
96 .parent = &pll0_clk,
97 .flags = CLK_PLL,
98 .div_reg = PLLDIV5,
99 };
100
101 static struct clk pll0_sysclk6 = {
102 .name = "pll0_sysclk6",
103 .parent = &pll0_clk,
104 .flags = CLK_PLL,
105 .div_reg = PLLDIV6,
106 };
107
108 static struct clk pll0_sysclk7 = {
109 .name = "pll0_sysclk7",
110 .parent = &pll0_clk,
111 .flags = CLK_PLL,
112 .div_reg = PLLDIV7,
113 };
114
115 static struct pll_data pll1_data = {
116 .num = 2,
117 .phys_base = DA850_PLL1_BASE,
118 .flags = PLL_HAS_POSTDIV,
119 };
120
121 static struct clk pll1_clk = {
122 .name = "pll1",
123 .parent = &ref_clk,
124 .pll_data = &pll1_data,
125 .flags = CLK_PLL,
126 };
127
128 static struct clk pll1_aux_clk = {
129 .name = "pll1_aux_clk",
130 .parent = &pll1_clk,
131 .flags = CLK_PLL | PRE_PLL,
132 };
133
134 static struct clk pll1_sysclk2 = {
135 .name = "pll1_sysclk2",
136 .parent = &pll1_clk,
137 .flags = CLK_PLL,
138 .div_reg = PLLDIV2,
139 };
140
141 static struct clk pll1_sysclk3 = {
142 .name = "pll1_sysclk3",
143 .parent = &pll1_clk,
144 .flags = CLK_PLL,
145 .div_reg = PLLDIV3,
146 };
147
148 static struct clk pll1_sysclk4 = {
149 .name = "pll1_sysclk4",
150 .parent = &pll1_clk,
151 .flags = CLK_PLL,
152 .div_reg = PLLDIV4,
153 };
154
155 static struct clk pll1_sysclk5 = {
156 .name = "pll1_sysclk5",
157 .parent = &pll1_clk,
158 .flags = CLK_PLL,
159 .div_reg = PLLDIV5,
160 };
161
162 static struct clk pll1_sysclk6 = {
163 .name = "pll0_sysclk6",
164 .parent = &pll0_clk,
165 .flags = CLK_PLL,
166 .div_reg = PLLDIV6,
167 };
168
169 static struct clk pll1_sysclk7 = {
170 .name = "pll1_sysclk7",
171 .parent = &pll1_clk,
172 .flags = CLK_PLL,
173 .div_reg = PLLDIV7,
174 };
175
176 static struct clk i2c0_clk = {
177 .name = "i2c0",
178 .parent = &pll0_aux_clk,
179 };
180
181 static struct clk timerp64_0_clk = {
182 .name = "timer0",
183 .parent = &pll0_aux_clk,
184 };
185
186 static struct clk timerp64_1_clk = {
187 .name = "timer1",
188 .parent = &pll0_aux_clk,
189 };
190
191 static struct clk arm_rom_clk = {
192 .name = "arm_rom",
193 .parent = &pll0_sysclk2,
194 .lpsc = DA8XX_LPSC0_ARM_RAM_ROM,
195 .flags = ALWAYS_ENABLED,
196 };
197
198 static struct clk tpcc0_clk = {
199 .name = "tpcc0",
200 .parent = &pll0_sysclk2,
201 .lpsc = DA8XX_LPSC0_TPCC,
202 .flags = ALWAYS_ENABLED | CLK_PSC,
203 };
204
205 static struct clk tptc0_clk = {
206 .name = "tptc0",
207 .parent = &pll0_sysclk2,
208 .lpsc = DA8XX_LPSC0_TPTC0,
209 .flags = ALWAYS_ENABLED,
210 };
211
212 static struct clk tptc1_clk = {
213 .name = "tptc1",
214 .parent = &pll0_sysclk2,
215 .lpsc = DA8XX_LPSC0_TPTC1,
216 .flags = ALWAYS_ENABLED,
217 };
218
219 static struct clk tpcc1_clk = {
220 .name = "tpcc1",
221 .parent = &pll0_sysclk2,
222 .lpsc = DA850_LPSC1_TPCC1,
223 .gpsc = 1,
224 .flags = CLK_PSC | ALWAYS_ENABLED,
225 };
226
227 static struct clk tptc2_clk = {
228 .name = "tptc2",
229 .parent = &pll0_sysclk2,
230 .lpsc = DA850_LPSC1_TPTC2,
231 .gpsc = 1,
232 .flags = ALWAYS_ENABLED,
233 };
234
235 static struct clk uart0_clk = {
236 .name = "uart0",
237 .parent = &pll0_sysclk2,
238 .lpsc = DA8XX_LPSC0_UART0,
239 };
240
241 static struct clk uart1_clk = {
242 .name = "uart1",
243 .parent = &pll0_sysclk2,
244 .lpsc = DA8XX_LPSC1_UART1,
245 .gpsc = 1,
246 .flags = DA850_CLK_ASYNC3,
247 };
248
249 static struct clk uart2_clk = {
250 .name = "uart2",
251 .parent = &pll0_sysclk2,
252 .lpsc = DA8XX_LPSC1_UART2,
253 .gpsc = 1,
254 .flags = DA850_CLK_ASYNC3,
255 };
256
257 static struct clk aintc_clk = {
258 .name = "aintc",
259 .parent = &pll0_sysclk4,
260 .lpsc = DA8XX_LPSC0_AINTC,
261 .flags = ALWAYS_ENABLED,
262 };
263
264 static struct clk gpio_clk = {
265 .name = "gpio",
266 .parent = &pll0_sysclk4,
267 .lpsc = DA8XX_LPSC1_GPIO,
268 .gpsc = 1,
269 };
270
271 static struct clk i2c1_clk = {
272 .name = "i2c1",
273 .parent = &pll0_sysclk4,
274 .lpsc = DA8XX_LPSC1_I2C,
275 .gpsc = 1,
276 };
277
278 static struct clk emif3_clk = {
279 .name = "emif3",
280 .parent = &pll0_sysclk5,
281 .lpsc = DA8XX_LPSC1_EMIF3C,
282 .gpsc = 1,
283 .flags = ALWAYS_ENABLED,
284 };
285
286 static struct clk arm_clk = {
287 .name = "arm",
288 .parent = &pll0_sysclk6,
289 .lpsc = DA8XX_LPSC0_ARM,
290 .flags = ALWAYS_ENABLED,
291 .set_rate = da850_set_armrate,
292 .round_rate = da850_round_armrate,
293 };
294
295 static struct clk rmii_clk = {
296 .name = "rmii",
297 .parent = &pll0_sysclk7,
298 };
299
300 static struct clk emac_clk = {
301 .name = "emac",
302 .parent = &pll0_sysclk4,
303 .lpsc = DA8XX_LPSC1_CPGMAC,
304 .gpsc = 1,
305 };
306
307 static struct clk mcasp_clk = {
308 .name = "mcasp",
309 .parent = &pll0_sysclk2,
310 .lpsc = DA8XX_LPSC1_McASP0,
311 .gpsc = 1,
312 };
313
314 static struct clk lcdc_clk = {
315 .name = "lcdc",
316 .parent = &pll0_sysclk2,
317 .lpsc = DA8XX_LPSC1_LCDC,
318 .gpsc = 1,
319 };
320
321 static struct clk mmcsd_clk = {
322 .name = "mmcsd",
323 .parent = &pll0_sysclk2,
324 .lpsc = DA8XX_LPSC0_MMC_SD,
325 };
326
327 static struct clk aemif_clk = {
328 .name = "aemif",
329 .parent = &pll0_sysclk3,
330 .lpsc = DA8XX_LPSC0_EMIF25,
331 .flags = ALWAYS_ENABLED,
332 };
333
334 static struct davinci_clk da850_clks[] = {
335 CLK(NULL, "ref", &ref_clk),
336 CLK(NULL, "pll0", &pll0_clk),
337 CLK(NULL, "pll0_aux", &pll0_aux_clk),
338 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
339 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
340 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
341 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
342 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
343 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
344 CLK(NULL, "pll1", &pll1_clk),
345 CLK(NULL, "pll1_aux", &pll1_aux_clk),
346 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
347 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
348 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
349 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
350 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
351 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
352 CLK("i2c_davinci.1", NULL, &i2c0_clk),
353 CLK(NULL, "timer0", &timerp64_0_clk),
354 CLK("watchdog", NULL, &timerp64_1_clk),
355 CLK(NULL, "arm_rom", &arm_rom_clk),
356 CLK(NULL, "tpcc0", &tpcc0_clk),
357 CLK(NULL, "tptc0", &tptc0_clk),
358 CLK(NULL, "tptc1", &tptc1_clk),
359 CLK(NULL, "tpcc1", &tpcc1_clk),
360 CLK(NULL, "tptc2", &tptc2_clk),
361 CLK(NULL, "uart0", &uart0_clk),
362 CLK(NULL, "uart1", &uart1_clk),
363 CLK(NULL, "uart2", &uart2_clk),
364 CLK(NULL, "aintc", &aintc_clk),
365 CLK(NULL, "gpio", &gpio_clk),
366 CLK("i2c_davinci.2", NULL, &i2c1_clk),
367 CLK(NULL, "emif3", &emif3_clk),
368 CLK(NULL, "arm", &arm_clk),
369 CLK(NULL, "rmii", &rmii_clk),
370 CLK("davinci_emac.1", NULL, &emac_clk),
371 CLK("davinci-mcasp.0", NULL, &mcasp_clk),
372 CLK("da8xx_lcdc.0", NULL, &lcdc_clk),
373 CLK("davinci_mmc.0", NULL, &mmcsd_clk),
374 CLK(NULL, "aemif", &aemif_clk),
375 CLK(NULL, NULL, NULL),
376 };
377
378 /*
379 * Device specific mux setup
380 *
381 * soc description mux mode mode mux dbg
382 * reg offset mask mode
383 */
384 static const struct mux_config da850_pins[] = {
385 #ifdef CONFIG_DAVINCI_MUX
386 /* UART0 function */
387 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
388 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
389 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
390 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
391 /* UART1 function */
392 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
393 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
394 /* UART2 function */
395 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
396 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
397 /* I2C1 function */
398 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
399 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
400 /* I2C0 function */
401 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
402 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
403 /* EMAC function */
404 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
405 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
406 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
407 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
408 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
409 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
410 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
411 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
412 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
413 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
414 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
415 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
416 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
417 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
418 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
419 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
420 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
421 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false)
422 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false)
423 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false)
424 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false)
425 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false)
426 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false)
427 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false)
428 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false)
429 /* McASP function */
430 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
431 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
432 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
433 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
434 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
435 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
436 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
437 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
438 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
439 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
440 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
441 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
442 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
443 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
444 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
445 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
446 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
447 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
448 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
449 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
450 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
451 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
452 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
453 /* LCD function */
454 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false)
455 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false)
456 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false)
457 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false)
458 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false)
459 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false)
460 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
461 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false)
462 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false)
463 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false)
464 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false)
465 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false)
466 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false)
467 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false)
468 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
469 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false)
470 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false)
471 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
472 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false)
473 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false)
474 /* MMC/SD0 function */
475 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false)
476 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false)
477 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false)
478 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false)
479 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false)
480 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false)
481 /* EMIF2.5/EMIFA function */
482 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false)
483 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false)
484 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false)
485 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false)
486 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false)
487 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false)
488 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false)
489 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false)
490 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false)
491 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false)
492 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false)
493 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
494 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
495 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
496 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false)
497 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false)
498 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false)
499 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false)
500 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false)
501 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false)
502 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false)
503 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false)
504 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false)
505 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false)
506 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false)
507 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false)
508 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false)
509 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false)
510 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false)
511 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false)
512 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false)
513 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false)
514 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false)
515 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false)
516 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false)
517 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false)
518 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false)
519 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false)
520 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false)
521 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false)
522 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false)
523 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false)
524 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false)
525 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false)
526 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false)
527 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false)
528 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
529 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
530 /* GPIO function */
531 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false)
532 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
533 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
534 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
535 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
536 #endif
537 };
538
539 const short da850_uart0_pins[] __initdata = {
540 DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD,
541 -1
542 };
543
544 const short da850_uart1_pins[] __initdata = {
545 DA850_UART1_RXD, DA850_UART1_TXD,
546 -1
547 };
548
549 const short da850_uart2_pins[] __initdata = {
550 DA850_UART2_RXD, DA850_UART2_TXD,
551 -1
552 };
553
554 const short da850_i2c0_pins[] __initdata = {
555 DA850_I2C0_SDA, DA850_I2C0_SCL,
556 -1
557 };
558
559 const short da850_i2c1_pins[] __initdata = {
560 DA850_I2C1_SCL, DA850_I2C1_SDA,
561 -1
562 };
563
564 const short da850_cpgmac_pins[] __initdata = {
565 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
566 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
567 DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
568 DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
569 DA850_MDIO_D,
570 -1
571 };
572
573 const short da850_rmii_pins[] __initdata = {
574 DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
575 DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
576 DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
577 DA850_MDIO_D,
578 -1
579 };
580
581 const short da850_mcasp_pins[] __initdata = {
582 DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
583 DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
584 DA850_AXR_11, DA850_AXR_12,
585 -1
586 };
587
588 const short da850_lcdcntl_pins[] __initdata = {
589 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
590 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
591 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
592 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
593 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
594 -1
595 };
596
597 const short da850_mmcsd0_pins[] __initdata = {
598 DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
599 DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
600 DA850_GPIO4_0, DA850_GPIO4_1,
601 -1
602 };
603
604 const short da850_nand_pins[] __initdata = {
605 DA850_EMA_D_7, DA850_EMA_D_6, DA850_EMA_D_5, DA850_EMA_D_4,
606 DA850_EMA_D_3, DA850_EMA_D_2, DA850_EMA_D_1, DA850_EMA_D_0,
607 DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4,
608 DA850_NEMA_WE, DA850_NEMA_OE,
609 -1
610 };
611
612 const short da850_nor_pins[] __initdata = {
613 DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
614 DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1,
615 DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5,
616 DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9,
617 DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13,
618 DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1,
619 DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5,
620 DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9,
621 DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13,
622 DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17,
623 DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21,
624 DA850_EMA_A_22, DA850_EMA_A_23,
625 -1
626 };
627
628 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
629 static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
630 [IRQ_DA8XX_COMMTX] = 7,
631 [IRQ_DA8XX_COMMRX] = 7,
632 [IRQ_DA8XX_NINT] = 7,
633 [IRQ_DA8XX_EVTOUT0] = 7,
634 [IRQ_DA8XX_EVTOUT1] = 7,
635 [IRQ_DA8XX_EVTOUT2] = 7,
636 [IRQ_DA8XX_EVTOUT3] = 7,
637 [IRQ_DA8XX_EVTOUT4] = 7,
638 [IRQ_DA8XX_EVTOUT5] = 7,
639 [IRQ_DA8XX_EVTOUT6] = 7,
640 [IRQ_DA8XX_EVTOUT6] = 7,
641 [IRQ_DA8XX_EVTOUT7] = 7,
642 [IRQ_DA8XX_CCINT0] = 7,
643 [IRQ_DA8XX_CCERRINT] = 7,
644 [IRQ_DA8XX_TCERRINT0] = 7,
645 [IRQ_DA8XX_AEMIFINT] = 7,
646 [IRQ_DA8XX_I2CINT0] = 7,
647 [IRQ_DA8XX_MMCSDINT0] = 7,
648 [IRQ_DA8XX_MMCSDINT1] = 7,
649 [IRQ_DA8XX_ALLINT0] = 7,
650 [IRQ_DA8XX_RTC] = 7,
651 [IRQ_DA8XX_SPINT0] = 7,
652 [IRQ_DA8XX_TINT12_0] = 7,
653 [IRQ_DA8XX_TINT34_0] = 7,
654 [IRQ_DA8XX_TINT12_1] = 7,
655 [IRQ_DA8XX_TINT34_1] = 7,
656 [IRQ_DA8XX_UARTINT0] = 7,
657 [IRQ_DA8XX_KEYMGRINT] = 7,
658 [IRQ_DA8XX_SECINT] = 7,
659 [IRQ_DA8XX_SECKEYERR] = 7,
660 [IRQ_DA850_MPUADDRERR0] = 7,
661 [IRQ_DA850_MPUPROTERR0] = 7,
662 [IRQ_DA850_IOPUADDRERR0] = 7,
663 [IRQ_DA850_IOPUPROTERR0] = 7,
664 [IRQ_DA850_IOPUADDRERR1] = 7,
665 [IRQ_DA850_IOPUPROTERR1] = 7,
666 [IRQ_DA850_IOPUADDRERR2] = 7,
667 [IRQ_DA850_IOPUPROTERR2] = 7,
668 [IRQ_DA850_BOOTCFG_ADDR_ERR] = 7,
669 [IRQ_DA850_BOOTCFG_PROT_ERR] = 7,
670 [IRQ_DA850_MPUADDRERR1] = 7,
671 [IRQ_DA850_MPUPROTERR1] = 7,
672 [IRQ_DA850_IOPUADDRERR3] = 7,
673 [IRQ_DA850_IOPUPROTERR3] = 7,
674 [IRQ_DA850_IOPUADDRERR4] = 7,
675 [IRQ_DA850_IOPUPROTERR4] = 7,
676 [IRQ_DA850_IOPUADDRERR5] = 7,
677 [IRQ_DA850_IOPUPROTERR5] = 7,
678 [IRQ_DA850_MIOPU_BOOTCFG_ERR] = 7,
679 [IRQ_DA8XX_CHIPINT0] = 7,
680 [IRQ_DA8XX_CHIPINT1] = 7,
681 [IRQ_DA8XX_CHIPINT2] = 7,
682 [IRQ_DA8XX_CHIPINT3] = 7,
683 [IRQ_DA8XX_TCERRINT1] = 7,
684 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
685 [IRQ_DA8XX_C0_RX_PULSE] = 7,
686 [IRQ_DA8XX_C0_TX_PULSE] = 7,
687 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
688 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
689 [IRQ_DA8XX_C1_RX_PULSE] = 7,
690 [IRQ_DA8XX_C1_TX_PULSE] = 7,
691 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
692 [IRQ_DA8XX_MEMERR] = 7,
693 [IRQ_DA8XX_GPIO0] = 7,
694 [IRQ_DA8XX_GPIO1] = 7,
695 [IRQ_DA8XX_GPIO2] = 7,
696 [IRQ_DA8XX_GPIO3] = 7,
697 [IRQ_DA8XX_GPIO4] = 7,
698 [IRQ_DA8XX_GPIO5] = 7,
699 [IRQ_DA8XX_GPIO6] = 7,
700 [IRQ_DA8XX_GPIO7] = 7,
701 [IRQ_DA8XX_GPIO8] = 7,
702 [IRQ_DA8XX_I2CINT1] = 7,
703 [IRQ_DA8XX_LCDINT] = 7,
704 [IRQ_DA8XX_UARTINT1] = 7,
705 [IRQ_DA8XX_MCASPINT] = 7,
706 [IRQ_DA8XX_ALLINT1] = 7,
707 [IRQ_DA8XX_SPINT1] = 7,
708 [IRQ_DA8XX_UHPI_INT1] = 7,
709 [IRQ_DA8XX_USB_INT] = 7,
710 [IRQ_DA8XX_IRQN] = 7,
711 [IRQ_DA8XX_RWAKEUP] = 7,
712 [IRQ_DA8XX_UARTINT2] = 7,
713 [IRQ_DA8XX_DFTSSINT] = 7,
714 [IRQ_DA8XX_EHRPWM0] = 7,
715 [IRQ_DA8XX_EHRPWM0TZ] = 7,
716 [IRQ_DA8XX_EHRPWM1] = 7,
717 [IRQ_DA8XX_EHRPWM1TZ] = 7,
718 [IRQ_DA850_SATAINT] = 7,
719 [IRQ_DA850_TINT12_2] = 7,
720 [IRQ_DA850_TINT34_2] = 7,
721 [IRQ_DA850_TINTALL_2] = 7,
722 [IRQ_DA8XX_ECAP0] = 7,
723 [IRQ_DA8XX_ECAP1] = 7,
724 [IRQ_DA8XX_ECAP2] = 7,
725 [IRQ_DA850_MMCSDINT0_1] = 7,
726 [IRQ_DA850_MMCSDINT1_1] = 7,
727 [IRQ_DA850_T12CMPINT0_2] = 7,
728 [IRQ_DA850_T12CMPINT1_2] = 7,
729 [IRQ_DA850_T12CMPINT2_2] = 7,
730 [IRQ_DA850_T12CMPINT3_2] = 7,
731 [IRQ_DA850_T12CMPINT4_2] = 7,
732 [IRQ_DA850_T12CMPINT5_2] = 7,
733 [IRQ_DA850_T12CMPINT6_2] = 7,
734 [IRQ_DA850_T12CMPINT7_2] = 7,
735 [IRQ_DA850_T12CMPINT0_3] = 7,
736 [IRQ_DA850_T12CMPINT1_3] = 7,
737 [IRQ_DA850_T12CMPINT2_3] = 7,
738 [IRQ_DA850_T12CMPINT3_3] = 7,
739 [IRQ_DA850_T12CMPINT4_3] = 7,
740 [IRQ_DA850_T12CMPINT5_3] = 7,
741 [IRQ_DA850_T12CMPINT6_3] = 7,
742 [IRQ_DA850_T12CMPINT7_3] = 7,
743 [IRQ_DA850_RPIINT] = 7,
744 [IRQ_DA850_VPIFINT] = 7,
745 [IRQ_DA850_CCINT1] = 7,
746 [IRQ_DA850_CCERRINT1] = 7,
747 [IRQ_DA850_TCERRINT2] = 7,
748 [IRQ_DA850_TINT12_3] = 7,
749 [IRQ_DA850_TINT34_3] = 7,
750 [IRQ_DA850_TINTALL_3] = 7,
751 [IRQ_DA850_MCBSP0RINT] = 7,
752 [IRQ_DA850_MCBSP0XINT] = 7,
753 [IRQ_DA850_MCBSP1RINT] = 7,
754 [IRQ_DA850_MCBSP1XINT] = 7,
755 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
756 };
757
758 static struct map_desc da850_io_desc[] = {
759 {
760 .virtual = IO_VIRT,
761 .pfn = __phys_to_pfn(IO_PHYS),
762 .length = IO_SIZE,
763 .type = MT_DEVICE
764 },
765 {
766 .virtual = DA8XX_CP_INTC_VIRT,
767 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
768 .length = DA8XX_CP_INTC_SIZE,
769 .type = MT_DEVICE
770 },
771 };
772
773 static void __iomem *da850_psc_bases[] = {
774 IO_ADDRESS(DA8XX_PSC0_BASE),
775 IO_ADDRESS(DA8XX_PSC1_BASE),
776 };
777
778 /* Contents of JTAG ID register used to identify exact cpu type */
779 static struct davinci_id da850_ids[] = {
780 {
781 .variant = 0x0,
782 .part_no = 0xb7d1,
783 .manufacturer = 0x017, /* 0x02f >> 1 */
784 .cpu_id = DAVINCI_CPU_ID_DA850,
785 .name = "da850/omap-l138",
786 },
787 };
788
789 static struct davinci_timer_instance da850_timer_instance[4] = {
790 {
791 .base = IO_ADDRESS(DA8XX_TIMER64P0_BASE),
792 .bottom_irq = IRQ_DA8XX_TINT12_0,
793 .top_irq = IRQ_DA8XX_TINT34_0,
794 },
795 {
796 .base = IO_ADDRESS(DA8XX_TIMER64P1_BASE),
797 .bottom_irq = IRQ_DA8XX_TINT12_1,
798 .top_irq = IRQ_DA8XX_TINT34_1,
799 },
800 {
801 .base = IO_ADDRESS(DA850_TIMER64P2_BASE),
802 .bottom_irq = IRQ_DA850_TINT12_2,
803 .top_irq = IRQ_DA850_TINT34_2,
804 },
805 {
806 .base = IO_ADDRESS(DA850_TIMER64P3_BASE),
807 .bottom_irq = IRQ_DA850_TINT12_3,
808 .top_irq = IRQ_DA850_TINT34_3,
809 },
810 };
811
812 /*
813 * T0_BOT: Timer 0, bottom : Used for clock_event
814 * T0_TOP: Timer 0, top : Used for clocksource
815 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
816 */
817 static struct davinci_timer_info da850_timer_info = {
818 .timers = da850_timer_instance,
819 .clockevent_id = T0_BOT,
820 .clocksource_id = T0_TOP,
821 };
822
823 static void da850_set_async3_src(int pllnum)
824 {
825 struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
826 struct davinci_clk *c;
827 unsigned int v;
828 int ret;
829
830 for (c = da850_clks; c->lk.clk; c++) {
831 clk = c->lk.clk;
832 if (clk->flags & DA850_CLK_ASYNC3) {
833 ret = clk_set_parent(clk, newparent);
834 WARN(ret, "DA850: unable to re-parent clock %s",
835 clk->name);
836 }
837 }
838
839 v = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG));
840 if (pllnum)
841 v |= CFGCHIP3_ASYNC3_CLKSRC;
842 else
843 v &= ~CFGCHIP3_ASYNC3_CLKSRC;
844 __raw_writel(v, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG));
845 }
846
847 #ifdef CONFIG_CPU_FREQ
848 /*
849 * Notes:
850 * According to the TRM, minimum PLLM results in maximum power savings.
851 * The OPP definitions below should keep the PLLM as low as possible.
852 *
853 * The output of the PLLM must be between 400 to 600 MHz.
854 * This rules out prediv of anything but divide-by-one for 24Mhz OSC input.
855 */
856 struct da850_opp {
857 unsigned int freq; /* in KHz */
858 unsigned int prediv;
859 unsigned int mult;
860 unsigned int postdiv;
861 unsigned int cvdd_min; /* in uV */
862 unsigned int cvdd_max; /* in uV */
863 };
864
865 static const struct da850_opp da850_opp_300 = {
866 .freq = 300000,
867 .prediv = 1,
868 .mult = 25,
869 .postdiv = 2,
870 .cvdd_min = 1140000,
871 .cvdd_max = 1320000,
872 };
873
874 static const struct da850_opp da850_opp_200 = {
875 .freq = 200000,
876 .prediv = 1,
877 .mult = 25,
878 .postdiv = 3,
879 .cvdd_min = 1050000,
880 .cvdd_max = 1160000,
881 };
882
883 static const struct da850_opp da850_opp_96 = {
884 .freq = 96000,
885 .prediv = 1,
886 .mult = 20,
887 .postdiv = 5,
888 .cvdd_min = 950000,
889 .cvdd_max = 1050000,
890 };
891
892 #define OPP(freq) \
893 { \
894 .index = (unsigned int) &da850_opp_##freq, \
895 .frequency = freq * 1000, \
896 }
897
898 static struct cpufreq_frequency_table da850_freq_table[] = {
899 OPP(300),
900 OPP(200),
901 OPP(96),
902 {
903 .index = 0,
904 .frequency = CPUFREQ_TABLE_END,
905 },
906 };
907
908 static struct davinci_cpufreq_config cpufreq_info = {
909 .freq_table = &da850_freq_table[0],
910 };
911
912 static struct platform_device da850_cpufreq_device = {
913 .name = "cpufreq-davinci",
914 .dev = {
915 .platform_data = &cpufreq_info,
916 },
917 };
918
919 int __init da850_register_cpufreq(void)
920 {
921 return platform_device_register(&da850_cpufreq_device);
922 }
923
924 static int da850_round_armrate(struct clk *clk, unsigned long rate)
925 {
926 int i, ret = 0, diff;
927 unsigned int best = (unsigned int) -1;
928
929 rate /= 1000; /* convert to kHz */
930
931 for (i = 0; da850_freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
932 diff = da850_freq_table[i].frequency - rate;
933 if (diff < 0)
934 diff = -diff;
935
936 if (diff < best) {
937 best = diff;
938 ret = da850_freq_table[i].frequency;
939 }
940 }
941
942 return ret * 1000;
943 }
944
945 static int da850_set_armrate(struct clk *clk, unsigned long index)
946 {
947 struct clk *pllclk = &pll0_clk;
948
949 return clk_set_rate(pllclk, index);
950 }
951
952 static int da850_set_pll0rate(struct clk *clk, unsigned long index)
953 {
954 unsigned int prediv, mult, postdiv;
955 struct da850_opp *opp;
956 struct pll_data *pll = clk->pll_data;
957 unsigned int v;
958 int ret;
959
960 opp = (struct da850_opp *) da850_freq_table[index].index;
961 prediv = opp->prediv;
962 mult = opp->mult;
963 postdiv = opp->postdiv;
964
965 /* Unlock writing to PLL registers */
966 v = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP0_REG));
967 v &= ~CFGCHIP0_PLL_MASTER_LOCK;
968 __raw_writel(v, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP0_REG));
969
970 ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
971 if (WARN_ON(ret))
972 return ret;
973
974 return 0;
975 }
976 #else
977 int __init da850_register_cpufreq(void)
978 {
979 return 0;
980 }
981
982 static int da850_set_armrate(struct clk *clk, unsigned long rate)
983 {
984 return -EINVAL;
985 }
986
987 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate)
988 {
989 return -EINVAL;
990 }
991
992 static int da850_round_armrate(struct clk *clk, unsigned long rate)
993 {
994 return clk->rate;
995 }
996 #endif
997
998 #ifdef CONFIG_REGULATOR
999 static struct regulator *cvdd;
1000
1001 static int da850_set_voltage(unsigned int index)
1002 {
1003 struct da850_opp *opp;
1004
1005 if (!cvdd)
1006 return -ENODEV;
1007
1008 opp = (struct da850_opp *) da850_freq_table[index].index;
1009
1010 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
1011 }
1012
1013 static int __init da850_regulator_init(void)
1014 {
1015 int ret = 0;
1016
1017 cvdd = regulator_get(NULL, "cvdd");
1018 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
1019 " voltage scaling unsupported\n")) {
1020 ret = PTR_ERR(cvdd);
1021 goto out;
1022 }
1023
1024 cpufreq_info.set_voltage = da850_set_voltage;
1025
1026 out:
1027 return ret;
1028 }
1029 device_initcall(da850_regulator_init);
1030 #endif
1031
1032 static struct davinci_soc_info davinci_soc_info_da850 = {
1033 .io_desc = da850_io_desc,
1034 .io_desc_num = ARRAY_SIZE(da850_io_desc),
1035 .ids = da850_ids,
1036 .ids_num = ARRAY_SIZE(da850_ids),
1037 .cpu_clks = da850_clks,
1038 .psc_bases = da850_psc_bases,
1039 .psc_bases_num = ARRAY_SIZE(da850_psc_bases),
1040 .pinmux_pins = da850_pins,
1041 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
1042 .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT,
1043 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
1044 .intc_irq_prios = da850_default_priorities,
1045 .intc_irq_num = DA850_N_CP_INTC_IRQ,
1046 .timer_info = &da850_timer_info,
1047 .gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE),
1048 .gpio_num = 144,
1049 .gpio_irq = IRQ_DA8XX_GPIO0,
1050 .serial_dev = &da8xx_serial_device,
1051 .emac_pdata = &da8xx_emac_pdata,
1052 };
1053
1054 void __init da850_init(void)
1055 {
1056 da8xx_syscfg_base = ioremap(DA8XX_SYSCFG_BASE, SZ_4K);
1057 if (WARN(!da8xx_syscfg_base, "Unable to map syscfg module"))
1058 return;
1059
1060 davinci_soc_info_da850.jtag_id_base =
1061 DA8XX_SYSCFG_VIRT(DA8XX_JTAG_ID_REG);
1062 davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG_VIRT(0x120);
1063
1064 davinci_common_init(&davinci_soc_info_da850);
1065
1066 /*
1067 * Move the clock source of Async3 domain to PLL1 SYSCLK2.
1068 * This helps keeping the peripherals on this domain insulated
1069 * from CPU frequency changes caused by DVFS. The firmware sets
1070 * both PLL0 and PLL1 to the same frequency so, there should not
1071 * be any noticible change even in non-DVFS use cases.
1072 */
1073 da850_set_async3_src(1);
1074 }
mm of the moment repository