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"[PATCH] Fix leaks on /proc/{*/sched,sched_debug,timer_list,timer_stats}" and
[mmotm.git] / arch / avr32 / mach-at32ap / at32ap700x.c
blob4bf44dc62af8726a729e2611784492ba8e47d559
1 /*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/dw_dmac.h>
11 #include <linux/fb.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/gpio.h>
16 #include <linux/spi/spi.h>
17 #include <linux/usb/atmel_usba_udc.h>
18 #include <linux/atmel-mci.h>
19
20 #include <asm/io.h>
21 #include <asm/irq.h>
22
23 #include <mach/at32ap700x.h>
24 #include <mach/board.h>
25 #include <mach/hmatrix.h>
26 #include <mach/portmux.h>
27 #include <mach/sram.h>
28
29 #include <sound/atmel-abdac.h>
30 #include <sound/atmel-ac97c.h>
31
32 #include <video/atmel_lcdc.h>
33
34 #include "clock.h"
35 #include "pio.h"
36 #include "pm.h"
37
38
39 #define PBMEM(base) \
40 { \
41 .start = base, \
42 .end = base + 0x3ff, \
43 .flags = IORESOURCE_MEM, \
44 }
45 #define IRQ(num) \
46 { \
47 .start = num, \
48 .end = num, \
49 .flags = IORESOURCE_IRQ, \
50 }
51 #define NAMED_IRQ(num, _name) \
52 { \
53 .start = num, \
54 .end = num, \
55 .name = _name, \
56 .flags = IORESOURCE_IRQ, \
57 }
58
59 /* REVISIT these assume *every* device supports DMA, but several
60 * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
61 */
62 #define DEFINE_DEV(_name, _id) \
63 static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32); \
64 static struct platform_device _name##_id##_device = { \
65 .name = #_name, \
66 .id = _id, \
67 .dev = { \
68 .dma_mask = &_name##_id##_dma_mask, \
69 .coherent_dma_mask = DMA_BIT_MASK(32), \
70 }, \
71 .resource = _name##_id##_resource, \
72 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
73 }
74 #define DEFINE_DEV_DATA(_name, _id) \
75 static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32); \
76 static struct platform_device _name##_id##_device = { \
77 .name = #_name, \
78 .id = _id, \
79 .dev = { \
80 .dma_mask = &_name##_id##_dma_mask, \
81 .platform_data = &_name##_id##_data, \
82 .coherent_dma_mask = DMA_BIT_MASK(32), \
83 }, \
84 .resource = _name##_id##_resource, \
85 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
86 }
87
88 #define select_peripheral(port, pin_mask, periph, flags) \
89 at32_select_periph(GPIO_##port##_BASE, pin_mask, \
90 GPIO_##periph, flags)
91
92 #define DEV_CLK(_name, devname, bus, _index) \
93 static struct clk devname##_##_name = { \
94 .name = #_name, \
95 .dev = &devname##_device.dev, \
96 .parent = &bus##_clk, \
97 .mode = bus##_clk_mode, \
98 .get_rate = bus##_clk_get_rate, \
99 .index = _index, \
100 }
101
102 static DEFINE_SPINLOCK(pm_lock);
103
104 static struct clk osc0;
105 static struct clk osc1;
106
107 static unsigned long osc_get_rate(struct clk *clk)
108 {
109 return at32_board_osc_rates[clk->index];
110 }
111
112 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
113 {
114 unsigned long div, mul, rate;
115
116 div = PM_BFEXT(PLLDIV, control) + 1;
117 mul = PM_BFEXT(PLLMUL, control) + 1;
118
119 rate = clk->parent->get_rate(clk->parent);
120 rate = (rate + div / 2) / div;
121 rate *= mul;
122
123 return rate;
124 }
125
126 static long pll_set_rate(struct clk *clk, unsigned long rate,
127 u32 *pll_ctrl)
128 {
129 unsigned long mul;
130 unsigned long mul_best_fit = 0;
131 unsigned long div;
132 unsigned long div_min;
133 unsigned long div_max;
134 unsigned long div_best_fit = 0;
135 unsigned long base;
136 unsigned long pll_in;
137 unsigned long actual = 0;
138 unsigned long rate_error;
139 unsigned long rate_error_prev = ~0UL;
140 u32 ctrl;
141
142 /* Rate must be between 80 MHz and 200 Mhz. */
143 if (rate < 80000000UL || rate > 200000000UL)
144 return -EINVAL;
145
146 ctrl = PM_BF(PLLOPT, 4);
147 base = clk->parent->get_rate(clk->parent);
148
149 /* PLL input frequency must be between 6 MHz and 32 MHz. */
150 div_min = DIV_ROUND_UP(base, 32000000UL);
151 div_max = base / 6000000UL;
152
153 if (div_max < div_min)
154 return -EINVAL;
155
156 for (div = div_min; div <= div_max; div++) {
157 pll_in = (base + div / 2) / div;
158 mul = (rate + pll_in / 2) / pll_in;
159
160 if (mul == 0)
161 continue;
162
163 actual = pll_in * mul;
164 rate_error = abs(actual - rate);
165
166 if (rate_error < rate_error_prev) {
167 mul_best_fit = mul;
168 div_best_fit = div;
169 rate_error_prev = rate_error;
170 }
171
172 if (rate_error == 0)
173 break;
174 }
175
176 if (div_best_fit == 0)
177 return -EINVAL;
178
179 ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
180 ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
181 ctrl |= PM_BF(PLLCOUNT, 16);
182
183 if (clk->parent == &osc1)
184 ctrl |= PM_BIT(PLLOSC);
185
186 *pll_ctrl = ctrl;
187
188 return actual;
189 }
190
191 static unsigned long pll0_get_rate(struct clk *clk)
192 {
193 u32 control;
194
195 control = pm_readl(PLL0);
196
197 return pll_get_rate(clk, control);
198 }
199
200 static void pll1_mode(struct clk *clk, int enabled)
201 {
202 unsigned long timeout;
203 u32 status;
204 u32 ctrl;
205
206 ctrl = pm_readl(PLL1);
207
208 if (enabled) {
209 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
210 pr_debug("clk %s: failed to enable, rate not set\n",
211 clk->name);
212 return;
213 }
214
215 ctrl |= PM_BIT(PLLEN);
216 pm_writel(PLL1, ctrl);
217
218 /* Wait for PLL lock. */
219 for (timeout = 10000; timeout; timeout--) {
220 status = pm_readl(ISR);
221 if (status & PM_BIT(LOCK1))
222 break;
223 udelay(10);
224 }
225
226 if (!(status & PM_BIT(LOCK1)))
227 printk(KERN_ERR "clk %s: timeout waiting for lock\n",
228 clk->name);
229 } else {
230 ctrl &= ~PM_BIT(PLLEN);
231 pm_writel(PLL1, ctrl);
232 }
233 }
234
235 static unsigned long pll1_get_rate(struct clk *clk)
236 {
237 u32 control;
238
239 control = pm_readl(PLL1);
240
241 return pll_get_rate(clk, control);
242 }
243
244 static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
245 {
246 u32 ctrl = 0;
247 unsigned long actual_rate;
248
249 actual_rate = pll_set_rate(clk, rate, &ctrl);
250
251 if (apply) {
252 if (actual_rate != rate)
253 return -EINVAL;
254 if (clk->users > 0)
255 return -EBUSY;
256 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
257 clk->name, rate, actual_rate);
258 pm_writel(PLL1, ctrl);
259 }
260
261 return actual_rate;
262 }
263
264 static int pll1_set_parent(struct clk *clk, struct clk *parent)
265 {
266 u32 ctrl;
267
268 if (clk->users > 0)
269 return -EBUSY;
270
271 ctrl = pm_readl(PLL1);
272 WARN_ON(ctrl & PM_BIT(PLLEN));
273
274 if (parent == &osc0)
275 ctrl &= ~PM_BIT(PLLOSC);
276 else if (parent == &osc1)
277 ctrl |= PM_BIT(PLLOSC);
278 else
279 return -EINVAL;
280
281 pm_writel(PLL1, ctrl);
282 clk->parent = parent;
283
284 return 0;
285 }
286
287 /*
288 * The AT32AP7000 has five primary clock sources: One 32kHz
289 * oscillator, two crystal oscillators and two PLLs.
290 */
291 static struct clk osc32k = {
292 .name = "osc32k",
293 .get_rate = osc_get_rate,
294 .users = 1,
295 .index = 0,
296 };
297 static struct clk osc0 = {
298 .name = "osc0",
299 .get_rate = osc_get_rate,
300 .users = 1,
301 .index = 1,
302 };
303 static struct clk osc1 = {
304 .name = "osc1",
305 .get_rate = osc_get_rate,
306 .index = 2,
307 };
308 static struct clk pll0 = {
309 .name = "pll0",
310 .get_rate = pll0_get_rate,
311 .parent = &osc0,
312 };
313 static struct clk pll1 = {
314 .name = "pll1",
315 .mode = pll1_mode,
316 .get_rate = pll1_get_rate,
317 .set_rate = pll1_set_rate,
318 .set_parent = pll1_set_parent,
319 .parent = &osc0,
320 };
321
322 /*
323 * The main clock can be either osc0 or pll0. The boot loader may
324 * have chosen one for us, so we don't really know which one until we
325 * have a look at the SM.
326 */
327 static struct clk *main_clock;
328
329 /*
330 * Synchronous clocks are generated from the main clock. The clocks
331 * must satisfy the constraint
332 * fCPU >= fHSB >= fPB
333 * i.e. each clock must not be faster than its parent.
334 */
335 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
336 {
337 return main_clock->get_rate(main_clock) >> shift;
338 };
339
340 static void cpu_clk_mode(struct clk *clk, int enabled)
341 {
342 unsigned long flags;
343 u32 mask;
344
345 spin_lock_irqsave(&pm_lock, flags);
346 mask = pm_readl(CPU_MASK);
347 if (enabled)
348 mask |= 1 << clk->index;
349 else
350 mask &= ~(1 << clk->index);
351 pm_writel(CPU_MASK, mask);
352 spin_unlock_irqrestore(&pm_lock, flags);
353 }
354
355 static unsigned long cpu_clk_get_rate(struct clk *clk)
356 {
357 unsigned long cksel, shift = 0;
358
359 cksel = pm_readl(CKSEL);
360 if (cksel & PM_BIT(CPUDIV))
361 shift = PM_BFEXT(CPUSEL, cksel) + 1;
362
363 return bus_clk_get_rate(clk, shift);
364 }
365
366 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
367 {
368 u32 control;
369 unsigned long parent_rate, child_div, actual_rate, div;
370
371 parent_rate = clk->parent->get_rate(clk->parent);
372 control = pm_readl(CKSEL);
373
374 if (control & PM_BIT(HSBDIV))
375 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
376 else
377 child_div = 1;
378
379 if (rate > 3 * (parent_rate / 4) || child_div == 1) {
380 actual_rate = parent_rate;
381 control &= ~PM_BIT(CPUDIV);
382 } else {
383 unsigned int cpusel;
384 div = (parent_rate + rate / 2) / rate;
385 if (div > child_div)
386 div = child_div;
387 cpusel = (div > 1) ? (fls(div) - 2) : 0;
388 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
389 actual_rate = parent_rate / (1 << (cpusel + 1));
390 }
391
392 pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
393 clk->name, rate, actual_rate);
394
395 if (apply)
396 pm_writel(CKSEL, control);
397
398 return actual_rate;
399 }
400
401 static void hsb_clk_mode(struct clk *clk, int enabled)
402 {
403 unsigned long flags;
404 u32 mask;
405
406 spin_lock_irqsave(&pm_lock, flags);
407 mask = pm_readl(HSB_MASK);
408 if (enabled)
409 mask |= 1 << clk->index;
410 else
411 mask &= ~(1 << clk->index);
412 pm_writel(HSB_MASK, mask);
413 spin_unlock_irqrestore(&pm_lock, flags);
414 }
415
416 static unsigned long hsb_clk_get_rate(struct clk *clk)
417 {
418 unsigned long cksel, shift = 0;
419
420 cksel = pm_readl(CKSEL);
421 if (cksel & PM_BIT(HSBDIV))
422 shift = PM_BFEXT(HSBSEL, cksel) + 1;
423
424 return bus_clk_get_rate(clk, shift);
425 }
426
427 void pba_clk_mode(struct clk *clk, int enabled)
428 {
429 unsigned long flags;
430 u32 mask;
431
432 spin_lock_irqsave(&pm_lock, flags);
433 mask = pm_readl(PBA_MASK);
434 if (enabled)
435 mask |= 1 << clk->index;
436 else
437 mask &= ~(1 << clk->index);
438 pm_writel(PBA_MASK, mask);
439 spin_unlock_irqrestore(&pm_lock, flags);
440 }
441
442 unsigned long pba_clk_get_rate(struct clk *clk)
443 {
444 unsigned long cksel, shift = 0;
445
446 cksel = pm_readl(CKSEL);
447 if (cksel & PM_BIT(PBADIV))
448 shift = PM_BFEXT(PBASEL, cksel) + 1;
449
450 return bus_clk_get_rate(clk, shift);
451 }
452
453 static void pbb_clk_mode(struct clk *clk, int enabled)
454 {
455 unsigned long flags;
456 u32 mask;
457
458 spin_lock_irqsave(&pm_lock, flags);
459 mask = pm_readl(PBB_MASK);
460 if (enabled)
461 mask |= 1 << clk->index;
462 else
463 mask &= ~(1 << clk->index);
464 pm_writel(PBB_MASK, mask);
465 spin_unlock_irqrestore(&pm_lock, flags);
466 }
467
468 static unsigned long pbb_clk_get_rate(struct clk *clk)
469 {
470 unsigned long cksel, shift = 0;
471
472 cksel = pm_readl(CKSEL);
473 if (cksel & PM_BIT(PBBDIV))
474 shift = PM_BFEXT(PBBSEL, cksel) + 1;
475
476 return bus_clk_get_rate(clk, shift);
477 }
478
479 static struct clk cpu_clk = {
480 .name = "cpu",
481 .get_rate = cpu_clk_get_rate,
482 .set_rate = cpu_clk_set_rate,
483 .users = 1,
484 };
485 static struct clk hsb_clk = {
486 .name = "hsb",
487 .parent = &cpu_clk,
488 .get_rate = hsb_clk_get_rate,
489 };
490 static struct clk pba_clk = {
491 .name = "pba",
492 .parent = &hsb_clk,
493 .mode = hsb_clk_mode,
494 .get_rate = pba_clk_get_rate,
495 .index = 1,
496 };
497 static struct clk pbb_clk = {
498 .name = "pbb",
499 .parent = &hsb_clk,
500 .mode = hsb_clk_mode,
501 .get_rate = pbb_clk_get_rate,
502 .users = 1,
503 .index = 2,
504 };
505
506 /* --------------------------------------------------------------------
507 * Generic Clock operations
508 * -------------------------------------------------------------------- */
509
510 static void genclk_mode(struct clk *clk, int enabled)
511 {
512 u32 control;
513
514 control = pm_readl(GCCTRL(clk->index));
515 if (enabled)
516 control |= PM_BIT(CEN);
517 else
518 control &= ~PM_BIT(CEN);
519 pm_writel(GCCTRL(clk->index), control);
520 }
521
522 static unsigned long genclk_get_rate(struct clk *clk)
523 {
524 u32 control;
525 unsigned long div = 1;
526
527 control = pm_readl(GCCTRL(clk->index));
528 if (control & PM_BIT(DIVEN))
529 div = 2 * (PM_BFEXT(DIV, control) + 1);
530
531 return clk->parent->get_rate(clk->parent) / div;
532 }
533
534 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
535 {
536 u32 control;
537 unsigned long parent_rate, actual_rate, div;
538
539 parent_rate = clk->parent->get_rate(clk->parent);
540 control = pm_readl(GCCTRL(clk->index));
541
542 if (rate > 3 * parent_rate / 4) {
543 actual_rate = parent_rate;
544 control &= ~PM_BIT(DIVEN);
545 } else {
546 div = (parent_rate + rate) / (2 * rate) - 1;
547 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
548 actual_rate = parent_rate / (2 * (div + 1));
549 }
550
551 dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
552 clk->name, rate, actual_rate);
553
554 if (apply)
555 pm_writel(GCCTRL(clk->index), control);
556
557 return actual_rate;
558 }
559
560 int genclk_set_parent(struct clk *clk, struct clk *parent)
561 {
562 u32 control;
563
564 dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
565 clk->name, parent->name, clk->parent->name);
566
567 control = pm_readl(GCCTRL(clk->index));
568
569 if (parent == &osc1 || parent == &pll1)
570 control |= PM_BIT(OSCSEL);
571 else if (parent == &osc0 || parent == &pll0)
572 control &= ~PM_BIT(OSCSEL);
573 else
574 return -EINVAL;
575
576 if (parent == &pll0 || parent == &pll1)
577 control |= PM_BIT(PLLSEL);
578 else
579 control &= ~PM_BIT(PLLSEL);
580
581 pm_writel(GCCTRL(clk->index), control);
582 clk->parent = parent;
583
584 return 0;
585 }
586
587 static void __init genclk_init_parent(struct clk *clk)
588 {
589 u32 control;
590 struct clk *parent;
591
592 BUG_ON(clk->index > 7);
593
594 control = pm_readl(GCCTRL(clk->index));
595 if (control & PM_BIT(OSCSEL))
596 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
597 else
598 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
599
600 clk->parent = parent;
601 }
602
603 static struct dw_dma_platform_data dw_dmac0_data = {
604 .nr_channels = 3,
605 };
606
607 static struct resource dw_dmac0_resource[] = {
608 PBMEM(0xff200000),
609 IRQ(2),
610 };
611 DEFINE_DEV_DATA(dw_dmac, 0);
612 DEV_CLK(hclk, dw_dmac0, hsb, 10);
613
614 /* --------------------------------------------------------------------
615 * System peripherals
616 * -------------------------------------------------------------------- */
617 static struct resource at32_pm0_resource[] = {
618 {
619 .start = 0xfff00000,
620 .end = 0xfff0007f,
621 .flags = IORESOURCE_MEM,
622 },
623 IRQ(20),
624 };
625
626 static struct resource at32ap700x_rtc0_resource[] = {
627 {
628 .start = 0xfff00080,
629 .end = 0xfff000af,
630 .flags = IORESOURCE_MEM,
631 },
632 IRQ(21),
633 };
634
635 static struct resource at32_wdt0_resource[] = {
636 {
637 .start = 0xfff000b0,
638 .end = 0xfff000cf,
639 .flags = IORESOURCE_MEM,
640 },
641 };
642
643 static struct resource at32_eic0_resource[] = {
644 {
645 .start = 0xfff00100,
646 .end = 0xfff0013f,
647 .flags = IORESOURCE_MEM,
648 },
649 IRQ(19),
650 };
651
652 DEFINE_DEV(at32_pm, 0);
653 DEFINE_DEV(at32ap700x_rtc, 0);
654 DEFINE_DEV(at32_wdt, 0);
655 DEFINE_DEV(at32_eic, 0);
656
657 /*
658 * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
659 * is always running.
660 */
661 static struct clk at32_pm_pclk = {
662 .name = "pclk",
663 .dev = &at32_pm0_device.dev,
664 .parent = &pbb_clk,
665 .mode = pbb_clk_mode,
666 .get_rate = pbb_clk_get_rate,
667 .users = 1,
668 .index = 0,
669 };
670
671 static struct resource intc0_resource[] = {
672 PBMEM(0xfff00400),
673 };
674 struct platform_device at32_intc0_device = {
675 .name = "intc",
676 .id = 0,
677 .resource = intc0_resource,
678 .num_resources = ARRAY_SIZE(intc0_resource),
679 };
680 DEV_CLK(pclk, at32_intc0, pbb, 1);
681
682 static struct clk ebi_clk = {
683 .name = "ebi",
684 .parent = &hsb_clk,
685 .mode = hsb_clk_mode,
686 .get_rate = hsb_clk_get_rate,
687 .users = 1,
688 };
689 static struct clk hramc_clk = {
690 .name = "hramc",
691 .parent = &hsb_clk,
692 .mode = hsb_clk_mode,
693 .get_rate = hsb_clk_get_rate,
694 .users = 1,
695 .index = 3,
696 };
697 static struct clk sdramc_clk = {
698 .name = "sdramc_clk",
699 .parent = &pbb_clk,
700 .mode = pbb_clk_mode,
701 .get_rate = pbb_clk_get_rate,
702 .users = 1,
703 .index = 14,
704 };
705
706 static struct resource smc0_resource[] = {
707 PBMEM(0xfff03400),
708 };
709 DEFINE_DEV(smc, 0);
710 DEV_CLK(pclk, smc0, pbb, 13);
711 DEV_CLK(mck, smc0, hsb, 0);
712
713 static struct platform_device pdc_device = {
714 .name = "pdc",
715 .id = 0,
716 };
717 DEV_CLK(hclk, pdc, hsb, 4);
718 DEV_CLK(pclk, pdc, pba, 16);
719
720 static struct clk pico_clk = {
721 .name = "pico",
722 .parent = &cpu_clk,
723 .mode = cpu_clk_mode,
724 .get_rate = cpu_clk_get_rate,
725 .users = 1,
726 };
727
728 /* --------------------------------------------------------------------
729 * HMATRIX
730 * -------------------------------------------------------------------- */
731
732 struct clk at32_hmatrix_clk = {
733 .name = "hmatrix_clk",
734 .parent = &pbb_clk,
735 .mode = pbb_clk_mode,
736 .get_rate = pbb_clk_get_rate,
737 .index = 2,
738 .users = 1,
739 };
740
741 /*
742 * Set bits in the HMATRIX Special Function Register (SFR) used by the
743 * External Bus Interface (EBI). This can be used to enable special
744 * features like CompactFlash support, NAND Flash support, etc. on
745 * certain chipselects.
746 */
747 static inline void set_ebi_sfr_bits(u32 mask)
748 {
749 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, mask);
750 }
751
752 /* --------------------------------------------------------------------
753 * Timer/Counter (TC)
754 * -------------------------------------------------------------------- */
755
756 static struct resource at32_tcb0_resource[] = {
757 PBMEM(0xfff00c00),
758 IRQ(22),
759 };
760 static struct platform_device at32_tcb0_device = {
761 .name = "atmel_tcb",
762 .id = 0,
763 .resource = at32_tcb0_resource,
764 .num_resources = ARRAY_SIZE(at32_tcb0_resource),
765 };
766 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
767
768 static struct resource at32_tcb1_resource[] = {
769 PBMEM(0xfff01000),
770 IRQ(23),
771 };
772 static struct platform_device at32_tcb1_device = {
773 .name = "atmel_tcb",
774 .id = 1,
775 .resource = at32_tcb1_resource,
776 .num_resources = ARRAY_SIZE(at32_tcb1_resource),
777 };
778 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
779
780 /* --------------------------------------------------------------------
781 * PIO
782 * -------------------------------------------------------------------- */
783
784 static struct resource pio0_resource[] = {
785 PBMEM(0xffe02800),
786 IRQ(13),
787 };
788 DEFINE_DEV(pio, 0);
789 DEV_CLK(mck, pio0, pba, 10);
790
791 static struct resource pio1_resource[] = {
792 PBMEM(0xffe02c00),
793 IRQ(14),
794 };
795 DEFINE_DEV(pio, 1);
796 DEV_CLK(mck, pio1, pba, 11);
797
798 static struct resource pio2_resource[] = {
799 PBMEM(0xffe03000),
800 IRQ(15),
801 };
802 DEFINE_DEV(pio, 2);
803 DEV_CLK(mck, pio2, pba, 12);
804
805 static struct resource pio3_resource[] = {
806 PBMEM(0xffe03400),
807 IRQ(16),
808 };
809 DEFINE_DEV(pio, 3);
810 DEV_CLK(mck, pio3, pba, 13);
811
812 static struct resource pio4_resource[] = {
813 PBMEM(0xffe03800),
814 IRQ(17),
815 };
816 DEFINE_DEV(pio, 4);
817 DEV_CLK(mck, pio4, pba, 14);
818
819 static int __init system_device_init(void)
820 {
821 platform_device_register(&at32_pm0_device);
822 platform_device_register(&at32_intc0_device);
823 platform_device_register(&at32ap700x_rtc0_device);
824 platform_device_register(&at32_wdt0_device);
825 platform_device_register(&at32_eic0_device);
826 platform_device_register(&smc0_device);
827 platform_device_register(&pdc_device);
828 platform_device_register(&dw_dmac0_device);
829
830 platform_device_register(&at32_tcb0_device);
831 platform_device_register(&at32_tcb1_device);
832
833 platform_device_register(&pio0_device);
834 platform_device_register(&pio1_device);
835 platform_device_register(&pio2_device);
836 platform_device_register(&pio3_device);
837 platform_device_register(&pio4_device);
838
839 return 0;
840 }
841 core_initcall(system_device_init);
842
843 /* --------------------------------------------------------------------
844 * PSIF
845 * -------------------------------------------------------------------- */
846 static struct resource atmel_psif0_resource[] __initdata = {
847 {
848 .start = 0xffe03c00,
849 .end = 0xffe03cff,
850 .flags = IORESOURCE_MEM,
851 },
852 IRQ(18),
853 };
854 static struct clk atmel_psif0_pclk = {
855 .name = "pclk",
856 .parent = &pba_clk,
857 .mode = pba_clk_mode,
858 .get_rate = pba_clk_get_rate,
859 .index = 15,
860 };
861
862 static struct resource atmel_psif1_resource[] __initdata = {
863 {
864 .start = 0xffe03d00,
865 .end = 0xffe03dff,
866 .flags = IORESOURCE_MEM,
867 },
868 IRQ(18),
869 };
870 static struct clk atmel_psif1_pclk = {
871 .name = "pclk",
872 .parent = &pba_clk,
873 .mode = pba_clk_mode,
874 .get_rate = pba_clk_get_rate,
875 .index = 15,
876 };
877
878 struct platform_device *__init at32_add_device_psif(unsigned int id)
879 {
880 struct platform_device *pdev;
881 u32 pin_mask;
882
883 if (!(id == 0 || id == 1))
884 return NULL;
885
886 pdev = platform_device_alloc("atmel_psif", id);
887 if (!pdev)
888 return NULL;
889
890 switch (id) {
891 case 0:
892 pin_mask = (1 << 8) | (1 << 9); /* CLOCK & DATA */
893
894 if (platform_device_add_resources(pdev, atmel_psif0_resource,
895 ARRAY_SIZE(atmel_psif0_resource)))
896 goto err_add_resources;
897 atmel_psif0_pclk.dev = &pdev->dev;
898 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
899 break;
900 case 1:
901 pin_mask = (1 << 11) | (1 << 12); /* CLOCK & DATA */
902
903 if (platform_device_add_resources(pdev, atmel_psif1_resource,
904 ARRAY_SIZE(atmel_psif1_resource)))
905 goto err_add_resources;
906 atmel_psif1_pclk.dev = &pdev->dev;
907 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
908 break;
909 default:
910 return NULL;
911 }
912
913 platform_device_add(pdev);
914 return pdev;
915
916 err_add_resources:
917 platform_device_put(pdev);
918 return NULL;
919 }
920
921 /* --------------------------------------------------------------------
922 * USART
923 * -------------------------------------------------------------------- */
924
925 static struct atmel_uart_data atmel_usart0_data = {
926 .use_dma_tx = 1,
927 .use_dma_rx = 1,
928 };
929 static struct resource atmel_usart0_resource[] = {
930 PBMEM(0xffe00c00),
931 IRQ(6),
932 };
933 DEFINE_DEV_DATA(atmel_usart, 0);
934 DEV_CLK(usart, atmel_usart0, pba, 3);
935
936 static struct atmel_uart_data atmel_usart1_data = {
937 .use_dma_tx = 1,
938 .use_dma_rx = 1,
939 };
940 static struct resource atmel_usart1_resource[] = {
941 PBMEM(0xffe01000),
942 IRQ(7),
943 };
944 DEFINE_DEV_DATA(atmel_usart, 1);
945 DEV_CLK(usart, atmel_usart1, pba, 4);
946
947 static struct atmel_uart_data atmel_usart2_data = {
948 .use_dma_tx = 1,
949 .use_dma_rx = 1,
950 };
951 static struct resource atmel_usart2_resource[] = {
952 PBMEM(0xffe01400),
953 IRQ(8),
954 };
955 DEFINE_DEV_DATA(atmel_usart, 2);
956 DEV_CLK(usart, atmel_usart2, pba, 5);
957
958 static struct atmel_uart_data atmel_usart3_data = {
959 .use_dma_tx = 1,
960 .use_dma_rx = 1,
961 };
962 static struct resource atmel_usart3_resource[] = {
963 PBMEM(0xffe01800),
964 IRQ(9),
965 };
966 DEFINE_DEV_DATA(atmel_usart, 3);
967 DEV_CLK(usart, atmel_usart3, pba, 6);
968
969 static inline void configure_usart0_pins(int flags)
970 {
971 u32 pin_mask = (1 << 8) | (1 << 9); /* RXD & TXD */
972 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 6);
973 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 7);
974 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 10);
975
976 select_peripheral(PIOA, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
977 }
978
979 static inline void configure_usart1_pins(int flags)
980 {
981 u32 pin_mask = (1 << 17) | (1 << 18); /* RXD & TXD */
982 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 19);
983 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 20);
984 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 16);
985
986 select_peripheral(PIOA, pin_mask, PERIPH_A, AT32_GPIOF_PULLUP);
987 }
988
989 static inline void configure_usart2_pins(int flags)
990 {
991 u32 pin_mask = (1 << 26) | (1 << 27); /* RXD & TXD */
992 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 30);
993 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 29);
994 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 28);
995
996 select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
997 }
998
999 static inline void configure_usart3_pins(int flags)
1000 {
1001 u32 pin_mask = (1 << 18) | (1 << 17); /* RXD & TXD */
1002 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 16);
1003 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 15);
1004 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 19);
1005
1006 select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
1007 }
1008
1009 static struct platform_device *__initdata at32_usarts[4];
1010
1011 void __init at32_map_usart(unsigned int hw_id, unsigned int line, int flags)
1012 {
1013 struct platform_device *pdev;
1014
1015 switch (hw_id) {
1016 case 0:
1017 pdev = &atmel_usart0_device;
1018 configure_usart0_pins(flags);
1019 break;
1020 case 1:
1021 pdev = &atmel_usart1_device;
1022 configure_usart1_pins(flags);
1023 break;
1024 case 2:
1025 pdev = &atmel_usart2_device;
1026 configure_usart2_pins(flags);
1027 break;
1028 case 3:
1029 pdev = &atmel_usart3_device;
1030 configure_usart3_pins(flags);
1031 break;
1032 default:
1033 return;
1034 }
1035
1036 if (PXSEG(pdev->resource[0].start) == P4SEG) {
1037 /* Addresses in the P4 segment are permanently mapped 1:1 */
1038 struct atmel_uart_data *data = pdev->dev.platform_data;
1039 data->regs = (void __iomem *)pdev->resource[0].start;
1040 }
1041
1042 pdev->id = line;
1043 at32_usarts[line] = pdev;
1044 }
1045
1046 struct platform_device *__init at32_add_device_usart(unsigned int id)
1047 {
1048 platform_device_register(at32_usarts[id]);
1049 return at32_usarts[id];
1050 }
1051
1052 struct platform_device *atmel_default_console_device;
1053
1054 void __init at32_setup_serial_console(unsigned int usart_id)
1055 {
1056 atmel_default_console_device = at32_usarts[usart_id];
1057 }
1058
1059 /* --------------------------------------------------------------------
1060 * Ethernet
1061 * -------------------------------------------------------------------- */
1062
1063 #ifdef CONFIG_CPU_AT32AP7000
1064 static struct eth_platform_data macb0_data;
1065 static struct resource macb0_resource[] = {
1066 PBMEM(0xfff01800),
1067 IRQ(25),
1068 };
1069 DEFINE_DEV_DATA(macb, 0);
1070 DEV_CLK(hclk, macb0, hsb, 8);
1071 DEV_CLK(pclk, macb0, pbb, 6);
1072
1073 static struct eth_platform_data macb1_data;
1074 static struct resource macb1_resource[] = {
1075 PBMEM(0xfff01c00),
1076 IRQ(26),
1077 };
1078 DEFINE_DEV_DATA(macb, 1);
1079 DEV_CLK(hclk, macb1, hsb, 9);
1080 DEV_CLK(pclk, macb1, pbb, 7);
1081
1082 struct platform_device *__init
1083 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
1084 {
1085 struct platform_device *pdev;
1086 u32 pin_mask;
1087
1088 switch (id) {
1089 case 0:
1090 pdev = &macb0_device;
1091
1092 pin_mask = (1 << 3); /* TXD0 */
1093 pin_mask |= (1 << 4); /* TXD1 */
1094 pin_mask |= (1 << 7); /* TXEN */
1095 pin_mask |= (1 << 8); /* TXCK */
1096 pin_mask |= (1 << 9); /* RXD0 */
1097 pin_mask |= (1 << 10); /* RXD1 */
1098 pin_mask |= (1 << 13); /* RXER */
1099 pin_mask |= (1 << 15); /* RXDV */
1100 pin_mask |= (1 << 16); /* MDC */
1101 pin_mask |= (1 << 17); /* MDIO */
1102
1103 if (!data->is_rmii) {
1104 pin_mask |= (1 << 0); /* COL */
1105 pin_mask |= (1 << 1); /* CRS */
1106 pin_mask |= (1 << 2); /* TXER */
1107 pin_mask |= (1 << 5); /* TXD2 */
1108 pin_mask |= (1 << 6); /* TXD3 */
1109 pin_mask |= (1 << 11); /* RXD2 */
1110 pin_mask |= (1 << 12); /* RXD3 */
1111 pin_mask |= (1 << 14); /* RXCK */
1112 #ifndef CONFIG_BOARD_MIMC200
1113 pin_mask |= (1 << 18); /* SPD */
1114 #endif
1115 }
1116
1117 select_peripheral(PIOC, pin_mask, PERIPH_A, 0);
1118
1119 break;
1120
1121 case 1:
1122 pdev = &macb1_device;
1123
1124 pin_mask = (1 << 13); /* TXD0 */
1125 pin_mask |= (1 << 14); /* TXD1 */
1126 pin_mask |= (1 << 11); /* TXEN */
1127 pin_mask |= (1 << 12); /* TXCK */
1128 pin_mask |= (1 << 10); /* RXD0 */
1129 pin_mask |= (1 << 6); /* RXD1 */
1130 pin_mask |= (1 << 5); /* RXER */
1131 pin_mask |= (1 << 4); /* RXDV */
1132 pin_mask |= (1 << 3); /* MDC */
1133 pin_mask |= (1 << 2); /* MDIO */
1134
1135 #ifndef CONFIG_BOARD_MIMC200
1136 if (!data->is_rmii)
1137 pin_mask |= (1 << 15); /* SPD */
1138 #endif
1139
1140 select_peripheral(PIOD, pin_mask, PERIPH_B, 0);
1141
1142 if (!data->is_rmii) {
1143 pin_mask = (1 << 19); /* COL */
1144 pin_mask |= (1 << 23); /* CRS */
1145 pin_mask |= (1 << 26); /* TXER */
1146 pin_mask |= (1 << 27); /* TXD2 */
1147 pin_mask |= (1 << 28); /* TXD3 */
1148 pin_mask |= (1 << 29); /* RXD2 */
1149 pin_mask |= (1 << 30); /* RXD3 */
1150 pin_mask |= (1 << 24); /* RXCK */
1151
1152 select_peripheral(PIOC, pin_mask, PERIPH_B, 0);
1153 }
1154 break;
1155
1156 default:
1157 return NULL;
1158 }
1159
1160 memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
1161 platform_device_register(pdev);
1162
1163 return pdev;
1164 }
1165 #endif
1166
1167 /* --------------------------------------------------------------------
1168 * SPI
1169 * -------------------------------------------------------------------- */
1170 static struct resource atmel_spi0_resource[] = {
1171 PBMEM(0xffe00000),
1172 IRQ(3),
1173 };
1174 DEFINE_DEV(atmel_spi, 0);
1175 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1176
1177 static struct resource atmel_spi1_resource[] = {
1178 PBMEM(0xffe00400),
1179 IRQ(4),
1180 };
1181 DEFINE_DEV(atmel_spi, 1);
1182 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1183
1184 void __init
1185 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b, unsigned int n)
1186 {
1187 /*
1188 * Manage the chipselects as GPIOs, normally using the same pins
1189 * the SPI controller expects; but boards can use other pins.
1190 */
1191 static u8 __initdata spi_pins[][4] = {
1192 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1193 GPIO_PIN_PA(5), GPIO_PIN_PA(20) },
1194 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1195 GPIO_PIN_PB(4), GPIO_PIN_PA(27) },
1196 };
1197 unsigned int pin, mode;
1198
1199 /* There are only 2 SPI controllers */
1200 if (bus_num > 1)
1201 return;
1202
1203 for (; n; n--, b++) {
1204 b->bus_num = bus_num;
1205 if (b->chip_select >= 4)
1206 continue;
1207 pin = (unsigned)b->controller_data;
1208 if (!pin) {
1209 pin = spi_pins[bus_num][b->chip_select];
1210 b->controller_data = (void *)pin;
1211 }
1212 mode = AT32_GPIOF_OUTPUT;
1213 if (!(b->mode & SPI_CS_HIGH))
1214 mode |= AT32_GPIOF_HIGH;
1215 at32_select_gpio(pin, mode);
1216 }
1217 }
1218
1219 struct platform_device *__init
1220 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1221 {
1222 struct platform_device *pdev;
1223 u32 pin_mask;
1224
1225 switch (id) {
1226 case 0:
1227 pdev = &atmel_spi0_device;
1228 pin_mask = (1 << 1) | (1 << 2); /* MOSI & SCK */
1229
1230 /* pullup MISO so a level is always defined */
1231 select_peripheral(PIOA, (1 << 0), PERIPH_A, AT32_GPIOF_PULLUP);
1232 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1233
1234 at32_spi_setup_slaves(0, b, n);
1235 break;
1236
1237 case 1:
1238 pdev = &atmel_spi1_device;
1239 pin_mask = (1 << 1) | (1 << 5); /* MOSI */
1240
1241 /* pullup MISO so a level is always defined */
1242 select_peripheral(PIOB, (1 << 0), PERIPH_B, AT32_GPIOF_PULLUP);
1243 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
1244
1245 at32_spi_setup_slaves(1, b, n);
1246 break;
1247
1248 default:
1249 return NULL;
1250 }
1251
1252 spi_register_board_info(b, n);
1253 platform_device_register(pdev);
1254 return pdev;
1255 }
1256
1257 /* --------------------------------------------------------------------
1258 * TWI
1259 * -------------------------------------------------------------------- */
1260 static struct resource atmel_twi0_resource[] __initdata = {
1261 PBMEM(0xffe00800),
1262 IRQ(5),
1263 };
1264 static struct clk atmel_twi0_pclk = {
1265 .name = "twi_pclk",
1266 .parent = &pba_clk,
1267 .mode = pba_clk_mode,
1268 .get_rate = pba_clk_get_rate,
1269 .index = 2,
1270 };
1271
1272 struct platform_device *__init at32_add_device_twi(unsigned int id,
1273 struct i2c_board_info *b,
1274 unsigned int n)
1275 {
1276 struct platform_device *pdev;
1277 u32 pin_mask;
1278
1279 if (id != 0)
1280 return NULL;
1281
1282 pdev = platform_device_alloc("atmel_twi", id);
1283 if (!pdev)
1284 return NULL;
1285
1286 if (platform_device_add_resources(pdev, atmel_twi0_resource,
1287 ARRAY_SIZE(atmel_twi0_resource)))
1288 goto err_add_resources;
1289
1290 pin_mask = (1 << 6) | (1 << 7); /* SDA & SDL */
1291
1292 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1293
1294 atmel_twi0_pclk.dev = &pdev->dev;
1295
1296 if (b)
1297 i2c_register_board_info(id, b, n);
1298
1299 platform_device_add(pdev);
1300 return pdev;
1301
1302 err_add_resources:
1303 platform_device_put(pdev);
1304 return NULL;
1305 }
1306
1307 /* --------------------------------------------------------------------
1308 * MMC
1309 * -------------------------------------------------------------------- */
1310 static struct resource atmel_mci0_resource[] __initdata = {
1311 PBMEM(0xfff02400),
1312 IRQ(28),
1313 };
1314 static struct clk atmel_mci0_pclk = {
1315 .name = "mci_clk",
1316 .parent = &pbb_clk,
1317 .mode = pbb_clk_mode,
1318 .get_rate = pbb_clk_get_rate,
1319 .index = 9,
1320 };
1321
1322 struct platform_device *__init
1323 at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1324 {
1325 struct platform_device *pdev;
1326 struct dw_dma_slave *dws;
1327 u32 pioa_mask;
1328 u32 piob_mask;
1329
1330 if (id != 0 || !data)
1331 return NULL;
1332
1333 /* Must have at least one usable slot */
1334 if (!data->slot[0].bus_width && !data->slot[1].bus_width)
1335 return NULL;
1336
1337 pdev = platform_device_alloc("atmel_mci", id);
1338 if (!pdev)
1339 goto fail;
1340
1341 if (platform_device_add_resources(pdev, atmel_mci0_resource,
1342 ARRAY_SIZE(atmel_mci0_resource)))
1343 goto fail;
1344
1345 dws = kzalloc(sizeof(struct dw_dma_slave), GFP_KERNEL);
1346
1347 dws->dma_dev = &dw_dmac0_device.dev;
1348 dws->reg_width = DW_DMA_SLAVE_WIDTH_32BIT;
1349 dws->cfg_hi = (DWC_CFGH_SRC_PER(0)
1350 | DWC_CFGH_DST_PER(1));
1351 dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL
1352 | DWC_CFGL_HS_SRC_POL);
1353
1354 data->dma_slave = dws;
1355
1356 if (platform_device_add_data(pdev, data,
1357 sizeof(struct mci_platform_data)))
1358 goto fail;
1359
1360 /* CLK line is common to both slots */
1361 pioa_mask = 1 << 10;
1362
1363 switch (data->slot[0].bus_width) {
1364 case 4:
1365 pioa_mask |= 1 << 13; /* DATA1 */
1366 pioa_mask |= 1 << 14; /* DATA2 */
1367 pioa_mask |= 1 << 15; /* DATA3 */
1368 /* fall through */
1369 case 1:
1370 pioa_mask |= 1 << 11; /* CMD */
1371 pioa_mask |= 1 << 12; /* DATA0 */
1372
1373 if (gpio_is_valid(data->slot[0].detect_pin))
1374 at32_select_gpio(data->slot[0].detect_pin, 0);
1375 if (gpio_is_valid(data->slot[0].wp_pin))
1376 at32_select_gpio(data->slot[0].wp_pin, 0);
1377 break;
1378 case 0:
1379 /* Slot is unused */
1380 break;
1381 default:
1382 goto fail;
1383 }
1384
1385 select_peripheral(PIOA, pioa_mask, PERIPH_A, 0);
1386 piob_mask = 0;
1387
1388 switch (data->slot[1].bus_width) {
1389 case 4:
1390 piob_mask |= 1 << 8; /* DATA1 */
1391 piob_mask |= 1 << 9; /* DATA2 */
1392 piob_mask |= 1 << 10; /* DATA3 */
1393 /* fall through */
1394 case 1:
1395 piob_mask |= 1 << 6; /* CMD */
1396 piob_mask |= 1 << 7; /* DATA0 */
1397 select_peripheral(PIOB, piob_mask, PERIPH_B, 0);
1398
1399 if (gpio_is_valid(data->slot[1].detect_pin))
1400 at32_select_gpio(data->slot[1].detect_pin, 0);
1401 if (gpio_is_valid(data->slot[1].wp_pin))
1402 at32_select_gpio(data->slot[1].wp_pin, 0);
1403 break;
1404 case 0:
1405 /* Slot is unused */
1406 break;
1407 default:
1408 if (!data->slot[0].bus_width)
1409 goto fail;
1410
1411 data->slot[1].bus_width = 0;
1412 break;
1413 }
1414
1415 atmel_mci0_pclk.dev = &pdev->dev;
1416
1417 platform_device_add(pdev);
1418 return pdev;
1419
1420 fail:
1421 platform_device_put(pdev);
1422 return NULL;
1423 }
1424
1425 /* --------------------------------------------------------------------
1426 * LCDC
1427 * -------------------------------------------------------------------- */
1428 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1429 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1430 static struct resource atmel_lcdfb0_resource[] = {
1431 {
1432 .start = 0xff000000,
1433 .end = 0xff000fff,
1434 .flags = IORESOURCE_MEM,
1435 },
1436 IRQ(1),
1437 {
1438 /* Placeholder for pre-allocated fb memory */
1439 .start = 0x00000000,
1440 .end = 0x00000000,
1441 .flags = 0,
1442 },
1443 };
1444 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1445 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1446 static struct clk atmel_lcdfb0_pixclk = {
1447 .name = "lcdc_clk",
1448 .dev = &atmel_lcdfb0_device.dev,
1449 .mode = genclk_mode,
1450 .get_rate = genclk_get_rate,
1451 .set_rate = genclk_set_rate,
1452 .set_parent = genclk_set_parent,
1453 .index = 7,
1454 };
1455
1456 struct platform_device *__init
1457 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1458 unsigned long fbmem_start, unsigned long fbmem_len,
1459 u64 pin_mask)
1460 {
1461 struct platform_device *pdev;
1462 struct atmel_lcdfb_info *info;
1463 struct fb_monspecs *monspecs;
1464 struct fb_videomode *modedb;
1465 unsigned int modedb_size;
1466 u32 portc_mask, portd_mask, porte_mask;
1467
1468 /*
1469 * Do a deep copy of the fb data, monspecs and modedb. Make
1470 * sure all allocations are done before setting up the
1471 * portmux.
1472 */
1473 monspecs = kmemdup(data->default_monspecs,
1474 sizeof(struct fb_monspecs), GFP_KERNEL);
1475 if (!monspecs)
1476 return NULL;
1477
1478 modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1479 modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1480 if (!modedb)
1481 goto err_dup_modedb;
1482 monspecs->modedb = modedb;
1483
1484 switch (id) {
1485 case 0:
1486 pdev = &atmel_lcdfb0_device;
1487
1488 if (pin_mask == 0ULL)
1489 /* Default to "full" lcdc control signals and 24bit */
1490 pin_mask = ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL;
1491
1492 /* LCDC on port C */
1493 portc_mask = pin_mask & 0xfff80000;
1494 select_peripheral(PIOC, portc_mask, PERIPH_A, 0);
1495
1496 /* LCDC on port D */
1497 portd_mask = pin_mask & 0x0003ffff;
1498 select_peripheral(PIOD, portd_mask, PERIPH_A, 0);
1499
1500 /* LCDC on port E */
1501 porte_mask = (pin_mask >> 32) & 0x0007ffff;
1502 select_peripheral(PIOE, porte_mask, PERIPH_B, 0);
1503
1504 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1505 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1506 break;
1507
1508 default:
1509 goto err_invalid_id;
1510 }
1511
1512 if (fbmem_len) {
1513 pdev->resource[2].start = fbmem_start;
1514 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1515 pdev->resource[2].flags = IORESOURCE_MEM;
1516 }
1517
1518 info = pdev->dev.platform_data;
1519 memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1520 info->default_monspecs = monspecs;
1521
1522 platform_device_register(pdev);
1523 return pdev;
1524
1525 err_invalid_id:
1526 kfree(modedb);
1527 err_dup_modedb:
1528 kfree(monspecs);
1529 return NULL;
1530 }
1531 #endif
1532
1533 /* --------------------------------------------------------------------
1534 * PWM
1535 * -------------------------------------------------------------------- */
1536 static struct resource atmel_pwm0_resource[] __initdata = {
1537 PBMEM(0xfff01400),
1538 IRQ(24),
1539 };
1540 static struct clk atmel_pwm0_mck = {
1541 .name = "pwm_clk",
1542 .parent = &pbb_clk,
1543 .mode = pbb_clk_mode,
1544 .get_rate = pbb_clk_get_rate,
1545 .index = 5,
1546 };
1547
1548 struct platform_device *__init at32_add_device_pwm(u32 mask)
1549 {
1550 struct platform_device *pdev;
1551 u32 pin_mask;
1552
1553 if (!mask)
1554 return NULL;
1555
1556 pdev = platform_device_alloc("atmel_pwm", 0);
1557 if (!pdev)
1558 return NULL;
1559
1560 if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1561 ARRAY_SIZE(atmel_pwm0_resource)))
1562 goto out_free_pdev;
1563
1564 if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1565 goto out_free_pdev;
1566
1567 pin_mask = 0;
1568 if (mask & (1 << 0))
1569 pin_mask |= (1 << 28);
1570 if (mask & (1 << 1))
1571 pin_mask |= (1 << 29);
1572 if (pin_mask > 0)
1573 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1574
1575 pin_mask = 0;
1576 if (mask & (1 << 2))
1577 pin_mask |= (1 << 21);
1578 if (mask & (1 << 3))
1579 pin_mask |= (1 << 22);
1580 if (pin_mask > 0)
1581 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1582
1583 atmel_pwm0_mck.dev = &pdev->dev;
1584
1585 platform_device_add(pdev);
1586
1587 return pdev;
1588
1589 out_free_pdev:
1590 platform_device_put(pdev);
1591 return NULL;
1592 }
1593
1594 /* --------------------------------------------------------------------
1595 * SSC
1596 * -------------------------------------------------------------------- */
1597 static struct resource ssc0_resource[] = {
1598 PBMEM(0xffe01c00),
1599 IRQ(10),
1600 };
1601 DEFINE_DEV(ssc, 0);
1602 DEV_CLK(pclk, ssc0, pba, 7);
1603
1604 static struct resource ssc1_resource[] = {
1605 PBMEM(0xffe02000),
1606 IRQ(11),
1607 };
1608 DEFINE_DEV(ssc, 1);
1609 DEV_CLK(pclk, ssc1, pba, 8);
1610
1611 static struct resource ssc2_resource[] = {
1612 PBMEM(0xffe02400),
1613 IRQ(12),
1614 };
1615 DEFINE_DEV(ssc, 2);
1616 DEV_CLK(pclk, ssc2, pba, 9);
1617
1618 struct platform_device *__init
1619 at32_add_device_ssc(unsigned int id, unsigned int flags)
1620 {
1621 struct platform_device *pdev;
1622 u32 pin_mask = 0;
1623
1624 switch (id) {
1625 case 0:
1626 pdev = &ssc0_device;
1627 if (flags & ATMEL_SSC_RF)
1628 pin_mask |= (1 << 21); /* RF */
1629 if (flags & ATMEL_SSC_RK)
1630 pin_mask |= (1 << 22); /* RK */
1631 if (flags & ATMEL_SSC_TK)
1632 pin_mask |= (1 << 23); /* TK */
1633 if (flags & ATMEL_SSC_TF)
1634 pin_mask |= (1 << 24); /* TF */
1635 if (flags & ATMEL_SSC_TD)
1636 pin_mask |= (1 << 25); /* TD */
1637 if (flags & ATMEL_SSC_RD)
1638 pin_mask |= (1 << 26); /* RD */
1639
1640 if (pin_mask > 0)
1641 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1642
1643 break;
1644 case 1:
1645 pdev = &ssc1_device;
1646 if (flags & ATMEL_SSC_RF)
1647 pin_mask |= (1 << 0); /* RF */
1648 if (flags & ATMEL_SSC_RK)
1649 pin_mask |= (1 << 1); /* RK */
1650 if (flags & ATMEL_SSC_TK)
1651 pin_mask |= (1 << 2); /* TK */
1652 if (flags & ATMEL_SSC_TF)
1653 pin_mask |= (1 << 3); /* TF */
1654 if (flags & ATMEL_SSC_TD)
1655 pin_mask |= (1 << 4); /* TD */
1656 if (flags & ATMEL_SSC_RD)
1657 pin_mask |= (1 << 5); /* RD */
1658
1659 if (pin_mask > 0)
1660 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1661
1662 break;
1663 case 2:
1664 pdev = &ssc2_device;
1665 if (flags & ATMEL_SSC_TD)
1666 pin_mask |= (1 << 13); /* TD */
1667 if (flags & ATMEL_SSC_RD)
1668 pin_mask |= (1 << 14); /* RD */
1669 if (flags & ATMEL_SSC_TK)
1670 pin_mask |= (1 << 15); /* TK */
1671 if (flags & ATMEL_SSC_TF)
1672 pin_mask |= (1 << 16); /* TF */
1673 if (flags & ATMEL_SSC_RF)
1674 pin_mask |= (1 << 17); /* RF */
1675 if (flags & ATMEL_SSC_RK)
1676 pin_mask |= (1 << 18); /* RK */
1677
1678 if (pin_mask > 0)
1679 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
1680
1681 break;
1682 default:
1683 return NULL;
1684 }
1685
1686 platform_device_register(pdev);
1687 return pdev;
1688 }
1689
1690 /* --------------------------------------------------------------------
1691 * USB Device Controller
1692 * -------------------------------------------------------------------- */
1693 static struct resource usba0_resource[] __initdata = {
1694 {
1695 .start = 0xff300000,
1696 .end = 0xff3fffff,
1697 .flags = IORESOURCE_MEM,
1698 }, {
1699 .start = 0xfff03000,
1700 .end = 0xfff033ff,
1701 .flags = IORESOURCE_MEM,
1702 },
1703 IRQ(31),
1704 };
1705 static struct clk usba0_pclk = {
1706 .name = "pclk",
1707 .parent = &pbb_clk,
1708 .mode = pbb_clk_mode,
1709 .get_rate = pbb_clk_get_rate,
1710 .index = 12,
1711 };
1712 static struct clk usba0_hclk = {
1713 .name = "hclk",
1714 .parent = &hsb_clk,
1715 .mode = hsb_clk_mode,
1716 .get_rate = hsb_clk_get_rate,
1717 .index = 6,
1718 };
1719
1720 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
1721 [idx] = { \
1722 .name = nam, \
1723 .index = idx, \
1724 .fifo_size = maxpkt, \
1725 .nr_banks = maxbk, \
1726 .can_dma = dma, \
1727 .can_isoc = isoc, \
1728 }
1729
1730 static struct usba_ep_data at32_usba_ep[] __initdata = {
1731 EP("ep0", 0, 64, 1, 0, 0),
1732 EP("ep1", 1, 512, 2, 1, 1),
1733 EP("ep2", 2, 512, 2, 1, 1),
1734 EP("ep3-int", 3, 64, 3, 1, 0),
1735 EP("ep4-int", 4, 64, 3, 1, 0),
1736 EP("ep5", 5, 1024, 3, 1, 1),
1737 EP("ep6", 6, 1024, 3, 1, 1),
1738 };
1739
1740 #undef EP
1741
1742 struct platform_device *__init
1743 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1744 {
1745 /*
1746 * pdata doesn't have room for any endpoints, so we need to
1747 * append room for the ones we need right after it.
1748 */
1749 struct {
1750 struct usba_platform_data pdata;
1751 struct usba_ep_data ep[7];
1752 } usba_data;
1753 struct platform_device *pdev;
1754
1755 if (id != 0)
1756 return NULL;
1757
1758 pdev = platform_device_alloc("atmel_usba_udc", 0);
1759 if (!pdev)
1760 return NULL;
1761
1762 if (platform_device_add_resources(pdev, usba0_resource,
1763 ARRAY_SIZE(usba0_resource)))
1764 goto out_free_pdev;
1765
1766 if (data)
1767 usba_data.pdata.vbus_pin = data->vbus_pin;
1768 else
1769 usba_data.pdata.vbus_pin = -EINVAL;
1770
1771 data = &usba_data.pdata;
1772 data->num_ep = ARRAY_SIZE(at32_usba_ep);
1773 memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1774
1775 if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1776 goto out_free_pdev;
1777
1778 if (gpio_is_valid(data->vbus_pin))
1779 at32_select_gpio(data->vbus_pin, 0);
1780
1781 usba0_pclk.dev = &pdev->dev;
1782 usba0_hclk.dev = &pdev->dev;
1783
1784 platform_device_add(pdev);
1785
1786 return pdev;
1787
1788 out_free_pdev:
1789 platform_device_put(pdev);
1790 return NULL;
1791 }
1792
1793 /* --------------------------------------------------------------------
1794 * IDE / CompactFlash
1795 * -------------------------------------------------------------------- */
1796 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1797 static struct resource at32_smc_cs4_resource[] __initdata = {
1798 {
1799 .start = 0x04000000,
1800 .end = 0x07ffffff,
1801 .flags = IORESOURCE_MEM,
1802 },
1803 IRQ(~0UL), /* Magic IRQ will be overridden */
1804 };
1805 static struct resource at32_smc_cs5_resource[] __initdata = {
1806 {
1807 .start = 0x20000000,
1808 .end = 0x23ffffff,
1809 .flags = IORESOURCE_MEM,
1810 },
1811 IRQ(~0UL), /* Magic IRQ will be overridden */
1812 };
1813
1814 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1815 unsigned int cs, unsigned int extint)
1816 {
1817 static unsigned int extint_pin_map[4] __initdata = {
1818 (1 << 25),
1819 (1 << 26),
1820 (1 << 27),
1821 (1 << 28),
1822 };
1823 static bool common_pins_initialized __initdata = false;
1824 unsigned int extint_pin;
1825 int ret;
1826 u32 pin_mask;
1827
1828 if (extint >= ARRAY_SIZE(extint_pin_map))
1829 return -EINVAL;
1830 extint_pin = extint_pin_map[extint];
1831
1832 switch (cs) {
1833 case 4:
1834 ret = platform_device_add_resources(pdev,
1835 at32_smc_cs4_resource,
1836 ARRAY_SIZE(at32_smc_cs4_resource));
1837 if (ret)
1838 return ret;
1839
1840 /* NCS4 -> OE_N */
1841 select_peripheral(PIOE, (1 << 21), PERIPH_A, 0);
1842 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE);
1843 break;
1844 case 5:
1845 ret = platform_device_add_resources(pdev,
1846 at32_smc_cs5_resource,
1847 ARRAY_SIZE(at32_smc_cs5_resource));
1848 if (ret)
1849 return ret;
1850
1851 /* NCS5 -> OE_N */
1852 select_peripheral(PIOE, (1 << 22), PERIPH_A, 0);
1853 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE);
1854 break;
1855 default:
1856 return -EINVAL;
1857 }
1858
1859 if (!common_pins_initialized) {
1860 pin_mask = (1 << 19); /* CFCE1 -> CS0_N */
1861 pin_mask |= (1 << 20); /* CFCE2 -> CS1_N */
1862 pin_mask |= (1 << 23); /* CFRNW -> DIR */
1863 pin_mask |= (1 << 24); /* NWAIT <- IORDY */
1864
1865 select_peripheral(PIOE, pin_mask, PERIPH_A, 0);
1866
1867 common_pins_initialized = true;
1868 }
1869
1870 select_peripheral(PIOB, extint_pin, PERIPH_A, AT32_GPIOF_DEGLITCH);
1871
1872 pdev->resource[1].start = EIM_IRQ_BASE + extint;
1873 pdev->resource[1].end = pdev->resource[1].start;
1874
1875 return 0;
1876 }
1877
1878 struct platform_device *__init
1879 at32_add_device_ide(unsigned int id, unsigned int extint,
1880 struct ide_platform_data *data)
1881 {
1882 struct platform_device *pdev;
1883
1884 pdev = platform_device_alloc("at32_ide", id);
1885 if (!pdev)
1886 goto fail;
1887
1888 if (platform_device_add_data(pdev, data,
1889 sizeof(struct ide_platform_data)))
1890 goto fail;
1891
1892 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1893 goto fail;
1894
1895 platform_device_add(pdev);
1896 return pdev;
1897
1898 fail:
1899 platform_device_put(pdev);
1900 return NULL;
1901 }
1902
1903 struct platform_device *__init
1904 at32_add_device_cf(unsigned int id, unsigned int extint,
1905 struct cf_platform_data *data)
1906 {
1907 struct platform_device *pdev;
1908
1909 pdev = platform_device_alloc("at32_cf", id);
1910 if (!pdev)
1911 goto fail;
1912
1913 if (platform_device_add_data(pdev, data,
1914 sizeof(struct cf_platform_data)))
1915 goto fail;
1916
1917 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1918 goto fail;
1919
1920 if (gpio_is_valid(data->detect_pin))
1921 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1922 if (gpio_is_valid(data->reset_pin))
1923 at32_select_gpio(data->reset_pin, 0);
1924 if (gpio_is_valid(data->vcc_pin))
1925 at32_select_gpio(data->vcc_pin, 0);
1926 /* READY is used as extint, so we can't select it as gpio */
1927
1928 platform_device_add(pdev);
1929 return pdev;
1930
1931 fail:
1932 platform_device_put(pdev);
1933 return NULL;
1934 }
1935 #endif
1936
1937 /* --------------------------------------------------------------------
1938 * NAND Flash / SmartMedia
1939 * -------------------------------------------------------------------- */
1940 static struct resource smc_cs3_resource[] __initdata = {
1941 {
1942 .start = 0x0c000000,
1943 .end = 0x0fffffff,
1944 .flags = IORESOURCE_MEM,
1945 }, {
1946 .start = 0xfff03c00,
1947 .end = 0xfff03fff,
1948 .flags = IORESOURCE_MEM,
1949 },
1950 };
1951
1952 struct platform_device *__init
1953 at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
1954 {
1955 struct platform_device *pdev;
1956
1957 if (id != 0 || !data)
1958 return NULL;
1959
1960 pdev = platform_device_alloc("atmel_nand", id);
1961 if (!pdev)
1962 goto fail;
1963
1964 if (platform_device_add_resources(pdev, smc_cs3_resource,
1965 ARRAY_SIZE(smc_cs3_resource)))
1966 goto fail;
1967
1968 if (platform_device_add_data(pdev, data,
1969 sizeof(struct atmel_nand_data)))
1970 goto fail;
1971
1972 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
1973 if (data->enable_pin)
1974 at32_select_gpio(data->enable_pin,
1975 AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
1976 if (data->rdy_pin)
1977 at32_select_gpio(data->rdy_pin, 0);
1978 if (data->det_pin)
1979 at32_select_gpio(data->det_pin, 0);
1980
1981 platform_device_add(pdev);
1982 return pdev;
1983
1984 fail:
1985 platform_device_put(pdev);
1986 return NULL;
1987 }
1988
1989 /* --------------------------------------------------------------------
1990 * AC97C
1991 * -------------------------------------------------------------------- */
1992 static struct resource atmel_ac97c0_resource[] __initdata = {
1993 PBMEM(0xfff02800),
1994 IRQ(29),
1995 };
1996 static struct clk atmel_ac97c0_pclk = {
1997 .name = "pclk",
1998 .parent = &pbb_clk,
1999 .mode = pbb_clk_mode,
2000 .get_rate = pbb_clk_get_rate,
2001 .index = 10,
2002 };
2003
2004 struct platform_device *__init
2005 at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data,
2006 unsigned int flags)
2007 {
2008 struct platform_device *pdev;
2009 struct dw_dma_slave *rx_dws;
2010 struct dw_dma_slave *tx_dws;
2011 struct ac97c_platform_data _data;
2012 u32 pin_mask;
2013
2014 if (id != 0)
2015 return NULL;
2016
2017 pdev = platform_device_alloc("atmel_ac97c", id);
2018 if (!pdev)
2019 return NULL;
2020
2021 if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
2022 ARRAY_SIZE(atmel_ac97c0_resource)))
2023 goto out_free_resources;
2024
2025 if (!data) {
2026 data = &_data;
2027 memset(data, 0, sizeof(struct ac97c_platform_data));
2028 data->reset_pin = -ENODEV;
2029 }
2030
2031 rx_dws = &data->rx_dws;
2032 tx_dws = &data->tx_dws;
2033
2034 /* Check if DMA slave interface for capture should be configured. */
2035 if (flags & AC97C_CAPTURE) {
2036 rx_dws->dma_dev = &dw_dmac0_device.dev;
2037 rx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT;
2038 rx_dws->cfg_hi = DWC_CFGH_SRC_PER(3);
2039 rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2040 }
2041
2042 /* Check if DMA slave interface for playback should be configured. */
2043 if (flags & AC97C_PLAYBACK) {
2044 tx_dws->dma_dev = &dw_dmac0_device.dev;
2045 tx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT;
2046 tx_dws->cfg_hi = DWC_CFGH_DST_PER(4);
2047 tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2048 }
2049
2050 if (platform_device_add_data(pdev, data,
2051 sizeof(struct ac97c_platform_data)))
2052 goto out_free_resources;
2053
2054 /* SDO | SYNC | SCLK | SDI */
2055 pin_mask = (1 << 20) | (1 << 21) | (1 << 22) | (1 << 23);
2056
2057 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
2058
2059 if (gpio_is_valid(data->reset_pin))
2060 at32_select_gpio(data->reset_pin, AT32_GPIOF_OUTPUT
2061 | AT32_GPIOF_HIGH);
2062
2063 atmel_ac97c0_pclk.dev = &pdev->dev;
2064
2065 platform_device_add(pdev);
2066 return pdev;
2067
2068 out_free_resources:
2069 platform_device_put(pdev);
2070 return NULL;
2071 }
2072
2073 /* --------------------------------------------------------------------
2074 * ABDAC
2075 * -------------------------------------------------------------------- */
2076 static struct resource abdac0_resource[] __initdata = {
2077 PBMEM(0xfff02000),
2078 IRQ(27),
2079 };
2080 static struct clk abdac0_pclk = {
2081 .name = "pclk",
2082 .parent = &pbb_clk,
2083 .mode = pbb_clk_mode,
2084 .get_rate = pbb_clk_get_rate,
2085 .index = 8,
2086 };
2087 static struct clk abdac0_sample_clk = {
2088 .name = "sample_clk",
2089 .mode = genclk_mode,
2090 .get_rate = genclk_get_rate,
2091 .set_rate = genclk_set_rate,
2092 .set_parent = genclk_set_parent,
2093 .index = 6,
2094 };
2095
2096 struct platform_device *__init
2097 at32_add_device_abdac(unsigned int id, struct atmel_abdac_pdata *data)
2098 {
2099 struct platform_device *pdev;
2100 struct dw_dma_slave *dws;
2101 u32 pin_mask;
2102
2103 if (id != 0 || !data)
2104 return NULL;
2105
2106 pdev = platform_device_alloc("atmel_abdac", id);
2107 if (!pdev)
2108 return NULL;
2109
2110 if (platform_device_add_resources(pdev, abdac0_resource,
2111 ARRAY_SIZE(abdac0_resource)))
2112 goto out_free_resources;
2113
2114 dws = &data->dws;
2115
2116 dws->dma_dev = &dw_dmac0_device.dev;
2117 dws->reg_width = DW_DMA_SLAVE_WIDTH_32BIT;
2118 dws->cfg_hi = DWC_CFGH_DST_PER(2);
2119 dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2120
2121 if (platform_device_add_data(pdev, data,
2122 sizeof(struct atmel_abdac_pdata)))
2123 goto out_free_resources;
2124
2125 pin_mask = (1 << 20) | (1 << 22); /* DATA1 & DATAN1 */
2126 pin_mask |= (1 << 21) | (1 << 23); /* DATA0 & DATAN0 */
2127
2128 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
2129
2130 abdac0_pclk.dev = &pdev->dev;
2131 abdac0_sample_clk.dev = &pdev->dev;
2132
2133 platform_device_add(pdev);
2134 return pdev;
2135
2136 out_free_resources:
2137 platform_device_put(pdev);
2138 return NULL;
2139 }
2140
2141 /* --------------------------------------------------------------------
2142 * GCLK
2143 * -------------------------------------------------------------------- */
2144 static struct clk gclk0 = {
2145 .name = "gclk0",
2146 .mode = genclk_mode,
2147 .get_rate = genclk_get_rate,
2148 .set_rate = genclk_set_rate,
2149 .set_parent = genclk_set_parent,
2150 .index = 0,
2151 };
2152 static struct clk gclk1 = {
2153 .name = "gclk1",
2154 .mode = genclk_mode,
2155 .get_rate = genclk_get_rate,
2156 .set_rate = genclk_set_rate,
2157 .set_parent = genclk_set_parent,
2158 .index = 1,
2159 };
2160 static struct clk gclk2 = {
2161 .name = "gclk2",
2162 .mode = genclk_mode,
2163 .get_rate = genclk_get_rate,
2164 .set_rate = genclk_set_rate,
2165 .set_parent = genclk_set_parent,
2166 .index = 2,
2167 };
2168 static struct clk gclk3 = {
2169 .name = "gclk3",
2170 .mode = genclk_mode,
2171 .get_rate = genclk_get_rate,
2172 .set_rate = genclk_set_rate,
2173 .set_parent = genclk_set_parent,
2174 .index = 3,
2175 };
2176 static struct clk gclk4 = {
2177 .name = "gclk4",
2178 .mode = genclk_mode,
2179 .get_rate = genclk_get_rate,
2180 .set_rate = genclk_set_rate,
2181 .set_parent = genclk_set_parent,
2182 .index = 4,
2183 };
2184
2185 static __initdata struct clk *init_clocks[] = {
2186 &osc32k,
2187 &osc0,
2188 &osc1,
2189 &pll0,
2190 &pll1,
2191 &cpu_clk,
2192 &hsb_clk,
2193 &pba_clk,
2194 &pbb_clk,
2195 &at32_pm_pclk,
2196 &at32_intc0_pclk,
2197 &at32_hmatrix_clk,
2198 &ebi_clk,
2199 &hramc_clk,
2200 &sdramc_clk,
2201 &smc0_pclk,
2202 &smc0_mck,
2203 &pdc_hclk,
2204 &pdc_pclk,
2205 &dw_dmac0_hclk,
2206 &pico_clk,
2207 &pio0_mck,
2208 &pio1_mck,
2209 &pio2_mck,
2210 &pio3_mck,
2211 &pio4_mck,
2212 &at32_tcb0_t0_clk,
2213 &at32_tcb1_t0_clk,
2214 &atmel_psif0_pclk,
2215 &atmel_psif1_pclk,
2216 &atmel_usart0_usart,
2217 &atmel_usart1_usart,
2218 &atmel_usart2_usart,
2219 &atmel_usart3_usart,
2220 &atmel_pwm0_mck,
2221 #if defined(CONFIG_CPU_AT32AP7000)
2222 &macb0_hclk,
2223 &macb0_pclk,
2224 &macb1_hclk,
2225 &macb1_pclk,
2226 #endif
2227 &atmel_spi0_spi_clk,
2228 &atmel_spi1_spi_clk,
2229 &atmel_twi0_pclk,
2230 &atmel_mci0_pclk,
2231 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2232 &atmel_lcdfb0_hck1,
2233 &atmel_lcdfb0_pixclk,
2234 #endif
2235 &ssc0_pclk,
2236 &ssc1_pclk,
2237 &ssc2_pclk,
2238 &usba0_hclk,
2239 &usba0_pclk,
2240 &atmel_ac97c0_pclk,
2241 &abdac0_pclk,
2242 &abdac0_sample_clk,
2243 &gclk0,
2244 &gclk1,
2245 &gclk2,
2246 &gclk3,
2247 &gclk4,
2248 };
2249
2250 void __init setup_platform(void)
2251 {
2252 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2253 int i;
2254
2255 if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2256 main_clock = &pll0;
2257 cpu_clk.parent = &pll0;
2258 } else {
2259 main_clock = &osc0;
2260 cpu_clk.parent = &osc0;
2261 }
2262
2263 if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2264 pll0.parent = &osc1;
2265 if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2266 pll1.parent = &osc1;
2267
2268 genclk_init_parent(&gclk0);
2269 genclk_init_parent(&gclk1);
2270 genclk_init_parent(&gclk2);
2271 genclk_init_parent(&gclk3);
2272 genclk_init_parent(&gclk4);
2273 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2274 genclk_init_parent(&atmel_lcdfb0_pixclk);
2275 #endif
2276 genclk_init_parent(&abdac0_sample_clk);
2277
2278 /*
2279 * Build initial dynamic clock list by registering all clocks
2280 * from the array.
2281 * At the same time, turn on all clocks that have at least one
2282 * user already, and turn off everything else. We only do this
2283 * for module clocks, and even though it isn't particularly
2284 * pretty to check the address of the mode function, it should
2285 * do the trick...
2286 */
2287 for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
2288 struct clk *clk = init_clocks[i];
2289
2290 /* first, register clock */
2291 at32_clk_register(clk);
2292
2293 if (clk->users == 0)
2294 continue;
2295
2296 if (clk->mode == &cpu_clk_mode)
2297 cpu_mask |= 1 << clk->index;
2298 else if (clk->mode == &hsb_clk_mode)
2299 hsb_mask |= 1 << clk->index;
2300 else if (clk->mode == &pba_clk_mode)
2301 pba_mask |= 1 << clk->index;
2302 else if (clk->mode == &pbb_clk_mode)
2303 pbb_mask |= 1 << clk->index;
2304 }
2305
2306 pm_writel(CPU_MASK, cpu_mask);
2307 pm_writel(HSB_MASK, hsb_mask);
2308 pm_writel(PBA_MASK, pba_mask);
2309 pm_writel(PBB_MASK, pbb_mask);
2310
2311 /* Initialize the port muxes */
2312 at32_init_pio(&pio0_device);
2313 at32_init_pio(&pio1_device);
2314 at32_init_pio(&pio2_device);
2315 at32_init_pio(&pio3_device);
2316 at32_init_pio(&pio4_device);
2317 }
2318
2319 struct gen_pool *sram_pool;
2320
2321 static int __init sram_init(void)
2322 {
2323 struct gen_pool *pool;
2324
2325 /* 1KiB granularity */
2326 pool = gen_pool_create(10, -1);
2327 if (!pool)
2328 goto fail;
2329
2330 if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
2331 goto err_pool_add;
2332
2333 sram_pool = pool;
2334 return 0;
2335
2336 err_pool_add:
2337 gen_pool_destroy(pool);
2338 fail:
2339 pr_err("Failed to create SRAM pool\n");
2340 return -ENOMEM;
2341 }
2342 core_initcall(sram_init);
mm of the moment repository