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"[PATCH] Fix leaks on /proc/{*/sched,sched_debug,timer_list,timer_stats}" and
[mmotm.git] / arch / mips / include / asm / mipsregs.h
bloba581d60cbcc21e395a1e7a9ba772c4b0be5dcb4b
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
12 */
13 #ifndef _ASM_MIPSREGS_H
14 #define _ASM_MIPSREGS_H
15
16 #include <linux/linkage.h>
17 #include <asm/hazards.h>
18 #include <asm/war.h>
19
20 /*
21 * The following macros are especially useful for __asm__
22 * inline assembler.
23 */
24 #ifndef __STR
25 #define __STR(x) #x
26 #endif
27 #ifndef STR
28 #define STR(x) __STR(x)
29 #endif
30
31 /*
32 * Configure language
33 */
34 #ifdef __ASSEMBLY__
35 #define _ULCAST_
36 #else
37 #define _ULCAST_ (unsigned long)
38 #endif
39
40 /*
41 * Coprocessor 0 register names
42 */
43 #define CP0_INDEX $0
44 #define CP0_RANDOM $1
45 #define CP0_ENTRYLO0 $2
46 #define CP0_ENTRYLO1 $3
47 #define CP0_CONF $3
48 #define CP0_CONTEXT $4
49 #define CP0_PAGEMASK $5
50 #define CP0_WIRED $6
51 #define CP0_INFO $7
52 #define CP0_BADVADDR $8
53 #define CP0_COUNT $9
54 #define CP0_ENTRYHI $10
55 #define CP0_COMPARE $11
56 #define CP0_STATUS $12
57 #define CP0_CAUSE $13
58 #define CP0_EPC $14
59 #define CP0_PRID $15
60 #define CP0_CONFIG $16
61 #define CP0_LLADDR $17
62 #define CP0_WATCHLO $18
63 #define CP0_WATCHHI $19
64 #define CP0_XCONTEXT $20
65 #define CP0_FRAMEMASK $21
66 #define CP0_DIAGNOSTIC $22
67 #define CP0_DEBUG $23
68 #define CP0_DEPC $24
69 #define CP0_PERFORMANCE $25
70 #define CP0_ECC $26
71 #define CP0_CACHEERR $27
72 #define CP0_TAGLO $28
73 #define CP0_TAGHI $29
74 #define CP0_ERROREPC $30
75 #define CP0_DESAVE $31
76
77 /*
78 * R4640/R4650 cp0 register names. These registers are listed
79 * here only for completeness; without MMU these CPUs are not useable
80 * by Linux. A future ELKS port might take make Linux run on them
81 * though ...
82 */
83 #define CP0_IBASE $0
84 #define CP0_IBOUND $1
85 #define CP0_DBASE $2
86 #define CP0_DBOUND $3
87 #define CP0_CALG $17
88 #define CP0_IWATCH $18
89 #define CP0_DWATCH $19
90
91 /*
92 * Coprocessor 0 Set 1 register names
93 */
94 #define CP0_S1_DERRADDR0 $26
95 #define CP0_S1_DERRADDR1 $27
96 #define CP0_S1_INTCONTROL $20
97
98 /*
99 * Coprocessor 0 Set 2 register names
100 */
101 #define CP0_S2_SRSCTL $12 /* MIPSR2 */
102
103 /*
104 * Coprocessor 0 Set 3 register names
105 */
106 #define CP0_S3_SRSMAP $12 /* MIPSR2 */
107
108 /*
109 * TX39 Series
110 */
111 #define CP0_TX39_CACHE $7
112
113 /*
114 * Coprocessor 1 (FPU) register names
115 */
116 #define CP1_REVISION $0
117 #define CP1_STATUS $31
118
119 /*
120 * FPU Status Register Values
121 */
122 /*
123 * Status Register Values
124 */
125
126 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
127 #define FPU_CSR_COND 0x00800000 /* $fcc0 */
128 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */
129 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */
130 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */
131 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */
132 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */
133 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */
134 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */
135 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */
136
137 /*
138 * X the exception cause indicator
139 * E the exception enable
140 * S the sticky/flag bit
141 */
142 #define FPU_CSR_ALL_X 0x0003f000
143 #define FPU_CSR_UNI_X 0x00020000
144 #define FPU_CSR_INV_X 0x00010000
145 #define FPU_CSR_DIV_X 0x00008000
146 #define FPU_CSR_OVF_X 0x00004000
147 #define FPU_CSR_UDF_X 0x00002000
148 #define FPU_CSR_INE_X 0x00001000
149
150 #define FPU_CSR_ALL_E 0x00000f80
151 #define FPU_CSR_INV_E 0x00000800
152 #define FPU_CSR_DIV_E 0x00000400
153 #define FPU_CSR_OVF_E 0x00000200
154 #define FPU_CSR_UDF_E 0x00000100
155 #define FPU_CSR_INE_E 0x00000080
156
157 #define FPU_CSR_ALL_S 0x0000007c
158 #define FPU_CSR_INV_S 0x00000040
159 #define FPU_CSR_DIV_S 0x00000020
160 #define FPU_CSR_OVF_S 0x00000010
161 #define FPU_CSR_UDF_S 0x00000008
162 #define FPU_CSR_INE_S 0x00000004
163
164 /* rounding mode */
165 #define FPU_CSR_RN 0x0 /* nearest */
166 #define FPU_CSR_RZ 0x1 /* towards zero */
167 #define FPU_CSR_RU 0x2 /* towards +Infinity */
168 #define FPU_CSR_RD 0x3 /* towards -Infinity */
169
170
171 /*
172 * Values for PageMask register
173 */
174 #ifdef CONFIG_CPU_VR41XX
175
176 /* Why doesn't stupidity hurt ... */
177
178 #define PM_1K 0x00000000
179 #define PM_4K 0x00001800
180 #define PM_16K 0x00007800
181 #define PM_64K 0x0001f800
182 #define PM_256K 0x0007f800
183
184 #else
185
186 #define PM_4K 0x00000000
187 #define PM_8K 0x00002000
188 #define PM_16K 0x00006000
189 #define PM_32K 0x0000e000
190 #define PM_64K 0x0001e000
191 #define PM_128K 0x0003e000
192 #define PM_256K 0x0007e000
193 #define PM_512K 0x000fe000
194 #define PM_1M 0x001fe000
195 #define PM_2M 0x003fe000
196 #define PM_4M 0x007fe000
197 #define PM_8M 0x00ffe000
198 #define PM_16M 0x01ffe000
199 #define PM_32M 0x03ffe000
200 #define PM_64M 0x07ffe000
201 #define PM_256M 0x1fffe000
202 #define PM_1G 0x7fffe000
203
204 #endif
205
206 /*
207 * Default page size for a given kernel configuration
208 */
209 #ifdef CONFIG_PAGE_SIZE_4KB
210 #define PM_DEFAULT_MASK PM_4K
211 #elif defined(CONFIG_PAGE_SIZE_8KB)
212 #define PM_DEFAULT_MASK PM_8K
213 #elif defined(CONFIG_PAGE_SIZE_16KB)
214 #define PM_DEFAULT_MASK PM_16K
215 #elif defined(CONFIG_PAGE_SIZE_32KB)
216 #define PM_DEFAULT_MASK PM_32K
217 #elif defined(CONFIG_PAGE_SIZE_64KB)
218 #define PM_DEFAULT_MASK PM_64K
219 #else
220 #error Bad page size configuration!
221 #endif
222
223 /*
224 * Default huge tlb size for a given kernel configuration
225 */
226 #ifdef CONFIG_PAGE_SIZE_4KB
227 #define PM_HUGE_MASK PM_1M
228 #elif defined(CONFIG_PAGE_SIZE_8KB)
229 #define PM_HUGE_MASK PM_4M
230 #elif defined(CONFIG_PAGE_SIZE_16KB)
231 #define PM_HUGE_MASK PM_16M
232 #elif defined(CONFIG_PAGE_SIZE_32KB)
233 #define PM_HUGE_MASK PM_64M
234 #elif defined(CONFIG_PAGE_SIZE_64KB)
235 #define PM_HUGE_MASK PM_256M
236 #elif defined(CONFIG_HUGETLB_PAGE)
237 #error Bad page size configuration for hugetlbfs!
238 #endif
239
240 /*
241 * Values used for computation of new tlb entries
242 */
243 #define PL_4K 12
244 #define PL_16K 14
245 #define PL_64K 16
246 #define PL_256K 18
247 #define PL_1M 20
248 #define PL_4M 22
249 #define PL_16M 24
250 #define PL_64M 26
251 #define PL_256M 28
252
253 /*
254 * R4x00 interrupt enable / cause bits
255 */
256 #define IE_SW0 (_ULCAST_(1) << 8)
257 #define IE_SW1 (_ULCAST_(1) << 9)
258 #define IE_IRQ0 (_ULCAST_(1) << 10)
259 #define IE_IRQ1 (_ULCAST_(1) << 11)
260 #define IE_IRQ2 (_ULCAST_(1) << 12)
261 #define IE_IRQ3 (_ULCAST_(1) << 13)
262 #define IE_IRQ4 (_ULCAST_(1) << 14)
263 #define IE_IRQ5 (_ULCAST_(1) << 15)
264
265 /*
266 * R4x00 interrupt cause bits
267 */
268 #define C_SW0 (_ULCAST_(1) << 8)
269 #define C_SW1 (_ULCAST_(1) << 9)
270 #define C_IRQ0 (_ULCAST_(1) << 10)
271 #define C_IRQ1 (_ULCAST_(1) << 11)
272 #define C_IRQ2 (_ULCAST_(1) << 12)
273 #define C_IRQ3 (_ULCAST_(1) << 13)
274 #define C_IRQ4 (_ULCAST_(1) << 14)
275 #define C_IRQ5 (_ULCAST_(1) << 15)
276
277 /*
278 * Bitfields in the R4xx0 cp0 status register
279 */
280 #define ST0_IE 0x00000001
281 #define ST0_EXL 0x00000002
282 #define ST0_ERL 0x00000004
283 #define ST0_KSU 0x00000018
284 # define KSU_USER 0x00000010
285 # define KSU_SUPERVISOR 0x00000008
286 # define KSU_KERNEL 0x00000000
287 #define ST0_UX 0x00000020
288 #define ST0_SX 0x00000040
289 #define ST0_KX 0x00000080
290 #define ST0_DE 0x00010000
291 #define ST0_CE 0x00020000
292
293 /*
294 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
295 * cacheops in userspace. This bit exists only on RM7000 and RM9000
296 * processors.
297 */
298 #define ST0_CO 0x08000000
299
300 /*
301 * Bitfields in the R[23]000 cp0 status register.
302 */
303 #define ST0_IEC 0x00000001
304 #define ST0_KUC 0x00000002
305 #define ST0_IEP 0x00000004
306 #define ST0_KUP 0x00000008
307 #define ST0_IEO 0x00000010
308 #define ST0_KUO 0x00000020
309 /* bits 6 & 7 are reserved on R[23]000 */
310 #define ST0_ISC 0x00010000
311 #define ST0_SWC 0x00020000
312 #define ST0_CM 0x00080000
313
314 /*
315 * Bits specific to the R4640/R4650
316 */
317 #define ST0_UM (_ULCAST_(1) << 4)
318 #define ST0_IL (_ULCAST_(1) << 23)
319 #define ST0_DL (_ULCAST_(1) << 24)
320
321 /*
322 * Enable the MIPS MDMX and DSP ASEs
323 */
324 #define ST0_MX 0x01000000
325
326 /*
327 * Bitfields in the TX39 family CP0 Configuration Register 3
328 */
329 #define TX39_CONF_ICS_SHIFT 19
330 #define TX39_CONF_ICS_MASK 0x00380000
331 #define TX39_CONF_ICS_1KB 0x00000000
332 #define TX39_CONF_ICS_2KB 0x00080000
333 #define TX39_CONF_ICS_4KB 0x00100000
334 #define TX39_CONF_ICS_8KB 0x00180000
335 #define TX39_CONF_ICS_16KB 0x00200000
336
337 #define TX39_CONF_DCS_SHIFT 16
338 #define TX39_CONF_DCS_MASK 0x00070000
339 #define TX39_CONF_DCS_1KB 0x00000000
340 #define TX39_CONF_DCS_2KB 0x00010000
341 #define TX39_CONF_DCS_4KB 0x00020000
342 #define TX39_CONF_DCS_8KB 0x00030000
343 #define TX39_CONF_DCS_16KB 0x00040000
344
345 #define TX39_CONF_CWFON 0x00004000
346 #define TX39_CONF_WBON 0x00002000
347 #define TX39_CONF_RF_SHIFT 10
348 #define TX39_CONF_RF_MASK 0x00000c00
349 #define TX39_CONF_DOZE 0x00000200
350 #define TX39_CONF_HALT 0x00000100
351 #define TX39_CONF_LOCK 0x00000080
352 #define TX39_CONF_ICE 0x00000020
353 #define TX39_CONF_DCE 0x00000010
354 #define TX39_CONF_IRSIZE_SHIFT 2
355 #define TX39_CONF_IRSIZE_MASK 0x0000000c
356 #define TX39_CONF_DRSIZE_SHIFT 0
357 #define TX39_CONF_DRSIZE_MASK 0x00000003
358
359 /*
360 * Status register bits available in all MIPS CPUs.
361 */
362 #define ST0_IM 0x0000ff00
363 #define STATUSB_IP0 8
364 #define STATUSF_IP0 (_ULCAST_(1) << 8)
365 #define STATUSB_IP1 9
366 #define STATUSF_IP1 (_ULCAST_(1) << 9)
367 #define STATUSB_IP2 10
368 #define STATUSF_IP2 (_ULCAST_(1) << 10)
369 #define STATUSB_IP3 11
370 #define STATUSF_IP3 (_ULCAST_(1) << 11)
371 #define STATUSB_IP4 12
372 #define STATUSF_IP4 (_ULCAST_(1) << 12)
373 #define STATUSB_IP5 13
374 #define STATUSF_IP5 (_ULCAST_(1) << 13)
375 #define STATUSB_IP6 14
376 #define STATUSF_IP6 (_ULCAST_(1) << 14)
377 #define STATUSB_IP7 15
378 #define STATUSF_IP7 (_ULCAST_(1) << 15)
379 #define STATUSB_IP8 0
380 #define STATUSF_IP8 (_ULCAST_(1) << 0)
381 #define STATUSB_IP9 1
382 #define STATUSF_IP9 (_ULCAST_(1) << 1)
383 #define STATUSB_IP10 2
384 #define STATUSF_IP10 (_ULCAST_(1) << 2)
385 #define STATUSB_IP11 3
386 #define STATUSF_IP11 (_ULCAST_(1) << 3)
387 #define STATUSB_IP12 4
388 #define STATUSF_IP12 (_ULCAST_(1) << 4)
389 #define STATUSB_IP13 5
390 #define STATUSF_IP13 (_ULCAST_(1) << 5)
391 #define STATUSB_IP14 6
392 #define STATUSF_IP14 (_ULCAST_(1) << 6)
393 #define STATUSB_IP15 7
394 #define STATUSF_IP15 (_ULCAST_(1) << 7)
395 #define ST0_CH 0x00040000
396 #define ST0_SR 0x00100000
397 #define ST0_TS 0x00200000
398 #define ST0_BEV 0x00400000
399 #define ST0_RE 0x02000000
400 #define ST0_FR 0x04000000
401 #define ST0_CU 0xf0000000
402 #define ST0_CU0 0x10000000
403 #define ST0_CU1 0x20000000
404 #define ST0_CU2 0x40000000
405 #define ST0_CU3 0x80000000
406 #define ST0_XX 0x80000000 /* MIPS IV naming */
407
408 /*
409 * Bitfields and bit numbers in the coprocessor 0 cause register.
410 *
411 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
412 */
413 #define CAUSEB_EXCCODE 2
414 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
415 #define CAUSEB_IP 8
416 #define CAUSEF_IP (_ULCAST_(255) << 8)
417 #define CAUSEB_IP0 8
418 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
419 #define CAUSEB_IP1 9
420 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
421 #define CAUSEB_IP2 10
422 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
423 #define CAUSEB_IP3 11
424 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
425 #define CAUSEB_IP4 12
426 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
427 #define CAUSEB_IP5 13
428 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
429 #define CAUSEB_IP6 14
430 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
431 #define CAUSEB_IP7 15
432 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
433 #define CAUSEB_IV 23
434 #define CAUSEF_IV (_ULCAST_(1) << 23)
435 #define CAUSEB_CE 28
436 #define CAUSEF_CE (_ULCAST_(3) << 28)
437 #define CAUSEB_BD 31
438 #define CAUSEF_BD (_ULCAST_(1) << 31)
439
440 /*
441 * Bits in the coprocessor 0 config register.
442 */
443 /* Generic bits. */
444 #define CONF_CM_CACHABLE_NO_WA 0
445 #define CONF_CM_CACHABLE_WA 1
446 #define CONF_CM_UNCACHED 2
447 #define CONF_CM_CACHABLE_NONCOHERENT 3
448 #define CONF_CM_CACHABLE_CE 4
449 #define CONF_CM_CACHABLE_COW 5
450 #define CONF_CM_CACHABLE_CUW 6
451 #define CONF_CM_CACHABLE_ACCELERATED 7
452 #define CONF_CM_CMASK 7
453 #define CONF_BE (_ULCAST_(1) << 15)
454
455 /* Bits common to various processors. */
456 #define CONF_CU (_ULCAST_(1) << 3)
457 #define CONF_DB (_ULCAST_(1) << 4)
458 #define CONF_IB (_ULCAST_(1) << 5)
459 #define CONF_DC (_ULCAST_(7) << 6)
460 #define CONF_IC (_ULCAST_(7) << 9)
461 #define CONF_EB (_ULCAST_(1) << 13)
462 #define CONF_EM (_ULCAST_(1) << 14)
463 #define CONF_SM (_ULCAST_(1) << 16)
464 #define CONF_SC (_ULCAST_(1) << 17)
465 #define CONF_EW (_ULCAST_(3) << 18)
466 #define CONF_EP (_ULCAST_(15)<< 24)
467 #define CONF_EC (_ULCAST_(7) << 28)
468 #define CONF_CM (_ULCAST_(1) << 31)
469
470 /* Bits specific to the R4xx0. */
471 #define R4K_CONF_SW (_ULCAST_(1) << 20)
472 #define R4K_CONF_SS (_ULCAST_(1) << 21)
473 #define R4K_CONF_SB (_ULCAST_(3) << 22)
474
475 /* Bits specific to the R5000. */
476 #define R5K_CONF_SE (_ULCAST_(1) << 12)
477 #define R5K_CONF_SS (_ULCAST_(3) << 20)
478
479 /* Bits specific to the RM7000. */
480 #define RM7K_CONF_SE (_ULCAST_(1) << 3)
481 #define RM7K_CONF_TE (_ULCAST_(1) << 12)
482 #define RM7K_CONF_CLK (_ULCAST_(1) << 16)
483 #define RM7K_CONF_TC (_ULCAST_(1) << 17)
484 #define RM7K_CONF_SI (_ULCAST_(3) << 20)
485 #define RM7K_CONF_SC (_ULCAST_(1) << 31)
486
487 /* Bits specific to the R10000. */
488 #define R10K_CONF_DN (_ULCAST_(3) << 3)
489 #define R10K_CONF_CT (_ULCAST_(1) << 5)
490 #define R10K_CONF_PE (_ULCAST_(1) << 6)
491 #define R10K_CONF_PM (_ULCAST_(3) << 7)
492 #define R10K_CONF_EC (_ULCAST_(15)<< 9)
493 #define R10K_CONF_SB (_ULCAST_(1) << 13)
494 #define R10K_CONF_SK (_ULCAST_(1) << 14)
495 #define R10K_CONF_SS (_ULCAST_(7) << 16)
496 #define R10K_CONF_SC (_ULCAST_(7) << 19)
497 #define R10K_CONF_DC (_ULCAST_(7) << 26)
498 #define R10K_CONF_IC (_ULCAST_(7) << 29)
499
500 /* Bits specific to the VR41xx. */
501 #define VR41_CONF_CS (_ULCAST_(1) << 12)
502 #define VR41_CONF_P4K (_ULCAST_(1) << 13)
503 #define VR41_CONF_BP (_ULCAST_(1) << 16)
504 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
505 #define VR41_CONF_AD (_ULCAST_(1) << 23)
506
507 /* Bits specific to the R30xx. */
508 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
509 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
510 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
511 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
512 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
513 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
514 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
515 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
516 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
517
518 /* Bits specific to the TX49. */
519 #define TX49_CONF_DC (_ULCAST_(1) << 16)
520 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
521 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
522 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
523
524 /* Bits specific to the MIPS32/64 PRA. */
525 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
526 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
527 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
528 #define MIPS_CONF_M (_ULCAST_(1) << 31)
529
530 /*
531 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
532 */
533 #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
534 #define MIPS_CONF1_EP (_ULCAST_(1) << 1)
535 #define MIPS_CONF1_CA (_ULCAST_(1) << 2)
536 #define MIPS_CONF1_WR (_ULCAST_(1) << 3)
537 #define MIPS_CONF1_PC (_ULCAST_(1) << 4)
538 #define MIPS_CONF1_MD (_ULCAST_(1) << 5)
539 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
540 #define MIPS_CONF1_DA (_ULCAST_(7) << 7)
541 #define MIPS_CONF1_DL (_ULCAST_(7) << 10)
542 #define MIPS_CONF1_DS (_ULCAST_(7) << 13)
543 #define MIPS_CONF1_IA (_ULCAST_(7) << 16)
544 #define MIPS_CONF1_IL (_ULCAST_(7) << 19)
545 #define MIPS_CONF1_IS (_ULCAST_(7) << 22)
546 #define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
547
548 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
549 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
550 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
551 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
552 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
553 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
554 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
555 #define MIPS_CONF2_TU (_ULCAST_(7) << 28)
556
557 #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
558 #define MIPS_CONF3_SM (_ULCAST_(1) << 1)
559 #define MIPS_CONF3_MT (_ULCAST_(1) << 2)
560 #define MIPS_CONF3_SP (_ULCAST_(1) << 4)
561 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
562 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
563 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
564 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
565 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
566
567 #define MIPS_CONF7_WII (_ULCAST_(1) << 31)
568
569 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
570
571
572 /*
573 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
574 */
575 #define MIPS_FPIR_S (_ULCAST_(1) << 16)
576 #define MIPS_FPIR_D (_ULCAST_(1) << 17)
577 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
578 #define MIPS_FPIR_3D (_ULCAST_(1) << 19)
579 #define MIPS_FPIR_W (_ULCAST_(1) << 20)
580 #define MIPS_FPIR_L (_ULCAST_(1) << 21)
581 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
582
583 #ifndef __ASSEMBLY__
584
585 /*
586 * Functions to access the R10000 performance counters. These are basically
587 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
588 * performance counter number encoded into bits 1 ... 5 of the instruction.
589 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
590 * disassembler these will look like an access to sel 0 or 1.
591 */
592 #define read_r10k_perf_cntr(counter) \
593 ({ \
594 unsigned int __res; \
595 __asm__ __volatile__( \
596 "mfpc\t%0, %1" \
597 : "=r" (__res) \
598 : "i" (counter)); \
599 \
600 __res; \
601 })
602
603 #define write_r10k_perf_cntr(counter,val) \
604 do { \
605 __asm__ __volatile__( \
606 "mtpc\t%0, %1" \
607 : \
608 : "r" (val), "i" (counter)); \
609 } while (0)
610
611 #define read_r10k_perf_event(counter) \
612 ({ \
613 unsigned int __res; \
614 __asm__ __volatile__( \
615 "mfps\t%0, %1" \
616 : "=r" (__res) \
617 : "i" (counter)); \
618 \
619 __res; \
620 })
621
622 #define write_r10k_perf_cntl(counter,val) \
623 do { \
624 __asm__ __volatile__( \
625 "mtps\t%0, %1" \
626 : \
627 : "r" (val), "i" (counter)); \
628 } while (0)
629
630
631 /*
632 * Macros to access the system control coprocessor
633 */
634
635 #define __read_32bit_c0_register(source, sel) \
636 ({ int __res; \
637 if (sel == 0) \
638 __asm__ __volatile__( \
639 "mfc0\t%0, " #source "\n\t" \
640 : "=r" (__res)); \
641 else \
642 __asm__ __volatile__( \
643 ".set\tmips32\n\t" \
644 "mfc0\t%0, " #source ", " #sel "\n\t" \
645 ".set\tmips0\n\t" \
646 : "=r" (__res)); \
647 __res; \
648 })
649
650 #define __read_64bit_c0_register(source, sel) \
651 ({ unsigned long long __res; \
652 if (sizeof(unsigned long) == 4) \
653 __res = __read_64bit_c0_split(source, sel); \
654 else if (sel == 0) \
655 __asm__ __volatile__( \
656 ".set\tmips3\n\t" \
657 "dmfc0\t%0, " #source "\n\t" \
658 ".set\tmips0" \
659 : "=r" (__res)); \
660 else \
661 __asm__ __volatile__( \
662 ".set\tmips64\n\t" \
663 "dmfc0\t%0, " #source ", " #sel "\n\t" \
664 ".set\tmips0" \
665 : "=r" (__res)); \
666 __res; \
667 })
668
669 #define __write_32bit_c0_register(register, sel, value) \
670 do { \
671 if (sel == 0) \
672 __asm__ __volatile__( \
673 "mtc0\t%z0, " #register "\n\t" \
674 : : "Jr" ((unsigned int)(value))); \
675 else \
676 __asm__ __volatile__( \
677 ".set\tmips32\n\t" \
678 "mtc0\t%z0, " #register ", " #sel "\n\t" \
679 ".set\tmips0" \
680 : : "Jr" ((unsigned int)(value))); \
681 } while (0)
682
683 #define __write_64bit_c0_register(register, sel, value) \
684 do { \
685 if (sizeof(unsigned long) == 4) \
686 __write_64bit_c0_split(register, sel, value); \
687 else if (sel == 0) \
688 __asm__ __volatile__( \
689 ".set\tmips3\n\t" \
690 "dmtc0\t%z0, " #register "\n\t" \
691 ".set\tmips0" \
692 : : "Jr" (value)); \
693 else \
694 __asm__ __volatile__( \
695 ".set\tmips64\n\t" \
696 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
697 ".set\tmips0" \
698 : : "Jr" (value)); \
699 } while (0)
700
701 #define __read_ulong_c0_register(reg, sel) \
702 ((sizeof(unsigned long) == 4) ? \
703 (unsigned long) __read_32bit_c0_register(reg, sel) : \
704 (unsigned long) __read_64bit_c0_register(reg, sel))
705
706 #define __write_ulong_c0_register(reg, sel, val) \
707 do { \
708 if (sizeof(unsigned long) == 4) \
709 __write_32bit_c0_register(reg, sel, val); \
710 else \
711 __write_64bit_c0_register(reg, sel, val); \
712 } while (0)
713
714 /*
715 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
716 */
717 #define __read_32bit_c0_ctrl_register(source) \
718 ({ int __res; \
719 __asm__ __volatile__( \
720 "cfc0\t%0, " #source "\n\t" \
721 : "=r" (__res)); \
722 __res; \
723 })
724
725 #define __write_32bit_c0_ctrl_register(register, value) \
726 do { \
727 __asm__ __volatile__( \
728 "ctc0\t%z0, " #register "\n\t" \
729 : : "Jr" ((unsigned int)(value))); \
730 } while (0)
731
732 /*
733 * These versions are only needed for systems with more than 38 bits of
734 * physical address space running the 32-bit kernel. That's none atm :-)
735 */
736 #define __read_64bit_c0_split(source, sel) \
737 ({ \
738 unsigned long long __val; \
739 unsigned long __flags; \
740 \
741 local_irq_save(__flags); \
742 if (sel == 0) \
743 __asm__ __volatile__( \
744 ".set\tmips64\n\t" \
745 "dmfc0\t%M0, " #source "\n\t" \
746 "dsll\t%L0, %M0, 32\n\t" \
747 "dsra\t%M0, %M0, 32\n\t" \
748 "dsra\t%L0, %L0, 32\n\t" \
749 ".set\tmips0" \
750 : "=r" (__val)); \
751 else \
752 __asm__ __volatile__( \
753 ".set\tmips64\n\t" \
754 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
755 "dsll\t%L0, %M0, 32\n\t" \
756 "dsra\t%M0, %M0, 32\n\t" \
757 "dsra\t%L0, %L0, 32\n\t" \
758 ".set\tmips0" \
759 : "=r" (__val)); \
760 local_irq_restore(__flags); \
761 \
762 __val; \
763 })
764
765 #define __write_64bit_c0_split(source, sel, val) \
766 do { \
767 unsigned long __flags; \
768 \
769 local_irq_save(__flags); \
770 if (sel == 0) \
771 __asm__ __volatile__( \
772 ".set\tmips64\n\t" \
773 "dsll\t%L0, %L0, 32\n\t" \
774 "dsrl\t%L0, %L0, 32\n\t" \
775 "dsll\t%M0, %M0, 32\n\t" \
776 "or\t%L0, %L0, %M0\n\t" \
777 "dmtc0\t%L0, " #source "\n\t" \
778 ".set\tmips0" \
779 : : "r" (val)); \
780 else \
781 __asm__ __volatile__( \
782 ".set\tmips64\n\t" \
783 "dsll\t%L0, %L0, 32\n\t" \
784 "dsrl\t%L0, %L0, 32\n\t" \
785 "dsll\t%M0, %M0, 32\n\t" \
786 "or\t%L0, %L0, %M0\n\t" \
787 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
788 ".set\tmips0" \
789 : : "r" (val)); \
790 local_irq_restore(__flags); \
791 } while (0)
792
793 #define read_c0_index() __read_32bit_c0_register($0, 0)
794 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
795
796 #define read_c0_random() __read_32bit_c0_register($1, 0)
797 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
798
799 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
800 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
801
802 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
803 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
804
805 #define read_c0_conf() __read_32bit_c0_register($3, 0)
806 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
807
808 #define read_c0_context() __read_ulong_c0_register($4, 0)
809 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
810
811 #define read_c0_userlocal() __read_ulong_c0_register($4, 2)
812 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
813
814 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
815 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
816
817 #define read_c0_wired() __read_32bit_c0_register($6, 0)
818 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
819
820 #define read_c0_info() __read_32bit_c0_register($7, 0)
821
822 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
823 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
824
825 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
826 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
827
828 #define read_c0_count() __read_32bit_c0_register($9, 0)
829 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
830
831 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
832 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
833
834 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
835 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
836
837 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
838 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
839
840 #define read_c0_compare() __read_32bit_c0_register($11, 0)
841 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
842
843 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
844 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
845
846 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
847 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
848
849 #define read_c0_status() __read_32bit_c0_register($12, 0)
850 #ifdef CONFIG_MIPS_MT_SMTC
851 #define write_c0_status(val) \
852 do { \
853 __write_32bit_c0_register($12, 0, val); \
854 __ehb(); \
855 } while (0)
856 #else
857 /*
858 * Legacy non-SMTC code, which may be hazardous
859 * but which might not support EHB
860 */
861 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
862 #endif /* CONFIG_MIPS_MT_SMTC */
863
864 #define read_c0_cause() __read_32bit_c0_register($13, 0)
865 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
866
867 #define read_c0_epc() __read_ulong_c0_register($14, 0)
868 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
869
870 #define read_c0_prid() __read_32bit_c0_register($15, 0)
871
872 #define read_c0_config() __read_32bit_c0_register($16, 0)
873 #define read_c0_config1() __read_32bit_c0_register($16, 1)
874 #define read_c0_config2() __read_32bit_c0_register($16, 2)
875 #define read_c0_config3() __read_32bit_c0_register($16, 3)
876 #define read_c0_config4() __read_32bit_c0_register($16, 4)
877 #define read_c0_config5() __read_32bit_c0_register($16, 5)
878 #define read_c0_config6() __read_32bit_c0_register($16, 6)
879 #define read_c0_config7() __read_32bit_c0_register($16, 7)
880 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
881 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
882 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
883 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
884 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
885 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
886 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
887 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
888
889 /*
890 * The WatchLo register. There may be upto 8 of them.
891 */
892 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
893 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
894 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
895 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
896 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
897 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
898 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
899 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
900 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
901 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
902 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
903 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
904 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
905 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
906 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
907 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
908
909 /*
910 * The WatchHi register. There may be upto 8 of them.
911 */
912 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
913 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
914 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
915 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
916 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
917 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
918 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
919 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
920
921 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
922 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
923 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
924 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
925 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
926 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
927 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
928 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
929
930 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
931 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
932
933 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
934 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
935
936 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
937 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
938
939 /* RM9000 PerfControl performance counter control register */
940 #define read_c0_perfcontrol() __read_32bit_c0_register($22, 0)
941 #define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
942
943 #define read_c0_diag() __read_32bit_c0_register($22, 0)
944 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
945
946 #define read_c0_diag1() __read_32bit_c0_register($22, 1)
947 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
948
949 #define read_c0_diag2() __read_32bit_c0_register($22, 2)
950 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
951
952 #define read_c0_diag3() __read_32bit_c0_register($22, 3)
953 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
954
955 #define read_c0_diag4() __read_32bit_c0_register($22, 4)
956 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
957
958 #define read_c0_diag5() __read_32bit_c0_register($22, 5)
959 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
960
961 #define read_c0_debug() __read_32bit_c0_register($23, 0)
962 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
963
964 #define read_c0_depc() __read_ulong_c0_register($24, 0)
965 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
966
967 /*
968 * MIPS32 / MIPS64 performance counters
969 */
970 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
971 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
972 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
973 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
974 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
975 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
976 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
977 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
978 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
979 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
980 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
981 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
982 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
983 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
984 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
985 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
986
987 /* RM9000 PerfCount performance counter register */
988 #define read_c0_perfcount() __read_64bit_c0_register($25, 0)
989 #define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
990
991 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
992 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
993
994 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
995 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
996
997 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
998
999 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1000 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1001
1002 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
1003 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1004
1005 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1006 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1007
1008 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
1009 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1010
1011 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1012 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1013
1014 /* MIPSR2 */
1015 #define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1016 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1017
1018 #define read_c0_intctl() __read_32bit_c0_register($12, 1)
1019 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1020
1021 #define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1022 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1023
1024 #define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1025 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1026
1027 #define read_c0_ebase() __read_32bit_c0_register($15, 1)
1028 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1029
1030
1031 /* Cavium OCTEON (cnMIPS) */
1032 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1033 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1034
1035 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1036 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1037
1038 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1039 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1040 /*
1041 * The cacheerr registers are not standardized. On OCTEON, they are
1042 * 64 bits wide.
1043 */
1044 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1045 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1046
1047 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1048 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1049
1050 /*
1051 * Macros to access the floating point coprocessor control registers
1052 */
1053 #define read_32bit_cp1_register(source) \
1054 ({ int __res; \
1055 __asm__ __volatile__( \
1056 ".set\tpush\n\t" \
1057 ".set\treorder\n\t" \
1058 /* gas fails to assemble cfc1 for some archs (octeon).*/ \
1059 ".set\tmips1\n\t" \
1060 "cfc1\t%0,"STR(source)"\n\t" \
1061 ".set\tpop" \
1062 : "=r" (__res)); \
1063 __res;})
1064
1065 #define rddsp(mask) \
1066 ({ \
1067 unsigned int __res; \
1068 \
1069 __asm__ __volatile__( \
1070 " .set push \n" \
1071 " .set noat \n" \
1072 " # rddsp $1, %x1 \n" \
1073 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1074 " move %0, $1 \n" \
1075 " .set pop \n" \
1076 : "=r" (__res) \
1077 : "i" (mask)); \
1078 __res; \
1079 })
1080
1081 #define wrdsp(val, mask) \
1082 do { \
1083 __asm__ __volatile__( \
1084 " .set push \n" \
1085 " .set noat \n" \
1086 " move $1, %0 \n" \
1087 " # wrdsp $1, %x1 \n" \
1088 " .word 0x7c2004f8 | (%x1 << 11) \n" \
1089 " .set pop \n" \
1090 : \
1091 : "r" (val), "i" (mask)); \
1092 } while (0)
1093
1094 #if 0 /* Need DSP ASE capable assembler ... */
1095 #define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
1096 #define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
1097 #define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
1098 #define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
1099
1100 #define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
1101 #define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
1102 #define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
1103 #define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
1104
1105 #define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
1106 #define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
1107 #define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
1108 #define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
1109
1110 #define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
1111 #define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
1112 #define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
1113 #define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
1114
1115 #else
1116
1117 #define mfhi0() \
1118 ({ \
1119 unsigned long __treg; \
1120 \
1121 __asm__ __volatile__( \
1122 " .set push \n" \
1123 " .set noat \n" \
1124 " # mfhi %0, $ac0 \n" \
1125 " .word 0x00000810 \n" \
1126 " move %0, $1 \n" \
1127 " .set pop \n" \
1128 : "=r" (__treg)); \
1129 __treg; \
1130 })
1131
1132 #define mfhi1() \
1133 ({ \
1134 unsigned long __treg; \
1135 \
1136 __asm__ __volatile__( \
1137 " .set push \n" \
1138 " .set noat \n" \
1139 " # mfhi %0, $ac1 \n" \
1140 " .word 0x00200810 \n" \
1141 " move %0, $1 \n" \
1142 " .set pop \n" \
1143 : "=r" (__treg)); \
1144 __treg; \
1145 })
1146
1147 #define mfhi2() \
1148 ({ \
1149 unsigned long __treg; \
1150 \
1151 __asm__ __volatile__( \
1152 " .set push \n" \
1153 " .set noat \n" \
1154 " # mfhi %0, $ac2 \n" \
1155 " .word 0x00400810 \n" \
1156 " move %0, $1 \n" \
1157 " .set pop \n" \
1158 : "=r" (__treg)); \
1159 __treg; \
1160 })
1161
1162 #define mfhi3() \
1163 ({ \
1164 unsigned long __treg; \
1165 \
1166 __asm__ __volatile__( \
1167 " .set push \n" \
1168 " .set noat \n" \
1169 " # mfhi %0, $ac3 \n" \
1170 " .word 0x00600810 \n" \
1171 " move %0, $1 \n" \
1172 " .set pop \n" \
1173 : "=r" (__treg)); \
1174 __treg; \
1175 })
1176
1177 #define mflo0() \
1178 ({ \
1179 unsigned long __treg; \
1180 \
1181 __asm__ __volatile__( \
1182 " .set push \n" \
1183 " .set noat \n" \
1184 " # mflo %0, $ac0 \n" \
1185 " .word 0x00000812 \n" \
1186 " move %0, $1 \n" \
1187 " .set pop \n" \
1188 : "=r" (__treg)); \
1189 __treg; \
1190 })
1191
1192 #define mflo1() \
1193 ({ \
1194 unsigned long __treg; \
1195 \
1196 __asm__ __volatile__( \
1197 " .set push \n" \
1198 " .set noat \n" \
1199 " # mflo %0, $ac1 \n" \
1200 " .word 0x00200812 \n" \
1201 " move %0, $1 \n" \
1202 " .set pop \n" \
1203 : "=r" (__treg)); \
1204 __treg; \
1205 })
1206
1207 #define mflo2() \
1208 ({ \
1209 unsigned long __treg; \
1210 \
1211 __asm__ __volatile__( \
1212 " .set push \n" \
1213 " .set noat \n" \
1214 " # mflo %0, $ac2 \n" \
1215 " .word 0x00400812 \n" \
1216 " move %0, $1 \n" \
1217 " .set pop \n" \
1218 : "=r" (__treg)); \
1219 __treg; \
1220 })
1221
1222 #define mflo3() \
1223 ({ \
1224 unsigned long __treg; \
1225 \
1226 __asm__ __volatile__( \
1227 " .set push \n" \
1228 " .set noat \n" \
1229 " # mflo %0, $ac3 \n" \
1230 " .word 0x00600812 \n" \
1231 " move %0, $1 \n" \
1232 " .set pop \n" \
1233 : "=r" (__treg)); \
1234 __treg; \
1235 })
1236
1237 #define mthi0(x) \
1238 do { \
1239 __asm__ __volatile__( \
1240 " .set push \n" \
1241 " .set noat \n" \
1242 " move $1, %0 \n" \
1243 " # mthi $1, $ac0 \n" \
1244 " .word 0x00200011 \n" \
1245 " .set pop \n" \
1246 : \
1247 : "r" (x)); \
1248 } while (0)
1249
1250 #define mthi1(x) \
1251 do { \
1252 __asm__ __volatile__( \
1253 " .set push \n" \
1254 " .set noat \n" \
1255 " move $1, %0 \n" \
1256 " # mthi $1, $ac1 \n" \
1257 " .word 0x00200811 \n" \
1258 " .set pop \n" \
1259 : \
1260 : "r" (x)); \
1261 } while (0)
1262
1263 #define mthi2(x) \
1264 do { \
1265 __asm__ __volatile__( \
1266 " .set push \n" \
1267 " .set noat \n" \
1268 " move $1, %0 \n" \
1269 " # mthi $1, $ac2 \n" \
1270 " .word 0x00201011 \n" \
1271 " .set pop \n" \
1272 : \
1273 : "r" (x)); \
1274 } while (0)
1275
1276 #define mthi3(x) \
1277 do { \
1278 __asm__ __volatile__( \
1279 " .set push \n" \
1280 " .set noat \n" \
1281 " move $1, %0 \n" \
1282 " # mthi $1, $ac3 \n" \
1283 " .word 0x00201811 \n" \
1284 " .set pop \n" \
1285 : \
1286 : "r" (x)); \
1287 } while (0)
1288
1289 #define mtlo0(x) \
1290 do { \
1291 __asm__ __volatile__( \
1292 " .set push \n" \
1293 " .set noat \n" \
1294 " move $1, %0 \n" \
1295 " # mtlo $1, $ac0 \n" \
1296 " .word 0x00200013 \n" \
1297 " .set pop \n" \
1298 : \
1299 : "r" (x)); \
1300 } while (0)
1301
1302 #define mtlo1(x) \
1303 do { \
1304 __asm__ __volatile__( \
1305 " .set push \n" \
1306 " .set noat \n" \
1307 " move $1, %0 \n" \
1308 " # mtlo $1, $ac1 \n" \
1309 " .word 0x00200813 \n" \
1310 " .set pop \n" \
1311 : \
1312 : "r" (x)); \
1313 } while (0)
1314
1315 #define mtlo2(x) \
1316 do { \
1317 __asm__ __volatile__( \
1318 " .set push \n" \
1319 " .set noat \n" \
1320 " move $1, %0 \n" \
1321 " # mtlo $1, $ac2 \n" \
1322 " .word 0x00201013 \n" \
1323 " .set pop \n" \
1324 : \
1325 : "r" (x)); \
1326 } while (0)
1327
1328 #define mtlo3(x) \
1329 do { \
1330 __asm__ __volatile__( \
1331 " .set push \n" \
1332 " .set noat \n" \
1333 " move $1, %0 \n" \
1334 " # mtlo $1, $ac3 \n" \
1335 " .word 0x00201813 \n" \
1336 " .set pop \n" \
1337 : \
1338 : "r" (x)); \
1339 } while (0)
1340
1341 #endif
1342
1343 /*
1344 * TLB operations.
1345 *
1346 * It is responsibility of the caller to take care of any TLB hazards.
1347 */
1348 static inline void tlb_probe(void)
1349 {
1350 __asm__ __volatile__(
1351 ".set noreorder\n\t"
1352 "tlbp\n\t"
1353 ".set reorder");
1354 }
1355
1356 static inline void tlb_read(void)
1357 {
1358 #if MIPS34K_MISSED_ITLB_WAR
1359 int res = 0;
1360
1361 __asm__ __volatile__(
1362 " .set push \n"
1363 " .set noreorder \n"
1364 " .set noat \n"
1365 " .set mips32r2 \n"
1366 " .word 0x41610001 # dvpe $1 \n"
1367 " move %0, $1 \n"
1368 " ehb \n"
1369 " .set pop \n"
1370 : "=r" (res));
1371
1372 instruction_hazard();
1373 #endif
1374
1375 __asm__ __volatile__(
1376 ".set noreorder\n\t"
1377 "tlbr\n\t"
1378 ".set reorder");
1379
1380 #if MIPS34K_MISSED_ITLB_WAR
1381 if ((res & _ULCAST_(1)))
1382 __asm__ __volatile__(
1383 " .set push \n"
1384 " .set noreorder \n"
1385 " .set noat \n"
1386 " .set mips32r2 \n"
1387 " .word 0x41600021 # evpe \n"
1388 " ehb \n"
1389 " .set pop \n");
1390 #endif
1391 }
1392
1393 static inline void tlb_write_indexed(void)
1394 {
1395 __asm__ __volatile__(
1396 ".set noreorder\n\t"
1397 "tlbwi\n\t"
1398 ".set reorder");
1399 }
1400
1401 static inline void tlb_write_random(void)
1402 {
1403 __asm__ __volatile__(
1404 ".set noreorder\n\t"
1405 "tlbwr\n\t"
1406 ".set reorder");
1407 }
1408
1409 /*
1410 * Manipulate bits in a c0 register.
1411 */
1412 #ifndef CONFIG_MIPS_MT_SMTC
1413 /*
1414 * SMTC Linux requires shutting-down microthread scheduling
1415 * during CP0 register read-modify-write sequences.
1416 */
1417 #define __BUILD_SET_C0(name) \
1418 static inline unsigned int \
1419 set_c0_##name(unsigned int set) \
1420 { \
1421 unsigned int res, new; \
1422 \
1423 res = read_c0_##name(); \
1424 new = res | set; \
1425 write_c0_##name(new); \
1426 \
1427 return res; \
1428 } \
1429 \
1430 static inline unsigned int \
1431 clear_c0_##name(unsigned int clear) \
1432 { \
1433 unsigned int res, new; \
1434 \
1435 res = read_c0_##name(); \
1436 new = res & ~clear; \
1437 write_c0_##name(new); \
1438 \
1439 return res; \
1440 } \
1441 \
1442 static inline unsigned int \
1443 change_c0_##name(unsigned int change, unsigned int val) \
1444 { \
1445 unsigned int res, new; \
1446 \
1447 res = read_c0_##name(); \
1448 new = res & ~change; \
1449 new |= (val & change); \
1450 write_c0_##name(new); \
1451 \
1452 return res; \
1453 }
1454
1455 #else /* SMTC versions that manage MT scheduling */
1456
1457 #include <linux/irqflags.h>
1458
1459 /*
1460 * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with
1461 * header file recursion.
1462 */
1463 static inline unsigned int __dmt(void)
1464 {
1465 int res;
1466
1467 __asm__ __volatile__(
1468 " .set push \n"
1469 " .set mips32r2 \n"
1470 " .set noat \n"
1471 " .word 0x41610BC1 # dmt $1 \n"
1472 " ehb \n"
1473 " move %0, $1 \n"
1474 " .set pop \n"
1475 : "=r" (res));
1476
1477 instruction_hazard();
1478
1479 return res;
1480 }
1481
1482 #define __VPECONTROL_TE_SHIFT 15
1483 #define __VPECONTROL_TE (1UL << __VPECONTROL_TE_SHIFT)
1484
1485 #define __EMT_ENABLE __VPECONTROL_TE
1486
1487 static inline void __emt(unsigned int previous)
1488 {
1489 if ((previous & __EMT_ENABLE))
1490 __asm__ __volatile__(
1491 " .set mips32r2 \n"
1492 " .word 0x41600be1 # emt \n"
1493 " ehb \n"
1494 " .set mips0 \n");
1495 }
1496
1497 static inline void __ehb(void)
1498 {
1499 __asm__ __volatile__(
1500 " .set mips32r2 \n"
1501 " ehb \n" " .set mips0 \n");
1502 }
1503
1504 /*
1505 * Note that local_irq_save/restore affect TC-specific IXMT state,
1506 * not Status.IE as in non-SMTC kernel.
1507 */
1508
1509 #define __BUILD_SET_C0(name) \
1510 static inline unsigned int \
1511 set_c0_##name(unsigned int set) \
1512 { \
1513 unsigned int res; \
1514 unsigned int new; \
1515 unsigned int omt; \
1516 unsigned long flags; \
1517 \
1518 local_irq_save(flags); \
1519 omt = __dmt(); \
1520 res = read_c0_##name(); \
1521 new = res | set; \
1522 write_c0_##name(new); \
1523 __emt(omt); \
1524 local_irq_restore(flags); \
1525 \
1526 return res; \
1527 } \
1528 \
1529 static inline unsigned int \
1530 clear_c0_##name(unsigned int clear) \
1531 { \
1532 unsigned int res; \
1533 unsigned int new; \
1534 unsigned int omt; \
1535 unsigned long flags; \
1536 \
1537 local_irq_save(flags); \
1538 omt = __dmt(); \
1539 res = read_c0_##name(); \
1540 new = res & ~clear; \
1541 write_c0_##name(new); \
1542 __emt(omt); \
1543 local_irq_restore(flags); \
1544 \
1545 return res; \
1546 } \
1547 \
1548 static inline unsigned int \
1549 change_c0_##name(unsigned int change, unsigned int newbits) \
1550 { \
1551 unsigned int res; \
1552 unsigned int new; \
1553 unsigned int omt; \
1554 unsigned long flags; \
1555 \
1556 local_irq_save(flags); \
1557 \
1558 omt = __dmt(); \
1559 res = read_c0_##name(); \
1560 new = res & ~change; \
1561 new |= (newbits & change); \
1562 write_c0_##name(new); \
1563 __emt(omt); \
1564 local_irq_restore(flags); \
1565 \
1566 return res; \
1567 }
1568 #endif
1569
1570 __BUILD_SET_C0(status)
1571 __BUILD_SET_C0(cause)
1572 __BUILD_SET_C0(config)
1573 __BUILD_SET_C0(intcontrol)
1574 __BUILD_SET_C0(intctl)
1575 __BUILD_SET_C0(srsmap)
1576
1577 #endif /* !__ASSEMBLY__ */
1578
1579 #endif /* _ASM_MIPSREGS_H */
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