arch/blackfin/mach-bf537/include/mach/bf537.h

   1 /*
   2  * System MMR Register and memory map for ADSP-BF537
   3  *
   4  * Copyright 2005-2008 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #ifndef __MACH_BF537_H__
  10 #define __MACH_BF537_H__
  11
  12 /* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */
  13
  14 #define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE)        /* SPI_STAT */
  15 #define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF)      /* SPORTx_STAT */
  16 #define PPI_ERR_MASK (0xFFFF & ~FLD)    /* PPI_STATUS */
  17 #define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE)   /* EMAC_SYSTAT */
  18 #define UART_ERR_MASK_STAT1 (0x4)       /* UARTx_IIR */
  19 #define UART_ERR_MASK_STAT0 (0x2)       /* UARTx_IIR */
  20 #define CAN_ERR_MASK  (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF)        /* CAN_GIF */
  21
  22 #define OFFSET_(x) ((x) & 0x0000FFFF)
  23
  24 /*some misc defines*/
  25 #define IMASK_IVG15             0x8000
  26 #define IMASK_IVG14             0x4000
  27 #define IMASK_IVG13             0x2000
  28 #define IMASK_IVG12             0x1000
  29
  30 #define IMASK_IVG11             0x0800
  31 #define IMASK_IVG10             0x0400
  32 #define IMASK_IVG9              0x0200
  33 #define IMASK_IVG8              0x0100
  34
  35 #define IMASK_IVG7              0x0080
  36 #define IMASK_IVGTMR    0x0040
  37 #define IMASK_IVGHW             0x0020
  38
  39 /***************************/
  40
  41
  42 #define BFIN_DSUBBANKS  4
  43 #define BFIN_DWAYS              2
  44 #define BFIN_DLINES             64
  45 #define BFIN_ISUBBANKS  4
  46 #define BFIN_IWAYS              4
  47 #define BFIN_ILINES             32
  48
  49 #define WAY0_L                  0x1
  50 #define WAY1_L                  0x2
  51 #define WAY01_L                 0x3
  52 #define WAY2_L                  0x4
  53 #define WAY02_L                 0x5
  54 #define WAY12_L                 0x6
  55 #define WAY012_L                0x7
  56
  57 #define WAY3_L                  0x8
  58 #define WAY03_L                 0x9
  59 #define WAY13_L                 0xA
  60 #define WAY013_L                0xB
  61
  62 #define WAY32_L                 0xC
  63 #define WAY320_L                0xD
  64 #define WAY321_L                0xE
  65 #define WAYALL_L                0xF
  66
  67 #define DMC_ENABLE (2<<2)       /*yes, 2, not 1 */
  68
  69 /********************************* EBIU Settings ************************************/
  70 #define AMBCTL0VAL      ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
  71 #define AMBCTL1VAL      ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
  72
  73 #ifdef CONFIG_C_AMBEN_ALL
  74 #define V_AMBEN AMBEN_ALL
  75 #endif
  76 #ifdef CONFIG_C_AMBEN
  77 #define V_AMBEN 0x0
  78 #endif
  79 #ifdef CONFIG_C_AMBEN_B0
  80 #define V_AMBEN AMBEN_B0
  81 #endif
  82 #ifdef CONFIG_C_AMBEN_B0_B1
  83 #define V_AMBEN AMBEN_B0_B1
  84 #endif
  85 #ifdef CONFIG_C_AMBEN_B0_B1_B2
  86 #define V_AMBEN AMBEN_B0_B1_B2
  87 #endif
  88 #ifdef CONFIG_C_AMCKEN
  89 #define V_AMCKEN AMCKEN
  90 #else
  91 #define V_AMCKEN 0x0
  92 #endif
  93 #ifdef CONFIG_C_CDPRIO
  94 #define V_CDPRIO 0x100
  95 #else
  96 #define V_CDPRIO 0x0
  97 #endif
  98
  99 #define AMGCTLVAL       (V_AMBEN | V_AMCKEN | V_CDPRIO)
 100
 101 #ifdef CONFIG_BF537
 102 #define CPU "BF537"
 103 #define CPUID 0x27c8
 104 #endif
 105 #ifdef CONFIG_BF536
 106 #define CPU "BF536"
 107 #define CPUID 0x27c8
 108 #endif
 109 #ifdef CONFIG_BF534
 110 #define CPU "BF534"
 111 #define CPUID 0x27c6
 112 #endif
 113
 114 #ifndef CPU
 115 #error "Unknown CPU type - This kernel doesn't seem to be configured properly"
 116 #endif
 117
 118 #endif                          /* __MACH_BF537_H__  */