arch/blackfin/mach-bf537/include/mach/blackfin.h

   1 /*
   2  * Copyright 2005-2009 Analog Devices Inc.
   3  *
   4  * Licensed under the GPL-2 or later
   5  */
   6
   7 #ifndef _MACH_BLACKFIN_H_
   8 #define _MACH_BLACKFIN_H_
   9
  10 #define BF537_FAMILY
  11
  12 #include "bf537.h"
  13 #include "defBF534.h"
  14 #include "anomaly.h"
  15
  16 #if defined(CONFIG_BF537) || defined(CONFIG_BF536)
  17 #include "defBF537.h"
  18 #endif
  19
  20 #if !defined(__ASSEMBLY__)
  21 #include "cdefBF534.h"
  22
  23 #if defined(CONFIG_BF537) || defined(CONFIG_BF536)
  24 #include "cdefBF537.h"
  25 #endif
  26 #endif
  27
  28 #define BFIN_UART_NR_PORTS      2
  29
  30 #define OFFSET_THR              0x00    /* Transmit Holding register            */
  31 #define OFFSET_RBR              0x00    /* Receive Buffer register              */
  32 #define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
  33 #define OFFSET_IER              0x04    /* Interrupt Enable Register            */
  34 #define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
  35 #define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
  36 #define OFFSET_LCR              0x0C    /* Line Control Register                */
  37 #define OFFSET_MCR              0x10    /* Modem Control Register               */
  38 #define OFFSET_LSR              0x14    /* Line Status Register                 */
  39 #define OFFSET_MSR              0x18    /* Modem Status Register                */
  40 #define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
  41 #define OFFSET_GCTL             0x24    /* Global Control Register              */
  42
  43 /* PLL_DIV Masks                                                                                                        */
  44 #define CCLK_DIV1 CSEL_DIV1     /*          CCLK = VCO / 1                                  */
  45 #define CCLK_DIV2 CSEL_DIV2     /*          CCLK = VCO / 2                                  */
  46 #define CCLK_DIV4 CSEL_DIV4     /*          CCLK = VCO / 4                                  */
  47 #define CCLK_DIV8 CSEL_DIV8     /*          CCLK = VCO / 8                                  */
  48
  49 #endif