arch/x86/include/asm/geode.h

   1 /*
   2  * AMD Geode definitions
   3  * Copyright (C) 2006, Advanced Micro Devices, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of version 2 of the GNU General Public License
   7  * as published by the Free Software Foundation.
   8  */
   9
  10 #ifndef _ASM_X86_GEODE_H
  11 #define _ASM_X86_GEODE_H
  12
  13 #include <asm/processor.h>
  14 #include <linux/io.h>
  15 #include <linux/cs5535.h>
  16
  17 /* Generic southbridge functions */
  18
  19 #define GEODE_DEV_PMS 0
  20 #define GEODE_DEV_ACPI 1
  21 #define GEODE_DEV_GPIO 2
  22 #define GEODE_DEV_MFGPT 3
  23
  24 extern int geode_get_dev_base(unsigned int dev);
  25
  26 /* Useful macros */
  27 #define geode_pms_base()        geode_get_dev_base(GEODE_DEV_PMS)
  28 #define geode_acpi_base()       geode_get_dev_base(GEODE_DEV_ACPI)
  29 #define geode_gpio_base()       geode_get_dev_base(GEODE_DEV_GPIO)
  30 #define geode_mfgpt_base()      geode_get_dev_base(GEODE_DEV_MFGPT)
  31
  32 /* MSRS */
  33
  34 #define MSR_GLIU_P2D_RO0        0x10000029
  35
  36 #define MSR_LX_GLD_MSR_CONFIG   0x48002001
  37 #define MSR_LX_MSR_PADSEL       0x48002011      /* NOT 0x48000011; the data
  38                                                  * sheet has the wrong value */
  39 #define MSR_GLCP_SYS_RSTPLL     0x4C000014
  40 #define MSR_GLCP_DOTPLL         0x4C000015
  41
  42 #define MSR_LBAR_SMB            0x5140000B
  43 #define MSR_LBAR_GPIO           0x5140000C
  44 #define MSR_LBAR_MFGPT          0x5140000D
  45 #define MSR_LBAR_ACPI           0x5140000E
  46 #define MSR_LBAR_PMS            0x5140000F
  47
  48 #define MSR_DIVIL_SOFT_RESET    0x51400017
  49
  50 #define MSR_PIC_YSEL_LOW        0x51400020
  51 #define MSR_PIC_YSEL_HIGH       0x51400021
  52 #define MSR_PIC_ZSEL_LOW        0x51400022
  53 #define MSR_PIC_ZSEL_HIGH       0x51400023
  54 #define MSR_PIC_IRQM_LPC        0x51400025
  55
  56 #define MSR_MFGPT_IRQ           0x51400028
  57 #define MSR_MFGPT_NR            0x51400029
  58 #define MSR_MFGPT_SETUP         0x5140002B
  59
  60 #define MSR_LX_SPARE_MSR        0x80000011      /* DC-specific */
  61
  62 #define MSR_GX_GLD_MSR_CONFIG   0xC0002001
  63 #define MSR_GX_MSR_PADSEL       0xC0002011
  64
  65 /* Resource Sizes */
  66
  67 #define LBAR_GPIO_SIZE          0xFF
  68 #define LBAR_MFGPT_SIZE         0x40
  69 #define LBAR_ACPI_SIZE          0x40
  70 #define LBAR_PMS_SIZE           0x80
  71
  72 /* ACPI registers (PMS block) */
  73
  74 /*
  75  * PM1_EN is only valid when VSA is enabled for 16 bit reads.
  76  * When VSA is not enabled, *always* read both PM1_STS and PM1_EN
  77  * with a 32 bit read at offset 0x0
  78  */
  79
  80 #define PM1_STS                 0x00
  81 #define PM1_EN                  0x02
  82 #define PM1_CNT                 0x08
  83 #define PM2_CNT                 0x0C
  84 #define PM_TMR                  0x10
  85 #define PM_GPE0_STS             0x18
  86 #define PM_GPE0_EN              0x1C
  87
  88 /* PMC registers (PMS block) */
  89
  90 #define PM_SSD                  0x00
  91 #define PM_SCXA                 0x04
  92 #define PM_SCYA                 0x08
  93 #define PM_OUT_SLPCTL           0x0C
  94 #define PM_SCLK                 0x10
  95 #define PM_SED                  0x1
  96 #define PM_SCXD                 0x18
  97 #define PM_SCYD                 0x1C
  98 #define PM_IN_SLPCTL            0x20
  99 #define PM_WKD                  0x30
 100 #define PM_WKXD                 0x34
 101 #define PM_RD                   0x38
 102 #define PM_WKXA                 0x3C
 103 #define PM_FSD                  0x40
 104 #define PM_TSD                  0x44
 105 #define PM_PSD                  0x48
 106 #define PM_NWKD                 0x4C
 107 #define PM_AWKD                 0x50
 108 #define PM_SSC                  0x54
 109
 110 /* VSA2 magic values */
 111
 112 #define VSA_VRC_INDEX           0xAC1C
 113 #define VSA_VRC_DATA            0xAC1E
 114 #define VSA_VR_UNLOCK           0xFC53  /* unlock virtual register */
 115 #define VSA_VR_SIGNATURE        0x0003
 116 #define VSA_VR_MEM_SIZE         0x0200
 117 #define AMD_VSA_SIG             0x4132  /* signature is ascii 'VSA2' */
 118 #define GSW_VSA_SIG             0x534d  /* General Software signature */
 119
 120 static inline u32 geode_gpio(unsigned int nr)
 121 {
 122         BUG_ON(nr > 28);
 123         return 1 << nr;
 124 }
 125
 126 extern void geode_gpio_set(u32, unsigned int);
 127 extern void geode_gpio_clear(u32, unsigned int);
 128 extern int geode_gpio_isset(u32, unsigned int);
 129 extern void geode_gpio_setup_event(unsigned int, int, int);
 130 extern void geode_gpio_set_irq(unsigned int, unsigned int);
 131
 132 static inline void geode_gpio_event_irq(unsigned int gpio, int pair)
 133 {
 134         geode_gpio_setup_event(gpio, pair, 0);
 135 }
 136
 137 static inline void geode_gpio_event_pme(unsigned int gpio, int pair)
 138 {
 139         geode_gpio_setup_event(gpio, pair, 1);
 140 }
 141
 142 /* Specific geode tests */
 143
 144 static inline int is_geode_gx(void)
 145 {
 146         return ((boot_cpu_data.x86_vendor == X86_VENDOR_NSC) &&
 147                 (boot_cpu_data.x86 == 5) &&
 148                 (boot_cpu_data.x86_model == 5));
 149 }
 150
 151 static inline int is_geode_lx(void)
 152 {
 153         return ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
 154                 (boot_cpu_data.x86 == 5) &&
 155                 (boot_cpu_data.x86_model == 10));
 156 }
 157
 158 static inline int is_geode(void)
 159 {
 160         return (is_geode_gx() || is_geode_lx());
 161 }
 162
 163 #ifdef CONFIG_MGEODE_LX
 164 extern int geode_has_vsa2(void);
 165 #else
 166 static inline int geode_has_vsa2(void)
 167 {
 168         return 0;
 169 }
 170 #endif
 171
 172 /* MFGPTs */
 173
 174 #define MFGPT_MAX_TIMERS        8
 175 #define MFGPT_TIMER_ANY         (-1)
 176
 177 #define MFGPT_DOMAIN_WORKING    1
 178 #define MFGPT_DOMAIN_STANDBY    2
 179 #define MFGPT_DOMAIN_ANY        (MFGPT_DOMAIN_WORKING | MFGPT_DOMAIN_STANDBY)
 180
 181 #define MFGPT_CMP1              0
 182 #define MFGPT_CMP2              1
 183
 184 #define MFGPT_EVENT_IRQ         0
 185 #define MFGPT_EVENT_NMI         1
 186 #define MFGPT_EVENT_RESET       3
 187
 188 #define MFGPT_REG_CMP1          0
 189 #define MFGPT_REG_CMP2          2
 190 #define MFGPT_REG_COUNTER       4
 191 #define MFGPT_REG_SETUP         6
 192
 193 #define MFGPT_SETUP_CNTEN       (1 << 15)
 194 #define MFGPT_SETUP_CMP2        (1 << 14)
 195 #define MFGPT_SETUP_CMP1        (1 << 13)
 196 #define MFGPT_SETUP_SETUP       (1 << 12)
 197 #define MFGPT_SETUP_STOPEN      (1 << 11)
 198 #define MFGPT_SETUP_EXTEN       (1 << 10)
 199 #define MFGPT_SETUP_REVEN       (1 << 5)
 200 #define MFGPT_SETUP_CLKSEL      (1 << 4)
 201
 202 static inline void geode_mfgpt_write(int timer, u16 reg, u16 value)
 203 {
 204         u32 base = geode_get_dev_base(GEODE_DEV_MFGPT);
 205         outw(value, base + reg + (timer * 8));
 206 }
 207
 208 static inline u16 geode_mfgpt_read(int timer, u16 reg)
 209 {
 210         u32 base = geode_get_dev_base(GEODE_DEV_MFGPT);
 211         return inw(base + reg + (timer * 8));
 212 }
 213
 214 extern int geode_mfgpt_toggle_event(int timer, int cmp, int event, int enable);
 215 extern int geode_mfgpt_set_irq(int timer, int cmp, int *irq, int enable);
 216 extern int geode_mfgpt_alloc_timer(int timer, int domain);
 217
 218 #define geode_mfgpt_setup_irq(t, c, i) geode_mfgpt_set_irq((t), (c), (i), 1)
 219 #define geode_mfgpt_release_irq(t, c, i) geode_mfgpt_set_irq((t), (c), (i), 0)
 220
 221 #ifdef CONFIG_GEODE_MFGPT_TIMER
 222 extern int __init mfgpt_timer_setup(void);
 223 #else
 224 static inline int mfgpt_timer_setup(void) { return 0; }
 225 #endif
 226
 227 #endif /* _ASM_X86_GEODE_H */