3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
10 * Dor Laor <dor.laor@qumranet.com>
11 * Gregory Haskins <ghaskins@novell.com>
12 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
20 #include <linux/kvm_host.h>
21 #include <linux/kvm.h>
23 #include <linux/highmem.h>
24 #include <linux/smp.h>
25 #include <linux/hrtimer.h>
27 #include <linux/module.h>
28 #include <linux/math64.h>
29 #include <asm/processor.h>
32 #include <asm/current.h>
33 #include <asm/apicdef.h>
34 #include <asm/atomic.h>
35 #include "kvm_cache_regs.h"
41 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
43 #define mod_64(x, y) ((x) % (y))
51 #define APIC_BUS_CYCLE_NS 1
53 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
54 #define apic_debug(fmt, arg...)
56 #define APIC_LVT_NUM 6
57 /* 14 is the version for Xeon and Pentium 8.4.8*/
58 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
59 #define LAPIC_MMIO_LENGTH (1 << 12)
60 /* followed define is not in apicdef.h */
61 #define APIC_SHORT_MASK 0xc0000
62 #define APIC_DEST_NOSHORT 0x0
63 #define APIC_DEST_MASK 0x800
64 #define MAX_APIC_VECTOR 256
66 #define VEC_POS(v) ((v) & (32 - 1))
67 #define REG_POS(v) (((v) >> 5) << 4)
69 static inline u32
apic_get_reg(struct kvm_lapic
*apic
, int reg_off
)
71 return *((u32
*) (apic
->regs
+ reg_off
));
74 static inline void apic_set_reg(struct kvm_lapic
*apic
, int reg_off
, u32 val
)
76 *((u32
*) (apic
->regs
+ reg_off
)) = val
;
79 static inline int apic_test_and_set_vector(int vec
, void *bitmap
)
81 return test_and_set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
84 static inline int apic_test_and_clear_vector(int vec
, void *bitmap
)
86 return test_and_clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
89 static inline void apic_set_vector(int vec
, void *bitmap
)
91 set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
94 static inline void apic_clear_vector(int vec
, void *bitmap
)
96 clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
99 static inline int apic_hw_enabled(struct kvm_lapic
*apic
)
101 return (apic
)->vcpu
->arch
.apic_base
& MSR_IA32_APICBASE_ENABLE
;
104 static inline int apic_sw_enabled(struct kvm_lapic
*apic
)
106 return apic_get_reg(apic
, APIC_SPIV
) & APIC_SPIV_APIC_ENABLED
;
109 static inline int apic_enabled(struct kvm_lapic
*apic
)
111 return apic_sw_enabled(apic
) && apic_hw_enabled(apic
);
115 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
118 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
119 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
121 static inline int kvm_apic_id(struct kvm_lapic
*apic
)
123 return (apic_get_reg(apic
, APIC_ID
) >> 24) & 0xff;
126 static inline int apic_lvt_enabled(struct kvm_lapic
*apic
, int lvt_type
)
128 return !(apic_get_reg(apic
, lvt_type
) & APIC_LVT_MASKED
);
131 static inline int apic_lvt_vector(struct kvm_lapic
*apic
, int lvt_type
)
133 return apic_get_reg(apic
, lvt_type
) & APIC_VECTOR_MASK
;
136 static inline int apic_lvtt_period(struct kvm_lapic
*apic
)
138 return apic_get_reg(apic
, APIC_LVTT
) & APIC_LVT_TIMER_PERIODIC
;
141 static inline int apic_lvt_nmi_mode(u32 lvt_val
)
143 return (lvt_val
& (APIC_MODE_MASK
| APIC_LVT_MASKED
)) == APIC_DM_NMI
;
146 void kvm_apic_set_version(struct kvm_vcpu
*vcpu
)
148 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
149 struct kvm_cpuid_entry2
*feat
;
150 u32 v
= APIC_VERSION
;
152 if (!irqchip_in_kernel(vcpu
->kvm
))
155 feat
= kvm_find_cpuid_entry(apic
->vcpu
, 0x1, 0);
156 if (feat
&& (feat
->ecx
& (1 << (X86_FEATURE_X2APIC
& 31))))
157 v
|= APIC_LVR_DIRECTED_EOI
;
158 apic_set_reg(apic
, APIC_LVR
, v
);
161 static inline int apic_x2apic_mode(struct kvm_lapic
*apic
)
163 return apic
->vcpu
->arch
.apic_base
& X2APIC_ENABLE
;
166 static unsigned int apic_lvt_mask
[APIC_LVT_NUM
] = {
167 LVT_MASK
| APIC_LVT_TIMER_PERIODIC
, /* LVTT */
168 LVT_MASK
| APIC_MODE_MASK
, /* LVTTHMR */
169 LVT_MASK
| APIC_MODE_MASK
, /* LVTPC */
170 LINT_MASK
, LINT_MASK
, /* LVT0-1 */
171 LVT_MASK
/* LVTERR */
174 static int find_highest_vector(void *bitmap
)
177 int word_offset
= MAX_APIC_VECTOR
>> 5;
179 while ((word_offset
!= 0) && (word
[(--word_offset
) << 2] == 0))
182 if (likely(!word_offset
&& !word
[0]))
185 return fls(word
[word_offset
<< 2]) - 1 + (word_offset
<< 5);
188 static inline int apic_test_and_set_irr(int vec
, struct kvm_lapic
*apic
)
190 apic
->irr_pending
= true;
191 return apic_test_and_set_vector(vec
, apic
->regs
+ APIC_IRR
);
194 static inline int apic_search_irr(struct kvm_lapic
*apic
)
196 return find_highest_vector(apic
->regs
+ APIC_IRR
);
199 static inline int apic_find_highest_irr(struct kvm_lapic
*apic
)
203 if (!apic
->irr_pending
)
206 result
= apic_search_irr(apic
);
207 ASSERT(result
== -1 || result
>= 16);
212 static inline void apic_clear_irr(int vec
, struct kvm_lapic
*apic
)
214 apic
->irr_pending
= false;
215 apic_clear_vector(vec
, apic
->regs
+ APIC_IRR
);
216 if (apic_search_irr(apic
) != -1)
217 apic
->irr_pending
= true;
220 int kvm_lapic_find_highest_irr(struct kvm_vcpu
*vcpu
)
222 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
225 /* This may race with setting of irr in __apic_accept_irq() and
226 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
227 * will cause vmexit immediately and the value will be recalculated
228 * on the next vmentry.
232 highest_irr
= apic_find_highest_irr(apic
);
237 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
238 int vector
, int level
, int trig_mode
);
240 int kvm_apic_set_irq(struct kvm_vcpu
*vcpu
, struct kvm_lapic_irq
*irq
)
242 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
244 return __apic_accept_irq(apic
, irq
->delivery_mode
, irq
->vector
,
245 irq
->level
, irq
->trig_mode
);
248 static inline int apic_find_highest_isr(struct kvm_lapic
*apic
)
252 result
= find_highest_vector(apic
->regs
+ APIC_ISR
);
253 ASSERT(result
== -1 || result
>= 16);
258 static void apic_update_ppr(struct kvm_lapic
*apic
)
263 tpr
= apic_get_reg(apic
, APIC_TASKPRI
);
264 isr
= apic_find_highest_isr(apic
);
265 isrv
= (isr
!= -1) ? isr
: 0;
267 if ((tpr
& 0xf0) >= (isrv
& 0xf0))
272 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
273 apic
, ppr
, isr
, isrv
);
275 apic_set_reg(apic
, APIC_PROCPRI
, ppr
);
278 static void apic_set_tpr(struct kvm_lapic
*apic
, u32 tpr
)
280 apic_set_reg(apic
, APIC_TASKPRI
, tpr
);
281 apic_update_ppr(apic
);
284 int kvm_apic_match_physical_addr(struct kvm_lapic
*apic
, u16 dest
)
286 return dest
== 0xff || kvm_apic_id(apic
) == dest
;
289 int kvm_apic_match_logical_addr(struct kvm_lapic
*apic
, u8 mda
)
294 if (apic_x2apic_mode(apic
)) {
295 logical_id
= apic_get_reg(apic
, APIC_LDR
);
296 return logical_id
& mda
;
299 logical_id
= GET_APIC_LOGICAL_ID(apic_get_reg(apic
, APIC_LDR
));
301 switch (apic_get_reg(apic
, APIC_DFR
)) {
303 if (logical_id
& mda
)
306 case APIC_DFR_CLUSTER
:
307 if (((logical_id
>> 4) == (mda
>> 0x4))
308 && (logical_id
& mda
& 0xf))
312 printk(KERN_WARNING
"Bad DFR vcpu %d: %08x\n",
313 apic
->vcpu
->vcpu_id
, apic_get_reg(apic
, APIC_DFR
));
320 int kvm_apic_match_dest(struct kvm_vcpu
*vcpu
, struct kvm_lapic
*source
,
321 int short_hand
, int dest
, int dest_mode
)
324 struct kvm_lapic
*target
= vcpu
->arch
.apic
;
326 apic_debug("target %p, source %p, dest 0x%x, "
327 "dest_mode 0x%x, short_hand 0x%x\n",
328 target
, source
, dest
, dest_mode
, short_hand
);
331 switch (short_hand
) {
332 case APIC_DEST_NOSHORT
:
335 result
= kvm_apic_match_physical_addr(target
, dest
);
338 result
= kvm_apic_match_logical_addr(target
, dest
);
341 result
= (target
== source
);
343 case APIC_DEST_ALLINC
:
346 case APIC_DEST_ALLBUT
:
347 result
= (target
!= source
);
350 printk(KERN_WARNING
"Bad dest shorthand value %x\n",
359 * Add a pending IRQ into lapic.
360 * Return 1 if successfully added and 0 if discarded.
362 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
363 int vector
, int level
, int trig_mode
)
366 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
368 switch (delivery_mode
) {
370 vcpu
->arch
.apic_arb_prio
++;
372 /* FIXME add logic for vcpu on reset */
373 if (unlikely(!apic_enabled(apic
)))
376 result
= !apic_test_and_set_irr(vector
, apic
);
377 trace_kvm_apic_accept_irq(vcpu
->vcpu_id
, delivery_mode
,
378 trig_mode
, vector
, !result
);
381 apic_debug("level trig mode repeatedly for "
382 "vector %d", vector
);
387 apic_debug("level trig mode for vector %d", vector
);
388 apic_set_vector(vector
, apic
->regs
+ APIC_TMR
);
390 apic_clear_vector(vector
, apic
->regs
+ APIC_TMR
);
395 printk(KERN_DEBUG
"Ignoring delivery mode 3\n");
399 printk(KERN_DEBUG
"Ignoring guest SMI\n");
404 kvm_inject_nmi(vcpu
);
411 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_RUNNABLE
)
413 "INIT on a runnable vcpu %d\n",
415 vcpu
->arch
.mp_state
= KVM_MP_STATE_INIT_RECEIVED
;
418 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
423 case APIC_DM_STARTUP
:
424 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
425 vcpu
->vcpu_id
, vector
);
426 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_INIT_RECEIVED
) {
428 vcpu
->arch
.sipi_vector
= vector
;
429 vcpu
->arch
.mp_state
= KVM_MP_STATE_SIPI_RECEIVED
;
436 * Should only be called by kvm_apic_local_deliver() with LVT0,
437 * before NMI watchdog was enabled. Already handled by
438 * kvm_apic_accept_pic_intr().
443 printk(KERN_ERR
"TODO: unsupported delivery mode %x\n",
450 int kvm_apic_compare_prio(struct kvm_vcpu
*vcpu1
, struct kvm_vcpu
*vcpu2
)
452 return vcpu1
->arch
.apic_arb_prio
- vcpu2
->arch
.apic_arb_prio
;
455 static void apic_set_eoi(struct kvm_lapic
*apic
)
457 int vector
= apic_find_highest_isr(apic
);
460 * Not every write EOI will has corresponding ISR,
461 * one example is when Kernel check timer on setup_IO_APIC
466 apic_clear_vector(vector
, apic
->regs
+ APIC_ISR
);
467 apic_update_ppr(apic
);
469 if (apic_test_and_clear_vector(vector
, apic
->regs
+ APIC_TMR
))
470 trigger_mode
= IOAPIC_LEVEL_TRIG
;
472 trigger_mode
= IOAPIC_EDGE_TRIG
;
473 if (!(apic_get_reg(apic
, APIC_SPIV
) & APIC_SPIV_DIRECTED_EOI
))
474 kvm_ioapic_update_eoi(apic
->vcpu
->kvm
, vector
, trigger_mode
);
477 static void apic_send_ipi(struct kvm_lapic
*apic
)
479 u32 icr_low
= apic_get_reg(apic
, APIC_ICR
);
480 u32 icr_high
= apic_get_reg(apic
, APIC_ICR2
);
481 struct kvm_lapic_irq irq
;
483 irq
.vector
= icr_low
& APIC_VECTOR_MASK
;
484 irq
.delivery_mode
= icr_low
& APIC_MODE_MASK
;
485 irq
.dest_mode
= icr_low
& APIC_DEST_MASK
;
486 irq
.level
= icr_low
& APIC_INT_ASSERT
;
487 irq
.trig_mode
= icr_low
& APIC_INT_LEVELTRIG
;
488 irq
.shorthand
= icr_low
& APIC_SHORT_MASK
;
489 if (apic_x2apic_mode(apic
))
490 irq
.dest_id
= icr_high
;
492 irq
.dest_id
= GET_APIC_DEST_FIELD(icr_high
);
494 trace_kvm_apic_ipi(icr_low
, irq
.dest_id
);
496 apic_debug("icr_high 0x%x, icr_low 0x%x, "
497 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
498 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
499 icr_high
, icr_low
, irq
.shorthand
, irq
.dest_id
,
500 irq
.trig_mode
, irq
.level
, irq
.dest_mode
, irq
.delivery_mode
,
503 kvm_irq_delivery_to_apic(apic
->vcpu
->kvm
, apic
, &irq
);
506 static u32
apic_get_tmcct(struct kvm_lapic
*apic
)
512 ASSERT(apic
!= NULL
);
514 /* if initial count is 0, current count should also be 0 */
515 if (apic_get_reg(apic
, APIC_TMICT
) == 0)
518 remaining
= hrtimer_expires_remaining(&apic
->lapic_timer
.timer
);
519 if (ktime_to_ns(remaining
) < 0)
520 remaining
= ktime_set(0, 0);
522 ns
= mod_64(ktime_to_ns(remaining
), apic
->lapic_timer
.period
);
523 tmcct
= div64_u64(ns
,
524 (APIC_BUS_CYCLE_NS
* apic
->divide_count
));
529 static void __report_tpr_access(struct kvm_lapic
*apic
, bool write
)
531 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
532 struct kvm_run
*run
= vcpu
->run
;
534 set_bit(KVM_REQ_REPORT_TPR_ACCESS
, &vcpu
->requests
);
535 run
->tpr_access
.rip
= kvm_rip_read(vcpu
);
536 run
->tpr_access
.is_write
= write
;
539 static inline void report_tpr_access(struct kvm_lapic
*apic
, bool write
)
541 if (apic
->vcpu
->arch
.tpr_access_reporting
)
542 __report_tpr_access(apic
, write
);
545 static u32
__apic_read(struct kvm_lapic
*apic
, unsigned int offset
)
549 if (offset
>= LAPIC_MMIO_LENGTH
)
554 if (apic_x2apic_mode(apic
))
555 val
= kvm_apic_id(apic
);
557 val
= kvm_apic_id(apic
) << 24;
560 printk(KERN_WARNING
"Access APIC ARBPRI register "
561 "which is for P6\n");
564 case APIC_TMCCT
: /* Timer CCR */
565 val
= apic_get_tmcct(apic
);
569 report_tpr_access(apic
, false);
572 apic_update_ppr(apic
);
573 val
= apic_get_reg(apic
, offset
);
580 static inline struct kvm_lapic
*to_lapic(struct kvm_io_device
*dev
)
582 return container_of(dev
, struct kvm_lapic
, dev
);
585 static int apic_reg_read(struct kvm_lapic
*apic
, u32 offset
, int len
,
588 unsigned char alignment
= offset
& 0xf;
590 /* this bitmask has a bit cleared for each reserver register */
591 static const u64 rmask
= 0x43ff01ffffffe70cULL
;
593 if ((alignment
+ len
) > 4) {
594 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
599 if (offset
> 0x3f0 || !(rmask
& (1ULL << (offset
>> 4)))) {
600 apic_debug("KVM_APIC_READ: read reserved register %x\n",
605 result
= __apic_read(apic
, offset
& ~0xf);
607 trace_kvm_apic_read(offset
, result
);
613 memcpy(data
, (char *)&result
+ alignment
, len
);
616 printk(KERN_ERR
"Local APIC read with len = %x, "
617 "should be 1,2, or 4 instead\n", len
);
623 static int apic_mmio_in_range(struct kvm_lapic
*apic
, gpa_t addr
)
625 return apic_hw_enabled(apic
) &&
626 addr
>= apic
->base_address
&&
627 addr
< apic
->base_address
+ LAPIC_MMIO_LENGTH
;
630 static int apic_mmio_read(struct kvm_io_device
*this,
631 gpa_t address
, int len
, void *data
)
633 struct kvm_lapic
*apic
= to_lapic(this);
634 u32 offset
= address
- apic
->base_address
;
636 if (!apic_mmio_in_range(apic
, address
))
639 apic_reg_read(apic
, offset
, len
, data
);
644 static void update_divide_count(struct kvm_lapic
*apic
)
646 u32 tmp1
, tmp2
, tdcr
;
648 tdcr
= apic_get_reg(apic
, APIC_TDCR
);
650 tmp2
= ((tmp1
& 0x3) | ((tmp1
& 0x8) >> 1)) + 1;
651 apic
->divide_count
= 0x1 << (tmp2
& 0x7);
653 apic_debug("timer divide count is 0x%x\n",
657 static void start_apic_timer(struct kvm_lapic
*apic
)
659 ktime_t now
= apic
->lapic_timer
.timer
.base
->get_time();
661 apic
->lapic_timer
.period
= (u64
)apic_get_reg(apic
, APIC_TMICT
) *
662 APIC_BUS_CYCLE_NS
* apic
->divide_count
;
663 atomic_set(&apic
->lapic_timer
.pending
, 0);
665 if (!apic
->lapic_timer
.period
)
668 * Do not allow the guest to program periodic timers with small
669 * interval, since the hrtimers are not throttled by the host
672 if (apic_lvtt_period(apic
)) {
673 if (apic
->lapic_timer
.period
< NSEC_PER_MSEC
/2)
674 apic
->lapic_timer
.period
= NSEC_PER_MSEC
/2;
677 hrtimer_start(&apic
->lapic_timer
.timer
,
678 ktime_add_ns(now
, apic
->lapic_timer
.period
),
681 apic_debug("%s: bus cycle is %" PRId64
"ns, now 0x%016"
683 "timer initial count 0x%x, period %lldns, "
684 "expire @ 0x%016" PRIx64
".\n", __func__
,
685 APIC_BUS_CYCLE_NS
, ktime_to_ns(now
),
686 apic_get_reg(apic
, APIC_TMICT
),
687 apic
->lapic_timer
.period
,
688 ktime_to_ns(ktime_add_ns(now
,
689 apic
->lapic_timer
.period
)));
692 static void apic_manage_nmi_watchdog(struct kvm_lapic
*apic
, u32 lvt0_val
)
694 int nmi_wd_enabled
= apic_lvt_nmi_mode(apic_get_reg(apic
, APIC_LVT0
));
696 if (apic_lvt_nmi_mode(lvt0_val
)) {
697 if (!nmi_wd_enabled
) {
698 apic_debug("Receive NMI setting on APIC_LVT0 "
699 "for cpu %d\n", apic
->vcpu
->vcpu_id
);
700 apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
++;
702 } else if (nmi_wd_enabled
)
703 apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
--;
706 static int apic_reg_write(struct kvm_lapic
*apic
, u32 reg
, u32 val
)
710 trace_kvm_apic_write(reg
, val
);
713 case APIC_ID
: /* Local APIC ID */
714 if (!apic_x2apic_mode(apic
))
715 apic_set_reg(apic
, APIC_ID
, val
);
721 report_tpr_access(apic
, true);
722 apic_set_tpr(apic
, val
& 0xff);
730 if (!apic_x2apic_mode(apic
))
731 apic_set_reg(apic
, APIC_LDR
, val
& APIC_LDR_MASK
);
737 if (!apic_x2apic_mode(apic
))
738 apic_set_reg(apic
, APIC_DFR
, val
| 0x0FFFFFFF);
745 if (apic_get_reg(apic
, APIC_LVR
) & APIC_LVR_DIRECTED_EOI
)
746 mask
|= APIC_SPIV_DIRECTED_EOI
;
747 apic_set_reg(apic
, APIC_SPIV
, val
& mask
);
748 if (!(val
& APIC_SPIV_APIC_ENABLED
)) {
752 for (i
= 0; i
< APIC_LVT_NUM
; i
++) {
753 lvt_val
= apic_get_reg(apic
,
754 APIC_LVTT
+ 0x10 * i
);
755 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
,
756 lvt_val
| APIC_LVT_MASKED
);
758 atomic_set(&apic
->lapic_timer
.pending
, 0);
764 /* No delay here, so we always clear the pending bit */
765 apic_set_reg(apic
, APIC_ICR
, val
& ~(1 << 12));
770 if (!apic_x2apic_mode(apic
))
772 apic_set_reg(apic
, APIC_ICR2
, val
);
776 apic_manage_nmi_watchdog(apic
, val
);
782 /* TODO: Check vector */
783 if (!apic_sw_enabled(apic
))
784 val
|= APIC_LVT_MASKED
;
786 val
&= apic_lvt_mask
[(reg
- APIC_LVTT
) >> 4];
787 apic_set_reg(apic
, reg
, val
);
792 hrtimer_cancel(&apic
->lapic_timer
.timer
);
793 apic_set_reg(apic
, APIC_TMICT
, val
);
794 start_apic_timer(apic
);
799 printk(KERN_ERR
"KVM_WRITE:TDCR %x\n", val
);
800 apic_set_reg(apic
, APIC_TDCR
, val
);
801 update_divide_count(apic
);
805 if (apic_x2apic_mode(apic
) && val
!= 0) {
806 printk(KERN_ERR
"KVM_WRITE:ESR not zero %x\n", val
);
812 if (apic_x2apic_mode(apic
)) {
813 apic_reg_write(apic
, APIC_ICR
, 0x40000 | (val
& 0xff));
822 apic_debug("Local APIC Write to read-only register %x\n", reg
);
826 static int apic_mmio_write(struct kvm_io_device
*this,
827 gpa_t address
, int len
, const void *data
)
829 struct kvm_lapic
*apic
= to_lapic(this);
830 unsigned int offset
= address
- apic
->base_address
;
833 if (!apic_mmio_in_range(apic
, address
))
837 * APIC register must be aligned on 128-bits boundary.
838 * 32/64/128 bits registers must be accessed thru 32 bits.
841 if (len
!= 4 || (offset
& 0xf)) {
842 /* Don't shout loud, $infamous_os would cause only noise. */
843 apic_debug("apic write: bad size=%d %lx\n", len
, (long)address
);
849 /* too common printing */
850 if (offset
!= APIC_EOI
)
851 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
852 "0x%x\n", __func__
, offset
, len
, val
);
854 apic_reg_write(apic
, offset
& 0xff0, val
);
859 void kvm_free_lapic(struct kvm_vcpu
*vcpu
)
861 if (!vcpu
->arch
.apic
)
864 hrtimer_cancel(&vcpu
->arch
.apic
->lapic_timer
.timer
);
866 if (vcpu
->arch
.apic
->regs_page
)
867 __free_page(vcpu
->arch
.apic
->regs_page
);
869 kfree(vcpu
->arch
.apic
);
873 *----------------------------------------------------------------------
875 *----------------------------------------------------------------------
878 void kvm_lapic_set_tpr(struct kvm_vcpu
*vcpu
, unsigned long cr8
)
880 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
884 apic_set_tpr(apic
, ((cr8
& 0x0f) << 4)
885 | (apic_get_reg(apic
, APIC_TASKPRI
) & 4));
888 u64
kvm_lapic_get_cr8(struct kvm_vcpu
*vcpu
)
890 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
895 tpr
= (u64
) apic_get_reg(apic
, APIC_TASKPRI
);
897 return (tpr
& 0xf0) >> 4;
900 void kvm_lapic_set_base(struct kvm_vcpu
*vcpu
, u64 value
)
902 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
905 value
|= MSR_IA32_APICBASE_BSP
;
906 vcpu
->arch
.apic_base
= value
;
910 if (!kvm_vcpu_is_bsp(apic
->vcpu
))
911 value
&= ~MSR_IA32_APICBASE_BSP
;
913 vcpu
->arch
.apic_base
= value
;
914 if (apic_x2apic_mode(apic
)) {
915 u32 id
= kvm_apic_id(apic
);
916 u32 ldr
= ((id
& ~0xf) << 16) | (1 << (id
& 0xf));
917 apic_set_reg(apic
, APIC_LDR
, ldr
);
919 apic
->base_address
= apic
->vcpu
->arch
.apic_base
&
920 MSR_IA32_APICBASE_BASE
;
922 /* with FSB delivery interrupt, we can restart APIC functionality */
923 apic_debug("apic base msr is 0x%016" PRIx64
", and base address is "
924 "0x%lx.\n", apic
->vcpu
->arch
.apic_base
, apic
->base_address
);
928 void kvm_lapic_reset(struct kvm_vcpu
*vcpu
)
930 struct kvm_lapic
*apic
;
933 apic_debug("%s\n", __func__
);
936 apic
= vcpu
->arch
.apic
;
937 ASSERT(apic
!= NULL
);
939 /* Stop the timer in case it's a reset to an active apic */
940 hrtimer_cancel(&apic
->lapic_timer
.timer
);
942 apic_set_reg(apic
, APIC_ID
, vcpu
->vcpu_id
<< 24);
943 kvm_apic_set_version(apic
->vcpu
);
945 for (i
= 0; i
< APIC_LVT_NUM
; i
++)
946 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
, APIC_LVT_MASKED
);
947 apic_set_reg(apic
, APIC_LVT0
,
948 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT
));
950 apic_set_reg(apic
, APIC_DFR
, 0xffffffffU
);
951 apic_set_reg(apic
, APIC_SPIV
, 0xff);
952 apic_set_reg(apic
, APIC_TASKPRI
, 0);
953 apic_set_reg(apic
, APIC_LDR
, 0);
954 apic_set_reg(apic
, APIC_ESR
, 0);
955 apic_set_reg(apic
, APIC_ICR
, 0);
956 apic_set_reg(apic
, APIC_ICR2
, 0);
957 apic_set_reg(apic
, APIC_TDCR
, 0);
958 apic_set_reg(apic
, APIC_TMICT
, 0);
959 for (i
= 0; i
< 8; i
++) {
960 apic_set_reg(apic
, APIC_IRR
+ 0x10 * i
, 0);
961 apic_set_reg(apic
, APIC_ISR
+ 0x10 * i
, 0);
962 apic_set_reg(apic
, APIC_TMR
+ 0x10 * i
, 0);
964 apic
->irr_pending
= false;
965 update_divide_count(apic
);
966 atomic_set(&apic
->lapic_timer
.pending
, 0);
967 if (kvm_vcpu_is_bsp(vcpu
))
968 vcpu
->arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
969 apic_update_ppr(apic
);
971 vcpu
->arch
.apic_arb_prio
= 0;
973 apic_debug(KERN_INFO
"%s: vcpu=%p, id=%d, base_msr="
974 "0x%016" PRIx64
", base_address=0x%0lx.\n", __func__
,
975 vcpu
, kvm_apic_id(apic
),
976 vcpu
->arch
.apic_base
, apic
->base_address
);
979 bool kvm_apic_present(struct kvm_vcpu
*vcpu
)
981 return vcpu
->arch
.apic
&& apic_hw_enabled(vcpu
->arch
.apic
);
984 int kvm_lapic_enabled(struct kvm_vcpu
*vcpu
)
986 return kvm_apic_present(vcpu
) && apic_sw_enabled(vcpu
->arch
.apic
);
990 *----------------------------------------------------------------------
992 *----------------------------------------------------------------------
995 static bool lapic_is_periodic(struct kvm_timer
*ktimer
)
997 struct kvm_lapic
*apic
= container_of(ktimer
, struct kvm_lapic
,
999 return apic_lvtt_period(apic
);
1002 int apic_has_pending_timer(struct kvm_vcpu
*vcpu
)
1004 struct kvm_lapic
*lapic
= vcpu
->arch
.apic
;
1006 if (lapic
&& apic_enabled(lapic
) && apic_lvt_enabled(lapic
, APIC_LVTT
))
1007 return atomic_read(&lapic
->lapic_timer
.pending
);
1012 static int kvm_apic_local_deliver(struct kvm_lapic
*apic
, int lvt_type
)
1014 u32 reg
= apic_get_reg(apic
, lvt_type
);
1015 int vector
, mode
, trig_mode
;
1017 if (apic_hw_enabled(apic
) && !(reg
& APIC_LVT_MASKED
)) {
1018 vector
= reg
& APIC_VECTOR_MASK
;
1019 mode
= reg
& APIC_MODE_MASK
;
1020 trig_mode
= reg
& APIC_LVT_LEVEL_TRIGGER
;
1021 return __apic_accept_irq(apic
, mode
, vector
, 1, trig_mode
);
1026 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu
*vcpu
)
1028 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1031 kvm_apic_local_deliver(apic
, APIC_LVT0
);
1034 static struct kvm_timer_ops lapic_timer_ops
= {
1035 .is_periodic
= lapic_is_periodic
,
1038 static const struct kvm_io_device_ops apic_mmio_ops
= {
1039 .read
= apic_mmio_read
,
1040 .write
= apic_mmio_write
,
1043 int kvm_create_lapic(struct kvm_vcpu
*vcpu
)
1045 struct kvm_lapic
*apic
;
1047 ASSERT(vcpu
!= NULL
);
1048 apic_debug("apic_init %d\n", vcpu
->vcpu_id
);
1050 apic
= kzalloc(sizeof(*apic
), GFP_KERNEL
);
1054 vcpu
->arch
.apic
= apic
;
1056 apic
->regs_page
= alloc_page(GFP_KERNEL
);
1057 if (apic
->regs_page
== NULL
) {
1058 printk(KERN_ERR
"malloc apic regs error for vcpu %x\n",
1060 goto nomem_free_apic
;
1062 apic
->regs
= page_address(apic
->regs_page
);
1063 memset(apic
->regs
, 0, PAGE_SIZE
);
1066 hrtimer_init(&apic
->lapic_timer
.timer
, CLOCK_MONOTONIC
,
1068 apic
->lapic_timer
.timer
.function
= kvm_timer_fn
;
1069 apic
->lapic_timer
.t_ops
= &lapic_timer_ops
;
1070 apic
->lapic_timer
.kvm
= vcpu
->kvm
;
1071 apic
->lapic_timer
.vcpu
= vcpu
;
1073 apic
->base_address
= APIC_DEFAULT_PHYS_BASE
;
1074 vcpu
->arch
.apic_base
= APIC_DEFAULT_PHYS_BASE
;
1076 kvm_lapic_reset(vcpu
);
1077 kvm_iodevice_init(&apic
->dev
, &apic_mmio_ops
);
1086 int kvm_apic_has_interrupt(struct kvm_vcpu
*vcpu
)
1088 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1091 if (!apic
|| !apic_enabled(apic
))
1094 apic_update_ppr(apic
);
1095 highest_irr
= apic_find_highest_irr(apic
);
1096 if ((highest_irr
== -1) ||
1097 ((highest_irr
& 0xF0) <= apic_get_reg(apic
, APIC_PROCPRI
)))
1102 int kvm_apic_accept_pic_intr(struct kvm_vcpu
*vcpu
)
1104 u32 lvt0
= apic_get_reg(vcpu
->arch
.apic
, APIC_LVT0
);
1107 if (kvm_vcpu_is_bsp(vcpu
)) {
1108 if (!apic_hw_enabled(vcpu
->arch
.apic
))
1110 if ((lvt0
& APIC_LVT_MASKED
) == 0 &&
1111 GET_APIC_DELIVERY_MODE(lvt0
) == APIC_MODE_EXTINT
)
1117 void kvm_inject_apic_timer_irqs(struct kvm_vcpu
*vcpu
)
1119 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1121 if (apic
&& atomic_read(&apic
->lapic_timer
.pending
) > 0) {
1122 if (kvm_apic_local_deliver(apic
, APIC_LVTT
))
1123 atomic_dec(&apic
->lapic_timer
.pending
);
1127 int kvm_get_apic_interrupt(struct kvm_vcpu
*vcpu
)
1129 int vector
= kvm_apic_has_interrupt(vcpu
);
1130 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1135 apic_set_vector(vector
, apic
->regs
+ APIC_ISR
);
1136 apic_update_ppr(apic
);
1137 apic_clear_irr(vector
, apic
);
1141 void kvm_apic_post_state_restore(struct kvm_vcpu
*vcpu
)
1143 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1145 apic
->base_address
= vcpu
->arch
.apic_base
&
1146 MSR_IA32_APICBASE_BASE
;
1147 kvm_apic_set_version(vcpu
);
1149 apic_update_ppr(apic
);
1150 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1151 update_divide_count(apic
);
1152 start_apic_timer(apic
);
1155 void __kvm_migrate_apic_timer(struct kvm_vcpu
*vcpu
)
1157 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1158 struct hrtimer
*timer
;
1163 timer
= &apic
->lapic_timer
.timer
;
1164 if (hrtimer_cancel(timer
))
1165 hrtimer_start_expires(timer
, HRTIMER_MODE_ABS
);
1168 void kvm_lapic_sync_from_vapic(struct kvm_vcpu
*vcpu
)
1173 if (!irqchip_in_kernel(vcpu
->kvm
) || !vcpu
->arch
.apic
->vapic_addr
)
1176 vapic
= kmap_atomic(vcpu
->arch
.apic
->vapic_page
, KM_USER0
);
1177 data
= *(u32
*)(vapic
+ offset_in_page(vcpu
->arch
.apic
->vapic_addr
));
1178 kunmap_atomic(vapic
, KM_USER0
);
1180 apic_set_tpr(vcpu
->arch
.apic
, data
& 0xff);
1183 void kvm_lapic_sync_to_vapic(struct kvm_vcpu
*vcpu
)
1186 int max_irr
, max_isr
;
1187 struct kvm_lapic
*apic
;
1190 if (!irqchip_in_kernel(vcpu
->kvm
) || !vcpu
->arch
.apic
->vapic_addr
)
1193 apic
= vcpu
->arch
.apic
;
1194 tpr
= apic_get_reg(apic
, APIC_TASKPRI
) & 0xff;
1195 max_irr
= apic_find_highest_irr(apic
);
1198 max_isr
= apic_find_highest_isr(apic
);
1201 data
= (tpr
& 0xff) | ((max_isr
& 0xf0) << 8) | (max_irr
<< 24);
1203 vapic
= kmap_atomic(vcpu
->arch
.apic
->vapic_page
, KM_USER0
);
1204 *(u32
*)(vapic
+ offset_in_page(vcpu
->arch
.apic
->vapic_addr
)) = data
;
1205 kunmap_atomic(vapic
, KM_USER0
);
1208 void kvm_lapic_set_vapic_addr(struct kvm_vcpu
*vcpu
, gpa_t vapic_addr
)
1210 if (!irqchip_in_kernel(vcpu
->kvm
))
1213 vcpu
->arch
.apic
->vapic_addr
= vapic_addr
;
1216 int kvm_x2apic_msr_write(struct kvm_vcpu
*vcpu
, u32 msr
, u64 data
)
1218 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1219 u32 reg
= (msr
- APIC_BASE_MSR
) << 4;
1221 if (!irqchip_in_kernel(vcpu
->kvm
) || !apic_x2apic_mode(apic
))
1224 /* if this is ICR write vector before command */
1226 apic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
1227 return apic_reg_write(apic
, reg
, (u32
)data
);
1230 int kvm_x2apic_msr_read(struct kvm_vcpu
*vcpu
, u32 msr
, u64
*data
)
1232 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1233 u32 reg
= (msr
- APIC_BASE_MSR
) << 4, low
, high
= 0;
1235 if (!irqchip_in_kernel(vcpu
->kvm
) || !apic_x2apic_mode(apic
))
1238 if (apic_reg_read(apic
, reg
, 4, &low
))
1241 apic_reg_read(apic
, APIC_ICR2
, 4, &high
);
1243 *data
= (((u64
)high
) << 32) | low
;