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On Tue, Nov 06, 2007 at 02:33:53AM -0800, akpm@linux-foundation.org wrote:
[mmotm.git] / drivers / gpu / drm / radeon / radeon_atombios.c
blob79d4b771c770d61b07ff632567c9852f8b6e04dc
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include "atom-bits.h"
32
33 /* from radeon_encoder.c */
34 extern uint32_t
35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37 extern void radeon_link_encoder_connector(struct drm_device *dev);
38 extern void
39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
41
42 /* from radeon_connector.c */
43 extern void
44 radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 bool linkb, uint32_t igp_lane_info);
50
51 /* from radeon_legacy_encoder.c */
52 extern void
53 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
54 uint32_t supported_device);
55
56 union atom_supported_devices {
57 struct _ATOM_SUPPORTED_DEVICES_INFO info;
58 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
59 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
60 };
61
62 static inline struct radeon_i2c_bus_rec radeon_lookup_gpio(struct drm_device
63 *dev, uint8_t id)
64 {
65 struct radeon_device *rdev = dev->dev_private;
66 struct atom_context *ctx = rdev->mode_info.atom_context;
67 ATOM_GPIO_I2C_ASSIGMENT gpio;
68 struct radeon_i2c_bus_rec i2c;
69 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
70 struct _ATOM_GPIO_I2C_INFO *i2c_info;
71 uint16_t data_offset;
72
73 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
74 i2c.valid = false;
75
76 atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
77
78 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
79
80 gpio = i2c_info->asGPIO_Info[id];
81
82 i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4;
83 i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4;
84 i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4;
85 i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4;
86 i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4;
87 i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4;
88 i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4;
89 i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4;
90 i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift);
91 i2c.mask_data_mask = (1 << gpio.ucDataMaskShift);
92 i2c.put_clk_mask = (1 << gpio.ucClkEnShift);
93 i2c.put_data_mask = (1 << gpio.ucDataEnShift);
94 i2c.get_clk_mask = (1 << gpio.ucClkY_Shift);
95 i2c.get_data_mask = (1 << gpio.ucDataY_Shift);
96 i2c.a_clk_mask = (1 << gpio.ucClkA_Shift);
97 i2c.a_data_mask = (1 << gpio.ucDataA_Shift);
98 i2c.valid = true;
99
100 return i2c;
101 }
102
103 static bool radeon_atom_apply_quirks(struct drm_device *dev,
104 uint32_t supported_device,
105 int *connector_type,
106 struct radeon_i2c_bus_rec *i2c_bus,
107 uint16_t *line_mux)
108 {
109
110 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
111 if ((dev->pdev->device == 0x791e) &&
112 (dev->pdev->subsystem_vendor == 0x1043) &&
113 (dev->pdev->subsystem_device == 0x826d)) {
114 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
115 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
116 *connector_type = DRM_MODE_CONNECTOR_DVID;
117 }
118
119 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
120 if ((dev->pdev->device == 0x7941) &&
121 (dev->pdev->subsystem_vendor == 0x147b) &&
122 (dev->pdev->subsystem_device == 0x2412)) {
123 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
124 return false;
125 }
126
127 /* Falcon NW laptop lists vga ddc line for LVDS */
128 if ((dev->pdev->device == 0x5653) &&
129 (dev->pdev->subsystem_vendor == 0x1462) &&
130 (dev->pdev->subsystem_device == 0x0291)) {
131 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
132 i2c_bus->valid = false;
133 *line_mux = 53;
134 }
135 }
136
137 /* Funky macbooks */
138 if ((dev->pdev->device == 0x71C5) &&
139 (dev->pdev->subsystem_vendor == 0x106b) &&
140 (dev->pdev->subsystem_device == 0x0080)) {
141 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
142 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
143 return false;
144 }
145
146 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
147 if ((dev->pdev->device == 0x9598) &&
148 (dev->pdev->subsystem_vendor == 0x1043) &&
149 (dev->pdev->subsystem_device == 0x01da)) {
150 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
151 *connector_type = DRM_MODE_CONNECTOR_DVII;
152 }
153 }
154
155 /* ASUS HD 3450 board lists the DVI port as HDMI */
156 if ((dev->pdev->device == 0x95C5) &&
157 (dev->pdev->subsystem_vendor == 0x1043) &&
158 (dev->pdev->subsystem_device == 0x01e2)) {
159 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
160 *connector_type = DRM_MODE_CONNECTOR_DVII;
161 }
162 }
163
164 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
165 * HDMI + VGA reporting as HDMI
166 */
167 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
168 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
169 *connector_type = DRM_MODE_CONNECTOR_VGA;
170 *line_mux = 0;
171 }
172 }
173
174 return true;
175 }
176
177 const int supported_devices_connector_convert[] = {
178 DRM_MODE_CONNECTOR_Unknown,
179 DRM_MODE_CONNECTOR_VGA,
180 DRM_MODE_CONNECTOR_DVII,
181 DRM_MODE_CONNECTOR_DVID,
182 DRM_MODE_CONNECTOR_DVIA,
183 DRM_MODE_CONNECTOR_SVIDEO,
184 DRM_MODE_CONNECTOR_Composite,
185 DRM_MODE_CONNECTOR_LVDS,
186 DRM_MODE_CONNECTOR_Unknown,
187 DRM_MODE_CONNECTOR_Unknown,
188 DRM_MODE_CONNECTOR_HDMIA,
189 DRM_MODE_CONNECTOR_HDMIB,
190 DRM_MODE_CONNECTOR_Unknown,
191 DRM_MODE_CONNECTOR_Unknown,
192 DRM_MODE_CONNECTOR_9PinDIN,
193 DRM_MODE_CONNECTOR_DisplayPort
194 };
195
196 const int object_connector_convert[] = {
197 DRM_MODE_CONNECTOR_Unknown,
198 DRM_MODE_CONNECTOR_DVII,
199 DRM_MODE_CONNECTOR_DVII,
200 DRM_MODE_CONNECTOR_DVID,
201 DRM_MODE_CONNECTOR_DVID,
202 DRM_MODE_CONNECTOR_VGA,
203 DRM_MODE_CONNECTOR_Composite,
204 DRM_MODE_CONNECTOR_SVIDEO,
205 DRM_MODE_CONNECTOR_Unknown,
206 DRM_MODE_CONNECTOR_Unknown,
207 DRM_MODE_CONNECTOR_9PinDIN,
208 DRM_MODE_CONNECTOR_Unknown,
209 DRM_MODE_CONNECTOR_HDMIA,
210 DRM_MODE_CONNECTOR_HDMIB,
211 DRM_MODE_CONNECTOR_LVDS,
212 DRM_MODE_CONNECTOR_9PinDIN,
213 DRM_MODE_CONNECTOR_Unknown,
214 DRM_MODE_CONNECTOR_Unknown,
215 DRM_MODE_CONNECTOR_Unknown,
216 DRM_MODE_CONNECTOR_DisplayPort
217 };
218
219 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
220 {
221 struct radeon_device *rdev = dev->dev_private;
222 struct radeon_mode_info *mode_info = &rdev->mode_info;
223 struct atom_context *ctx = mode_info->atom_context;
224 int index = GetIndexIntoMasterTable(DATA, Object_Header);
225 uint16_t size, data_offset;
226 uint8_t frev, crev, line_mux = 0;
227 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
228 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
229 ATOM_OBJECT_HEADER *obj_header;
230 int i, j, path_size, device_support;
231 int connector_type;
232 uint16_t igp_lane_info, conn_id;
233 bool linkb;
234 struct radeon_i2c_bus_rec ddc_bus;
235
236 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
237
238 if (data_offset == 0)
239 return false;
240
241 if (crev < 2)
242 return false;
243
244 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
245 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
246 (ctx->bios + data_offset +
247 le16_to_cpu(obj_header->usDisplayPathTableOffset));
248 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
249 (ctx->bios + data_offset +
250 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
251 device_support = le16_to_cpu(obj_header->usDeviceSupport);
252
253 path_size = 0;
254 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
255 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
256 ATOM_DISPLAY_OBJECT_PATH *path;
257 addr += path_size;
258 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
259 path_size += le16_to_cpu(path->usSize);
260 linkb = false;
261
262 if (device_support & le16_to_cpu(path->usDeviceTag)) {
263 uint8_t con_obj_id, con_obj_num, con_obj_type;
264
265 con_obj_id =
266 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
267 >> OBJECT_ID_SHIFT;
268 con_obj_num =
269 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
270 >> ENUM_ID_SHIFT;
271 con_obj_type =
272 (le16_to_cpu(path->usConnObjectId) &
273 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
274
275 /* TODO CV support */
276 if (le16_to_cpu(path->usDeviceTag) ==
277 ATOM_DEVICE_CV_SUPPORT)
278 continue;
279
280 if ((rdev->family == CHIP_RS780) &&
281 (con_obj_id ==
282 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
283 uint16_t igp_offset = 0;
284 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
285
286 index =
287 GetIndexIntoMasterTable(DATA,
288 IntegratedSystemInfo);
289
290 atom_parse_data_header(ctx, index, &size, &frev,
291 &crev, &igp_offset);
292
293 if (crev >= 2) {
294 igp_obj =
295 (ATOM_INTEGRATED_SYSTEM_INFO_V2
296 *) (ctx->bios + igp_offset);
297
298 if (igp_obj) {
299 uint32_t slot_config, ct;
300
301 if (con_obj_num == 1)
302 slot_config =
303 igp_obj->
304 ulDDISlot1Config;
305 else
306 slot_config =
307 igp_obj->
308 ulDDISlot2Config;
309
310 ct = (slot_config >> 16) & 0xff;
311 connector_type =
312 object_connector_convert
313 [ct];
314 igp_lane_info =
315 slot_config & 0xffff;
316 } else
317 continue;
318 } else
319 continue;
320 } else {
321 igp_lane_info = 0;
322 connector_type =
323 object_connector_convert[con_obj_id];
324 }
325
326 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
327 continue;
328
329 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
330 j++) {
331 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
332
333 enc_obj_id =
334 (le16_to_cpu(path->usGraphicObjIds[j]) &
335 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
336 enc_obj_num =
337 (le16_to_cpu(path->usGraphicObjIds[j]) &
338 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
339 enc_obj_type =
340 (le16_to_cpu(path->usGraphicObjIds[j]) &
341 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
342
343 /* FIXME: add support for router objects */
344 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
345 if (enc_obj_num == 2)
346 linkb = true;
347 else
348 linkb = false;
349
350 radeon_add_atom_encoder(dev,
351 enc_obj_id,
352 le16_to_cpu
353 (path->
354 usDeviceTag));
355
356 }
357 }
358
359 /* look up gpio for ddc */
360 if ((le16_to_cpu(path->usDeviceTag) &
361 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
362 == 0) {
363 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
364 if (le16_to_cpu(path->usConnObjectId) ==
365 le16_to_cpu(con_obj->asObjects[j].
366 usObjectID)) {
367 ATOM_COMMON_RECORD_HEADER
368 *record =
369 (ATOM_COMMON_RECORD_HEADER
370 *)
371 (ctx->bios + data_offset +
372 le16_to_cpu(con_obj->
373 asObjects[j].
374 usRecordOffset));
375 ATOM_I2C_RECORD *i2c_record;
376
377 while (record->ucRecordType > 0
378 && record->
379 ucRecordType <=
380 ATOM_MAX_OBJECT_RECORD_NUMBER) {
381 switch (record->
382 ucRecordType) {
383 case ATOM_I2C_RECORD_TYPE:
384 i2c_record =
385 (ATOM_I2C_RECORD
386 *) record;
387 line_mux =
388 i2c_record->
389 sucI2cId.
390 bfI2C_LineMux;
391 break;
392 }
393 record =
394 (ATOM_COMMON_RECORD_HEADER
395 *) ((char *)record
396 +
397 record->
398 ucRecordSize);
399 }
400 break;
401 }
402 }
403 } else
404 line_mux = 0;
405
406 if ((le16_to_cpu(path->usDeviceTag) ==
407 ATOM_DEVICE_TV1_SUPPORT)
408 || (le16_to_cpu(path->usDeviceTag) ==
409 ATOM_DEVICE_TV2_SUPPORT)
410 || (le16_to_cpu(path->usDeviceTag) ==
411 ATOM_DEVICE_CV_SUPPORT))
412 ddc_bus.valid = false;
413 else
414 ddc_bus = radeon_lookup_gpio(dev, line_mux);
415
416 conn_id = le16_to_cpu(path->usConnObjectId);
417
418 if (!radeon_atom_apply_quirks
419 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
420 &ddc_bus, &conn_id))
421 continue;
422
423 radeon_add_atom_connector(dev,
424 conn_id,
425 le16_to_cpu(path->
426 usDeviceTag),
427 connector_type, &ddc_bus,
428 linkb, igp_lane_info);
429
430 }
431 }
432
433 radeon_link_encoder_connector(dev);
434
435 return true;
436 }
437
438 struct bios_connector {
439 bool valid;
440 uint16_t line_mux;
441 uint16_t devices;
442 int connector_type;
443 struct radeon_i2c_bus_rec ddc_bus;
444 };
445
446 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
447 drm_device
448 *dev)
449 {
450 struct radeon_device *rdev = dev->dev_private;
451 struct radeon_mode_info *mode_info = &rdev->mode_info;
452 struct atom_context *ctx = mode_info->atom_context;
453 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
454 uint16_t size, data_offset;
455 uint8_t frev, crev;
456 uint16_t device_support;
457 uint8_t dac;
458 union atom_supported_devices *supported_devices;
459 int i, j;
460 struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
461
462 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
463
464 supported_devices =
465 (union atom_supported_devices *)(ctx->bios + data_offset);
466
467 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
468
469 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
470 ATOM_CONNECTOR_INFO_I2C ci =
471 supported_devices->info.asConnInfo[i];
472
473 bios_connectors[i].valid = false;
474
475 if (!(device_support & (1 << i))) {
476 continue;
477 }
478
479 if (i == ATOM_DEVICE_CV_INDEX) {
480 DRM_DEBUG("Skipping Component Video\n");
481 continue;
482 }
483
484 bios_connectors[i].connector_type =
485 supported_devices_connector_convert[ci.sucConnectorInfo.
486 sbfAccess.
487 bfConnectorType];
488
489 if (bios_connectors[i].connector_type ==
490 DRM_MODE_CONNECTOR_Unknown)
491 continue;
492
493 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
494
495 if ((rdev->family == CHIP_RS690) ||
496 (rdev->family == CHIP_RS740)) {
497 if ((i == ATOM_DEVICE_DFP2_INDEX)
498 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 2))
499 bios_connectors[i].line_mux =
500 ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
501 else if ((i == ATOM_DEVICE_DFP3_INDEX)
502 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 1))
503 bios_connectors[i].line_mux =
504 ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
505 else
506 bios_connectors[i].line_mux =
507 ci.sucI2cId.sbfAccess.bfI2C_LineMux;
508 } else
509 bios_connectors[i].line_mux =
510 ci.sucI2cId.sbfAccess.bfI2C_LineMux;
511
512 /* give tv unique connector ids */
513 if (i == ATOM_DEVICE_TV1_INDEX) {
514 bios_connectors[i].ddc_bus.valid = false;
515 bios_connectors[i].line_mux = 50;
516 } else if (i == ATOM_DEVICE_TV2_INDEX) {
517 bios_connectors[i].ddc_bus.valid = false;
518 bios_connectors[i].line_mux = 51;
519 } else if (i == ATOM_DEVICE_CV_INDEX) {
520 bios_connectors[i].ddc_bus.valid = false;
521 bios_connectors[i].line_mux = 52;
522 } else
523 bios_connectors[i].ddc_bus =
524 radeon_lookup_gpio(dev,
525 bios_connectors[i].line_mux);
526
527 /* Always set the connector type to VGA for CRT1/CRT2. if they are
528 * shared with a DVI port, we'll pick up the DVI connector when we
529 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
530 */
531 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
532 bios_connectors[i].connector_type =
533 DRM_MODE_CONNECTOR_VGA;
534
535 if (!radeon_atom_apply_quirks
536 (dev, (1 << i), &bios_connectors[i].connector_type,
537 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux))
538 continue;
539
540 bios_connectors[i].valid = true;
541 bios_connectors[i].devices = (1 << i);
542
543 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
544 radeon_add_atom_encoder(dev,
545 radeon_get_encoder_id(dev,
546 (1 << i),
547 dac),
548 (1 << i));
549 else
550 radeon_add_legacy_encoder(dev,
551 radeon_get_encoder_id(dev,
552 (1 <<
553 i),
554 dac),
555 (1 << i));
556 }
557
558 /* combine shared connectors */
559 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
560 if (bios_connectors[i].valid) {
561 for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) {
562 if (bios_connectors[j].valid && (i != j)) {
563 if (bios_connectors[i].line_mux ==
564 bios_connectors[j].line_mux) {
565 if (((bios_connectors[i].
566 devices &
567 (ATOM_DEVICE_DFP_SUPPORT))
568 && (bios_connectors[j].
569 devices &
570 (ATOM_DEVICE_CRT_SUPPORT)))
571 ||
572 ((bios_connectors[j].
573 devices &
574 (ATOM_DEVICE_DFP_SUPPORT))
575 && (bios_connectors[i].
576 devices &
577 (ATOM_DEVICE_CRT_SUPPORT)))) {
578 bios_connectors[i].
579 devices |=
580 bios_connectors[j].
581 devices;
582 bios_connectors[i].
583 connector_type =
584 DRM_MODE_CONNECTOR_DVII;
585 bios_connectors[j].
586 valid = false;
587 }
588 }
589 }
590 }
591 }
592 }
593
594 /* add the connectors */
595 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
596 if (bios_connectors[i].valid)
597 radeon_add_atom_connector(dev,
598 bios_connectors[i].line_mux,
599 bios_connectors[i].devices,
600 bios_connectors[i].
601 connector_type,
602 &bios_connectors[i].ddc_bus,
603 false, 0);
604 }
605
606 radeon_link_encoder_connector(dev);
607
608 return true;
609 }
610
611 union firmware_info {
612 ATOM_FIRMWARE_INFO info;
613 ATOM_FIRMWARE_INFO_V1_2 info_12;
614 ATOM_FIRMWARE_INFO_V1_3 info_13;
615 ATOM_FIRMWARE_INFO_V1_4 info_14;
616 };
617
618 bool radeon_atom_get_clock_info(struct drm_device *dev)
619 {
620 struct radeon_device *rdev = dev->dev_private;
621 struct radeon_mode_info *mode_info = &rdev->mode_info;
622 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
623 union firmware_info *firmware_info;
624 uint8_t frev, crev;
625 struct radeon_pll *p1pll = &rdev->clock.p1pll;
626 struct radeon_pll *p2pll = &rdev->clock.p2pll;
627 struct radeon_pll *spll = &rdev->clock.spll;
628 struct radeon_pll *mpll = &rdev->clock.mpll;
629 uint16_t data_offset;
630
631 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
632 &crev, &data_offset);
633
634 firmware_info =
635 (union firmware_info *)(mode_info->atom_context->bios +
636 data_offset);
637
638 if (firmware_info) {
639 /* pixel clocks */
640 p1pll->reference_freq =
641 le16_to_cpu(firmware_info->info.usReferenceClock);
642 p1pll->reference_div = 0;
643
644 p1pll->pll_out_min =
645 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
646 p1pll->pll_out_max =
647 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
648
649 if (p1pll->pll_out_min == 0) {
650 if (ASIC_IS_AVIVO(rdev))
651 p1pll->pll_out_min = 64800;
652 else
653 p1pll->pll_out_min = 20000;
654 }
655
656 p1pll->pll_in_min =
657 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
658 p1pll->pll_in_max =
659 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
660
661 *p2pll = *p1pll;
662
663 /* system clock */
664 spll->reference_freq =
665 le16_to_cpu(firmware_info->info.usReferenceClock);
666 spll->reference_div = 0;
667
668 spll->pll_out_min =
669 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
670 spll->pll_out_max =
671 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
672
673 /* ??? */
674 if (spll->pll_out_min == 0) {
675 if (ASIC_IS_AVIVO(rdev))
676 spll->pll_out_min = 64800;
677 else
678 spll->pll_out_min = 20000;
679 }
680
681 spll->pll_in_min =
682 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
683 spll->pll_in_max =
684 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
685
686 /* memory clock */
687 mpll->reference_freq =
688 le16_to_cpu(firmware_info->info.usReferenceClock);
689 mpll->reference_div = 0;
690
691 mpll->pll_out_min =
692 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
693 mpll->pll_out_max =
694 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
695
696 /* ??? */
697 if (mpll->pll_out_min == 0) {
698 if (ASIC_IS_AVIVO(rdev))
699 mpll->pll_out_min = 64800;
700 else
701 mpll->pll_out_min = 20000;
702 }
703
704 mpll->pll_in_min =
705 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
706 mpll->pll_in_max =
707 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
708
709 rdev->clock.default_sclk =
710 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
711 rdev->clock.default_mclk =
712 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
713
714 return true;
715 }
716 return false;
717 }
718
719 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
720 struct radeon_encoder_int_tmds *tmds)
721 {
722 struct drm_device *dev = encoder->base.dev;
723 struct radeon_device *rdev = dev->dev_private;
724 struct radeon_mode_info *mode_info = &rdev->mode_info;
725 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
726 uint16_t data_offset;
727 struct _ATOM_TMDS_INFO *tmds_info;
728 uint8_t frev, crev;
729 uint16_t maxfreq;
730 int i;
731
732 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
733 &crev, &data_offset);
734
735 tmds_info =
736 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
737 data_offset);
738
739 if (tmds_info) {
740 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
741 for (i = 0; i < 4; i++) {
742 tmds->tmds_pll[i].freq =
743 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
744 tmds->tmds_pll[i].value =
745 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
746 tmds->tmds_pll[i].value |=
747 (tmds_info->asMiscInfo[i].
748 ucPLL_VCO_Gain & 0x3f) << 6;
749 tmds->tmds_pll[i].value |=
750 (tmds_info->asMiscInfo[i].
751 ucPLL_DutyCycle & 0xf) << 12;
752 tmds->tmds_pll[i].value |=
753 (tmds_info->asMiscInfo[i].
754 ucPLL_VoltageSwing & 0xf) << 16;
755
756 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
757 tmds->tmds_pll[i].freq,
758 tmds->tmds_pll[i].value);
759
760 if (maxfreq == tmds->tmds_pll[i].freq) {
761 tmds->tmds_pll[i].freq = 0xffffffff;
762 break;
763 }
764 }
765 return true;
766 }
767 return false;
768 }
769
770 union lvds_info {
771 struct _ATOM_LVDS_INFO info;
772 struct _ATOM_LVDS_INFO_V12 info_12;
773 };
774
775 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
776 radeon_encoder
777 *encoder)
778 {
779 struct drm_device *dev = encoder->base.dev;
780 struct radeon_device *rdev = dev->dev_private;
781 struct radeon_mode_info *mode_info = &rdev->mode_info;
782 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
783 uint16_t data_offset;
784 union lvds_info *lvds_info;
785 uint8_t frev, crev;
786 struct radeon_encoder_atom_dig *lvds = NULL;
787
788 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
789 &crev, &data_offset);
790
791 lvds_info =
792 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
793
794 if (lvds_info) {
795 lvds =
796 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
797
798 if (!lvds)
799 return NULL;
800
801 lvds->native_mode.clock =
802 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
803 lvds->native_mode.hdisplay =
804 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
805 lvds->native_mode.vdisplay =
806 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
807 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
808 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
809 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
810 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
811 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
812 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
813 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
814 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
815 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
816 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
817 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
818 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
819 lvds->panel_pwr_delay =
820 le16_to_cpu(lvds_info->info.usOffDelayInMs);
821 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
822 /* set crtc values */
823 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
824
825 encoder->native_mode = lvds->native_mode;
826 }
827 return lvds;
828 }
829
830 struct radeon_encoder_primary_dac *
831 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
832 {
833 struct drm_device *dev = encoder->base.dev;
834 struct radeon_device *rdev = dev->dev_private;
835 struct radeon_mode_info *mode_info = &rdev->mode_info;
836 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
837 uint16_t data_offset;
838 struct _COMPASSIONATE_DATA *dac_info;
839 uint8_t frev, crev;
840 uint8_t bg, dac;
841 struct radeon_encoder_primary_dac *p_dac = NULL;
842
843 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
844
845 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
846
847 if (dac_info) {
848 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
849
850 if (!p_dac)
851 return NULL;
852
853 bg = dac_info->ucDAC1_BG_Adjustment;
854 dac = dac_info->ucDAC1_DAC_Adjustment;
855 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
856
857 }
858 return p_dac;
859 }
860
861 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
862 struct drm_display_mode *mode)
863 {
864 struct radeon_mode_info *mode_info = &rdev->mode_info;
865 ATOM_ANALOG_TV_INFO *tv_info;
866 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
867 ATOM_DTD_FORMAT *dtd_timings;
868 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
869 u8 frev, crev;
870 u16 data_offset, misc;
871
872 atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
873
874 switch (crev) {
875 case 1:
876 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
877 if (index > MAX_SUPPORTED_TV_TIMING)
878 return false;
879
880 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
881 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
882 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
883 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
884 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
885
886 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
887 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
888 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
889 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
890 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
891
892 mode->flags = 0;
893 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
894 if (misc & ATOM_VSYNC_POLARITY)
895 mode->flags |= DRM_MODE_FLAG_NVSYNC;
896 if (misc & ATOM_HSYNC_POLARITY)
897 mode->flags |= DRM_MODE_FLAG_NHSYNC;
898 if (misc & ATOM_COMPOSITESYNC)
899 mode->flags |= DRM_MODE_FLAG_CSYNC;
900 if (misc & ATOM_INTERLACE)
901 mode->flags |= DRM_MODE_FLAG_INTERLACE;
902 if (misc & ATOM_DOUBLE_CLOCK_MODE)
903 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
904
905 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
906
907 if (index == 1) {
908 /* PAL timings appear to have wrong values for totals */
909 mode->crtc_htotal -= 1;
910 mode->crtc_vtotal -= 1;
911 }
912 break;
913 case 2:
914 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
915 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
916 return false;
917
918 dtd_timings = &tv_info_v1_2->aModeTimings[index];
919 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
920 le16_to_cpu(dtd_timings->usHBlanking_Time);
921 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
922 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
923 le16_to_cpu(dtd_timings->usHSyncOffset);
924 mode->crtc_hsync_end = mode->crtc_hsync_start +
925 le16_to_cpu(dtd_timings->usHSyncWidth);
926
927 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
928 le16_to_cpu(dtd_timings->usVBlanking_Time);
929 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
930 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
931 le16_to_cpu(dtd_timings->usVSyncOffset);
932 mode->crtc_vsync_end = mode->crtc_vsync_start +
933 le16_to_cpu(dtd_timings->usVSyncWidth);
934
935 mode->flags = 0;
936 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
937 if (misc & ATOM_VSYNC_POLARITY)
938 mode->flags |= DRM_MODE_FLAG_NVSYNC;
939 if (misc & ATOM_HSYNC_POLARITY)
940 mode->flags |= DRM_MODE_FLAG_NHSYNC;
941 if (misc & ATOM_COMPOSITESYNC)
942 mode->flags |= DRM_MODE_FLAG_CSYNC;
943 if (misc & ATOM_INTERLACE)
944 mode->flags |= DRM_MODE_FLAG_INTERLACE;
945 if (misc & ATOM_DOUBLE_CLOCK_MODE)
946 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
947
948 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
949 break;
950 }
951 return true;
952 }
953
954 struct radeon_encoder_tv_dac *
955 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
956 {
957 struct drm_device *dev = encoder->base.dev;
958 struct radeon_device *rdev = dev->dev_private;
959 struct radeon_mode_info *mode_info = &rdev->mode_info;
960 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
961 uint16_t data_offset;
962 struct _COMPASSIONATE_DATA *dac_info;
963 uint8_t frev, crev;
964 uint8_t bg, dac;
965 struct radeon_encoder_tv_dac *tv_dac = NULL;
966
967 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
968
969 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
970
971 if (dac_info) {
972 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
973
974 if (!tv_dac)
975 return NULL;
976
977 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
978 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
979 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
980
981 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
982 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
983 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
984
985 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
986 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
987 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
988
989 }
990 return tv_dac;
991 }
992
993 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
994 {
995 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
996 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
997
998 args.ucEnable = enable;
999
1000 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1001 }
1002
1003 void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
1004 {
1005 ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
1006 int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
1007
1008 args.ucEnable = enable;
1009
1010 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1011 }
1012
1013 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1014 uint32_t eng_clock)
1015 {
1016 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1017 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1018
1019 args.ulTargetEngineClock = eng_clock; /* 10 khz */
1020
1021 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1022 }
1023
1024 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1025 uint32_t mem_clock)
1026 {
1027 SET_MEMORY_CLOCK_PS_ALLOCATION args;
1028 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1029
1030 if (rdev->flags & RADEON_IS_IGP)
1031 return;
1032
1033 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
1034
1035 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1036 }
1037
1038 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1039 {
1040 struct radeon_device *rdev = dev->dev_private;
1041 uint32_t bios_2_scratch, bios_6_scratch;
1042
1043 if (rdev->family >= CHIP_R600) {
1044 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1045 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1046 } else {
1047 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1048 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1049 }
1050
1051 /* let the bios control the backlight */
1052 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1053
1054 /* tell the bios not to handle mode switching */
1055 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1056
1057 if (rdev->family >= CHIP_R600) {
1058 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1059 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1060 } else {
1061 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1062 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1063 }
1064
1065 }
1066
1067 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1068 {
1069 uint32_t scratch_reg;
1070 int i;
1071
1072 if (rdev->family >= CHIP_R600)
1073 scratch_reg = R600_BIOS_0_SCRATCH;
1074 else
1075 scratch_reg = RADEON_BIOS_0_SCRATCH;
1076
1077 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1078 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1079 }
1080
1081 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
1082 {
1083 uint32_t scratch_reg;
1084 int i;
1085
1086 if (rdev->family >= CHIP_R600)
1087 scratch_reg = R600_BIOS_0_SCRATCH;
1088 else
1089 scratch_reg = RADEON_BIOS_0_SCRATCH;
1090
1091 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1092 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
1093 }
1094
1095 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1096 {
1097 struct drm_device *dev = encoder->dev;
1098 struct radeon_device *rdev = dev->dev_private;
1099 uint32_t bios_6_scratch;
1100
1101 if (rdev->family >= CHIP_R600)
1102 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1103 else
1104 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1105
1106 if (lock)
1107 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1108 else
1109 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1110
1111 if (rdev->family >= CHIP_R600)
1112 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1113 else
1114 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1115 }
1116
1117 /* at some point we may want to break this out into individual functions */
1118 void
1119 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
1120 struct drm_encoder *encoder,
1121 bool connected)
1122 {
1123 struct drm_device *dev = connector->dev;
1124 struct radeon_device *rdev = dev->dev_private;
1125 struct radeon_connector *radeon_connector =
1126 to_radeon_connector(connector);
1127 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1128 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1129
1130 if (rdev->family >= CHIP_R600) {
1131 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1132 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1133 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1134 } else {
1135 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1136 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1137 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1138 }
1139
1140 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
1141 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
1142 if (connected) {
1143 DRM_DEBUG("TV1 connected\n");
1144 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
1145 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
1146 } else {
1147 DRM_DEBUG("TV1 disconnected\n");
1148 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
1149 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
1150 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
1151 }
1152 }
1153 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
1154 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
1155 if (connected) {
1156 DRM_DEBUG("CV connected\n");
1157 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
1158 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
1159 } else {
1160 DRM_DEBUG("CV disconnected\n");
1161 bios_0_scratch &= ~ATOM_S0_CV_MASK;
1162 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
1163 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
1164 }
1165 }
1166 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
1167 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
1168 if (connected) {
1169 DRM_DEBUG("LCD1 connected\n");
1170 bios_0_scratch |= ATOM_S0_LCD1;
1171 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
1172 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
1173 } else {
1174 DRM_DEBUG("LCD1 disconnected\n");
1175 bios_0_scratch &= ~ATOM_S0_LCD1;
1176 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
1177 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
1178 }
1179 }
1180 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
1181 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
1182 if (connected) {
1183 DRM_DEBUG("CRT1 connected\n");
1184 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
1185 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
1186 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
1187 } else {
1188 DRM_DEBUG("CRT1 disconnected\n");
1189 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
1190 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
1191 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
1192 }
1193 }
1194 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
1195 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
1196 if (connected) {
1197 DRM_DEBUG("CRT2 connected\n");
1198 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
1199 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
1200 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
1201 } else {
1202 DRM_DEBUG("CRT2 disconnected\n");
1203 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
1204 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
1205 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
1206 }
1207 }
1208 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
1209 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
1210 if (connected) {
1211 DRM_DEBUG("DFP1 connected\n");
1212 bios_0_scratch |= ATOM_S0_DFP1;
1213 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
1214 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
1215 } else {
1216 DRM_DEBUG("DFP1 disconnected\n");
1217 bios_0_scratch &= ~ATOM_S0_DFP1;
1218 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
1219 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
1220 }
1221 }
1222 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
1223 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
1224 if (connected) {
1225 DRM_DEBUG("DFP2 connected\n");
1226 bios_0_scratch |= ATOM_S0_DFP2;
1227 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
1228 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
1229 } else {
1230 DRM_DEBUG("DFP2 disconnected\n");
1231 bios_0_scratch &= ~ATOM_S0_DFP2;
1232 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
1233 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
1234 }
1235 }
1236 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
1237 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
1238 if (connected) {
1239 DRM_DEBUG("DFP3 connected\n");
1240 bios_0_scratch |= ATOM_S0_DFP3;
1241 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
1242 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
1243 } else {
1244 DRM_DEBUG("DFP3 disconnected\n");
1245 bios_0_scratch &= ~ATOM_S0_DFP3;
1246 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
1247 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
1248 }
1249 }
1250 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
1251 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
1252 if (connected) {
1253 DRM_DEBUG("DFP4 connected\n");
1254 bios_0_scratch |= ATOM_S0_DFP4;
1255 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
1256 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
1257 } else {
1258 DRM_DEBUG("DFP4 disconnected\n");
1259 bios_0_scratch &= ~ATOM_S0_DFP4;
1260 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
1261 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
1262 }
1263 }
1264 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
1265 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
1266 if (connected) {
1267 DRM_DEBUG("DFP5 connected\n");
1268 bios_0_scratch |= ATOM_S0_DFP5;
1269 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
1270 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
1271 } else {
1272 DRM_DEBUG("DFP5 disconnected\n");
1273 bios_0_scratch &= ~ATOM_S0_DFP5;
1274 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
1275 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
1276 }
1277 }
1278
1279 if (rdev->family >= CHIP_R600) {
1280 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
1281 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1282 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1283 } else {
1284 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
1285 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1286 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1287 }
1288 }
1289
1290 void
1291 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
1292 {
1293 struct drm_device *dev = encoder->dev;
1294 struct radeon_device *rdev = dev->dev_private;
1295 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1296 uint32_t bios_3_scratch;
1297
1298 if (rdev->family >= CHIP_R600)
1299 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1300 else
1301 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1302
1303 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1304 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
1305 bios_3_scratch |= (crtc << 18);
1306 }
1307 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1308 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
1309 bios_3_scratch |= (crtc << 24);
1310 }
1311 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1312 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
1313 bios_3_scratch |= (crtc << 16);
1314 }
1315 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1316 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
1317 bios_3_scratch |= (crtc << 20);
1318 }
1319 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1320 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
1321 bios_3_scratch |= (crtc << 17);
1322 }
1323 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1324 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
1325 bios_3_scratch |= (crtc << 19);
1326 }
1327 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1328 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
1329 bios_3_scratch |= (crtc << 23);
1330 }
1331 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1332 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
1333 bios_3_scratch |= (crtc << 25);
1334 }
1335
1336 if (rdev->family >= CHIP_R600)
1337 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1338 else
1339 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1340 }
1341
1342 void
1343 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
1344 {
1345 struct drm_device *dev = encoder->dev;
1346 struct radeon_device *rdev = dev->dev_private;
1347 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1348 uint32_t bios_2_scratch;
1349
1350 if (rdev->family >= CHIP_R600)
1351 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1352 else
1353 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1354
1355 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1356 if (on)
1357 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
1358 else
1359 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
1360 }
1361 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1362 if (on)
1363 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
1364 else
1365 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
1366 }
1367 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1368 if (on)
1369 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
1370 else
1371 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
1372 }
1373 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1374 if (on)
1375 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
1376 else
1377 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
1378 }
1379 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1380 if (on)
1381 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
1382 else
1383 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
1384 }
1385 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1386 if (on)
1387 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
1388 else
1389 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
1390 }
1391 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1392 if (on)
1393 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
1394 else
1395 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
1396 }
1397 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1398 if (on)
1399 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
1400 else
1401 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
1402 }
1403 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
1404 if (on)
1405 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
1406 else
1407 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
1408 }
1409 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
1410 if (on)
1411 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
1412 else
1413 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
1414 }
1415
1416 if (rdev->family >= CHIP_R600)
1417 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1418 else
1419 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1420 }
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