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On Tue, Nov 06, 2007 at 02:33:53AM -0800, akpm@linux-foundation.org wrote:
[mmotm.git] / drivers / mmc / host / atmel-mci.c
blob244f2d10a1e42c5a0754d59bfeee5b67492e1ee1
1 /*
2 * Atmel MultiMedia Card Interface driver
3 *
4 * Copyright (C) 2004-2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10 #include <linux/blkdev.h>
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/device.h>
14 #include <linux/dmaengine.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/scatterlist.h>
24 #include <linux/seq_file.h>
25 #include <linux/stat.h>
26
27 #include <linux/mmc/host.h>
28 #include <linux/atmel-mci.h>
29
30 #include <asm/io.h>
31 #include <asm/unaligned.h>
32
33 #include <mach/cpu.h>
34 #include <mach/board.h>
35
36 #include "atmel-mci-regs.h"
37
38 #define ATMCI_DATA_ERROR_FLAGS (MCI_DCRCE | MCI_DTOE | MCI_OVRE | MCI_UNRE)
39 #define ATMCI_DMA_THRESHOLD 16
40
41 enum {
42 EVENT_CMD_COMPLETE = 0,
43 EVENT_XFER_COMPLETE,
44 EVENT_DATA_COMPLETE,
45 EVENT_DATA_ERROR,
46 };
47
48 enum atmel_mci_state {
49 STATE_IDLE = 0,
50 STATE_SENDING_CMD,
51 STATE_SENDING_DATA,
52 STATE_DATA_BUSY,
53 STATE_SENDING_STOP,
54 STATE_DATA_ERROR,
55 };
56
57 struct atmel_mci_dma {
58 #ifdef CONFIG_MMC_ATMELMCI_DMA
59 struct dma_chan *chan;
60 struct dma_async_tx_descriptor *data_desc;
61 #endif
62 };
63
64 /**
65 * struct atmel_mci - MMC controller state shared between all slots
66 * @lock: Spinlock protecting the queue and associated data.
67 * @regs: Pointer to MMIO registers.
68 * @sg: Scatterlist entry currently being processed by PIO code, if any.
69 * @pio_offset: Offset into the current scatterlist entry.
70 * @cur_slot: The slot which is currently using the controller.
71 * @mrq: The request currently being processed on @cur_slot,
72 * or NULL if the controller is idle.
73 * @cmd: The command currently being sent to the card, or NULL.
74 * @data: The data currently being transferred, or NULL if no data
75 * transfer is in progress.
76 * @dma: DMA client state.
77 * @data_chan: DMA channel being used for the current data transfer.
78 * @cmd_status: Snapshot of SR taken upon completion of the current
79 * command. Only valid when EVENT_CMD_COMPLETE is pending.
80 * @data_status: Snapshot of SR taken upon completion of the current
81 * data transfer. Only valid when EVENT_DATA_COMPLETE or
82 * EVENT_DATA_ERROR is pending.
83 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
84 * to be sent.
85 * @tasklet: Tasklet running the request state machine.
86 * @pending_events: Bitmask of events flagged by the interrupt handler
87 * to be processed by the tasklet.
88 * @completed_events: Bitmask of events which the state machine has
89 * processed.
90 * @state: Tasklet state.
91 * @queue: List of slots waiting for access to the controller.
92 * @need_clock_update: Update the clock rate before the next request.
93 * @need_reset: Reset controller before next request.
94 * @mode_reg: Value of the MR register.
95 * @cfg_reg: Value of the CFG register.
96 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
97 * rate and timeout calculations.
98 * @mapbase: Physical address of the MMIO registers.
99 * @mck: The peripheral bus clock hooked up to the MMC controller.
100 * @pdev: Platform device associated with the MMC controller.
101 * @slot: Slots sharing this MMC controller.
102 *
103 * Locking
104 * =======
105 *
106 * @lock is a softirq-safe spinlock protecting @queue as well as
107 * @cur_slot, @mrq and @state. These must always be updated
108 * at the same time while holding @lock.
109 *
110 * @lock also protects mode_reg and need_clock_update since these are
111 * used to synchronize mode register updates with the queue
112 * processing.
113 *
114 * The @mrq field of struct atmel_mci_slot is also protected by @lock,
115 * and must always be written at the same time as the slot is added to
116 * @queue.
117 *
118 * @pending_events and @completed_events are accessed using atomic bit
119 * operations, so they don't need any locking.
120 *
121 * None of the fields touched by the interrupt handler need any
122 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
123 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
124 * interrupts must be disabled and @data_status updated with a
125 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
126 * CMDRDY interupt must be disabled and @cmd_status updated with a
127 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
128 * bytes_xfered field of @data must be written. This is ensured by
129 * using barriers.
130 */
131 struct atmel_mci {
132 spinlock_t lock;
133 void __iomem *regs;
134
135 struct scatterlist *sg;
136 unsigned int pio_offset;
137
138 struct atmel_mci_slot *cur_slot;
139 struct mmc_request *mrq;
140 struct mmc_command *cmd;
141 struct mmc_data *data;
142
143 struct atmel_mci_dma dma;
144 struct dma_chan *data_chan;
145
146 u32 cmd_status;
147 u32 data_status;
148 u32 stop_cmdr;
149
150 struct tasklet_struct tasklet;
151 unsigned long pending_events;
152 unsigned long completed_events;
153 enum atmel_mci_state state;
154 struct list_head queue;
155
156 bool need_clock_update;
157 bool need_reset;
158 u32 mode_reg;
159 u32 cfg_reg;
160 unsigned long bus_hz;
161 unsigned long mapbase;
162 struct clk *mck;
163 struct platform_device *pdev;
164
165 struct atmel_mci_slot *slot[ATMEL_MCI_MAX_NR_SLOTS];
166 };
167
168 /**
169 * struct atmel_mci_slot - MMC slot state
170 * @mmc: The mmc_host representing this slot.
171 * @host: The MMC controller this slot is using.
172 * @sdc_reg: Value of SDCR to be written before using this slot.
173 * @mrq: mmc_request currently being processed or waiting to be
174 * processed, or NULL when the slot is idle.
175 * @queue_node: List node for placing this node in the @queue list of
176 * &struct atmel_mci.
177 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
178 * @flags: Random state bits associated with the slot.
179 * @detect_pin: GPIO pin used for card detection, or negative if not
180 * available.
181 * @wp_pin: GPIO pin used for card write protect sending, or negative
182 * if not available.
183 * @detect_is_active_high: The state of the detect pin when it is active.
184 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
185 */
186 struct atmel_mci_slot {
187 struct mmc_host *mmc;
188 struct atmel_mci *host;
189
190 u32 sdc_reg;
191
192 struct mmc_request *mrq;
193 struct list_head queue_node;
194
195 unsigned int clock;
196 unsigned long flags;
197 #define ATMCI_CARD_PRESENT 0
198 #define ATMCI_CARD_NEED_INIT 1
199 #define ATMCI_SHUTDOWN 2
200
201 int detect_pin;
202 int wp_pin;
203 bool detect_is_active_high;
204
205 struct timer_list detect_timer;
206 };
207
208 #define atmci_test_and_clear_pending(host, event) \
209 test_and_clear_bit(event, &host->pending_events)
210 #define atmci_set_completed(host, event) \
211 set_bit(event, &host->completed_events)
212 #define atmci_set_pending(host, event) \
213 set_bit(event, &host->pending_events)
214
215 /*
216 * Enable or disable features/registers based on
217 * whether the processor supports them
218 */
219 static bool mci_has_rwproof(void)
220 {
221 if (cpu_is_at91sam9261() || cpu_is_at91rm9200())
222 return false;
223 else
224 return true;
225 }
226
227 /*
228 * The new MCI2 module isn't 100% compatible with the old MCI module,
229 * and it has a few nice features which we want to use...
230 */
231 static inline bool atmci_is_mci2(void)
232 {
233 if (cpu_is_at91sam9g45())
234 return true;
235
236 return false;
237 }
238
239
240 /*
241 * The debugfs stuff below is mostly optimized away when
242 * CONFIG_DEBUG_FS is not set.
243 */
244 static int atmci_req_show(struct seq_file *s, void *v)
245 {
246 struct atmel_mci_slot *slot = s->private;
247 struct mmc_request *mrq;
248 struct mmc_command *cmd;
249 struct mmc_command *stop;
250 struct mmc_data *data;
251
252 /* Make sure we get a consistent snapshot */
253 spin_lock_bh(&slot->host->lock);
254 mrq = slot->mrq;
255
256 if (mrq) {
257 cmd = mrq->cmd;
258 data = mrq->data;
259 stop = mrq->stop;
260
261 if (cmd)
262 seq_printf(s,
263 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
264 cmd->opcode, cmd->arg, cmd->flags,
265 cmd->resp[0], cmd->resp[1], cmd->resp[2],
266 cmd->resp[2], cmd->error);
267 if (data)
268 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
269 data->bytes_xfered, data->blocks,
270 data->blksz, data->flags, data->error);
271 if (stop)
272 seq_printf(s,
273 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
274 stop->opcode, stop->arg, stop->flags,
275 stop->resp[0], stop->resp[1], stop->resp[2],
276 stop->resp[2], stop->error);
277 }
278
279 spin_unlock_bh(&slot->host->lock);
280
281 return 0;
282 }
283
284 static int atmci_req_open(struct inode *inode, struct file *file)
285 {
286 return single_open(file, atmci_req_show, inode->i_private);
287 }
288
289 static const struct file_operations atmci_req_fops = {
290 .owner = THIS_MODULE,
291 .open = atmci_req_open,
292 .read = seq_read,
293 .llseek = seq_lseek,
294 .release = single_release,
295 };
296
297 static void atmci_show_status_reg(struct seq_file *s,
298 const char *regname, u32 value)
299 {
300 static const char *sr_bit[] = {
301 [0] = "CMDRDY",
302 [1] = "RXRDY",
303 [2] = "TXRDY",
304 [3] = "BLKE",
305 [4] = "DTIP",
306 [5] = "NOTBUSY",
307 [6] = "ENDRX",
308 [7] = "ENDTX",
309 [8] = "SDIOIRQA",
310 [9] = "SDIOIRQB",
311 [12] = "SDIOWAIT",
312 [14] = "RXBUFF",
313 [15] = "TXBUFE",
314 [16] = "RINDE",
315 [17] = "RDIRE",
316 [18] = "RCRCE",
317 [19] = "RENDE",
318 [20] = "RTOE",
319 [21] = "DCRCE",
320 [22] = "DTOE",
321 [23] = "CSTOE",
322 [24] = "BLKOVRE",
323 [25] = "DMADONE",
324 [26] = "FIFOEMPTY",
325 [27] = "XFRDONE",
326 [30] = "OVRE",
327 [31] = "UNRE",
328 };
329 unsigned int i;
330
331 seq_printf(s, "%s:\t0x%08x", regname, value);
332 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
333 if (value & (1 << i)) {
334 if (sr_bit[i])
335 seq_printf(s, " %s", sr_bit[i]);
336 else
337 seq_puts(s, " UNKNOWN");
338 }
339 }
340 seq_putc(s, '\n');
341 }
342
343 static int atmci_regs_show(struct seq_file *s, void *v)
344 {
345 struct atmel_mci *host = s->private;
346 u32 *buf;
347
348 buf = kmalloc(MCI_REGS_SIZE, GFP_KERNEL);
349 if (!buf)
350 return -ENOMEM;
351
352 /*
353 * Grab a more or less consistent snapshot. Note that we're
354 * not disabling interrupts, so IMR and SR may not be
355 * consistent.
356 */
357 spin_lock_bh(&host->lock);
358 clk_enable(host->mck);
359 memcpy_fromio(buf, host->regs, MCI_REGS_SIZE);
360 clk_disable(host->mck);
361 spin_unlock_bh(&host->lock);
362
363 seq_printf(s, "MR:\t0x%08x%s%s CLKDIV=%u\n",
364 buf[MCI_MR / 4],
365 buf[MCI_MR / 4] & MCI_MR_RDPROOF ? " RDPROOF" : "",
366 buf[MCI_MR / 4] & MCI_MR_WRPROOF ? " WRPROOF" : "",
367 buf[MCI_MR / 4] & 0xff);
368 seq_printf(s, "DTOR:\t0x%08x\n", buf[MCI_DTOR / 4]);
369 seq_printf(s, "SDCR:\t0x%08x\n", buf[MCI_SDCR / 4]);
370 seq_printf(s, "ARGR:\t0x%08x\n", buf[MCI_ARGR / 4]);
371 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
372 buf[MCI_BLKR / 4],
373 buf[MCI_BLKR / 4] & 0xffff,
374 (buf[MCI_BLKR / 4] >> 16) & 0xffff);
375 if (atmci_is_mci2())
376 seq_printf(s, "CSTOR:\t0x%08x\n", buf[MCI_CSTOR / 4]);
377
378 /* Don't read RSPR and RDR; it will consume the data there */
379
380 atmci_show_status_reg(s, "SR", buf[MCI_SR / 4]);
381 atmci_show_status_reg(s, "IMR", buf[MCI_IMR / 4]);
382
383 if (atmci_is_mci2()) {
384 u32 val;
385
386 val = buf[MCI_DMA / 4];
387 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
388 val, val & 3,
389 ((val >> 4) & 3) ?
390 1 << (((val >> 4) & 3) + 1) : 1,
391 val & MCI_DMAEN ? " DMAEN" : "");
392
393 val = buf[MCI_CFG / 4];
394 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
395 val,
396 val & MCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
397 val & MCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
398 val & MCI_CFG_HSMODE ? " HSMODE" : "",
399 val & MCI_CFG_LSYNC ? " LSYNC" : "");
400 }
401
402 kfree(buf);
403
404 return 0;
405 }
406
407 static int atmci_regs_open(struct inode *inode, struct file *file)
408 {
409 return single_open(file, atmci_regs_show, inode->i_private);
410 }
411
412 static const struct file_operations atmci_regs_fops = {
413 .owner = THIS_MODULE,
414 .open = atmci_regs_open,
415 .read = seq_read,
416 .llseek = seq_lseek,
417 .release = single_release,
418 };
419
420 static void atmci_init_debugfs(struct atmel_mci_slot *slot)
421 {
422 struct mmc_host *mmc = slot->mmc;
423 struct atmel_mci *host = slot->host;
424 struct dentry *root;
425 struct dentry *node;
426
427 root = mmc->debugfs_root;
428 if (!root)
429 return;
430
431 node = debugfs_create_file("regs", S_IRUSR, root, host,
432 &atmci_regs_fops);
433 if (IS_ERR(node))
434 return;
435 if (!node)
436 goto err;
437
438 node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
439 if (!node)
440 goto err;
441
442 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
443 if (!node)
444 goto err;
445
446 node = debugfs_create_x32("pending_events", S_IRUSR, root,
447 (u32 *)&host->pending_events);
448 if (!node)
449 goto err;
450
451 node = debugfs_create_x32("completed_events", S_IRUSR, root,
452 (u32 *)&host->completed_events);
453 if (!node)
454 goto err;
455
456 return;
457
458 err:
459 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
460 }
461
462 static inline unsigned int ns_to_clocks(struct atmel_mci *host,
463 unsigned int ns)
464 {
465 return (ns * (host->bus_hz / 1000000) + 999) / 1000;
466 }
467
468 static void atmci_set_timeout(struct atmel_mci *host,
469 struct atmel_mci_slot *slot, struct mmc_data *data)
470 {
471 static unsigned dtomul_to_shift[] = {
472 0, 4, 7, 8, 10, 12, 16, 20
473 };
474 unsigned timeout;
475 unsigned dtocyc;
476 unsigned dtomul;
477
478 timeout = ns_to_clocks(host, data->timeout_ns) + data->timeout_clks;
479
480 for (dtomul = 0; dtomul < 8; dtomul++) {
481 unsigned shift = dtomul_to_shift[dtomul];
482 dtocyc = (timeout + (1 << shift) - 1) >> shift;
483 if (dtocyc < 15)
484 break;
485 }
486
487 if (dtomul >= 8) {
488 dtomul = 7;
489 dtocyc = 15;
490 }
491
492 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
493 dtocyc << dtomul_to_shift[dtomul]);
494 mci_writel(host, DTOR, (MCI_DTOMUL(dtomul) | MCI_DTOCYC(dtocyc)));
495 }
496
497 /*
498 * Return mask with command flags to be enabled for this command.
499 */
500 static u32 atmci_prepare_command(struct mmc_host *mmc,
501 struct mmc_command *cmd)
502 {
503 struct mmc_data *data;
504 u32 cmdr;
505
506 cmd->error = -EINPROGRESS;
507
508 cmdr = MCI_CMDR_CMDNB(cmd->opcode);
509
510 if (cmd->flags & MMC_RSP_PRESENT) {
511 if (cmd->flags & MMC_RSP_136)
512 cmdr |= MCI_CMDR_RSPTYP_136BIT;
513 else
514 cmdr |= MCI_CMDR_RSPTYP_48BIT;
515 }
516
517 /*
518 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
519 * it's too difficult to determine whether this is an ACMD or
520 * not. Better make it 64.
521 */
522 cmdr |= MCI_CMDR_MAXLAT_64CYC;
523
524 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
525 cmdr |= MCI_CMDR_OPDCMD;
526
527 data = cmd->data;
528 if (data) {
529 cmdr |= MCI_CMDR_START_XFER;
530 if (data->flags & MMC_DATA_STREAM)
531 cmdr |= MCI_CMDR_STREAM;
532 else if (data->blocks > 1)
533 cmdr |= MCI_CMDR_MULTI_BLOCK;
534 else
535 cmdr |= MCI_CMDR_BLOCK;
536
537 if (data->flags & MMC_DATA_READ)
538 cmdr |= MCI_CMDR_TRDIR_READ;
539 }
540
541 return cmdr;
542 }
543
544 static void atmci_start_command(struct atmel_mci *host,
545 struct mmc_command *cmd, u32 cmd_flags)
546 {
547 WARN_ON(host->cmd);
548 host->cmd = cmd;
549
550 dev_vdbg(&host->pdev->dev,
551 "start command: ARGR=0x%08x CMDR=0x%08x\n",
552 cmd->arg, cmd_flags);
553
554 mci_writel(host, ARGR, cmd->arg);
555 mci_writel(host, CMDR, cmd_flags);
556 }
557
558 static void send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
559 {
560 atmci_start_command(host, data->stop, host->stop_cmdr);
561 mci_writel(host, IER, MCI_CMDRDY);
562 }
563
564 #ifdef CONFIG_MMC_ATMELMCI_DMA
565 static void atmci_dma_cleanup(struct atmel_mci *host)
566 {
567 struct mmc_data *data = host->data;
568
569 dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len,
570 ((data->flags & MMC_DATA_WRITE)
571 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
572 }
573
574 static void atmci_stop_dma(struct atmel_mci *host)
575 {
576 struct dma_chan *chan = host->data_chan;
577
578 if (chan) {
579 chan->device->device_terminate_all(chan);
580 atmci_dma_cleanup(host);
581 } else {
582 /* Data transfer was stopped by the interrupt handler */
583 atmci_set_pending(host, EVENT_XFER_COMPLETE);
584 mci_writel(host, IER, MCI_NOTBUSY);
585 }
586 }
587
588 /* This function is called by the DMA driver from tasklet context. */
589 static void atmci_dma_complete(void *arg)
590 {
591 struct atmel_mci *host = arg;
592 struct mmc_data *data = host->data;
593
594 dev_vdbg(&host->pdev->dev, "DMA complete\n");
595
596 if (atmci_is_mci2())
597 /* Disable DMA hardware handshaking on MCI */
598 mci_writel(host, DMA, mci_readl(host, DMA) & ~MCI_DMAEN);
599
600 atmci_dma_cleanup(host);
601
602 /*
603 * If the card was removed, data will be NULL. No point trying
604 * to send the stop command or waiting for NBUSY in this case.
605 */
606 if (data) {
607 atmci_set_pending(host, EVENT_XFER_COMPLETE);
608 tasklet_schedule(&host->tasklet);
609
610 /*
611 * Regardless of what the documentation says, we have
612 * to wait for NOTBUSY even after block read
613 * operations.
614 *
615 * When the DMA transfer is complete, the controller
616 * may still be reading the CRC from the card, i.e.
617 * the data transfer is still in progress and we
618 * haven't seen all the potential error bits yet.
619 *
620 * The interrupt handler will schedule a different
621 * tasklet to finish things up when the data transfer
622 * is completely done.
623 *
624 * We may not complete the mmc request here anyway
625 * because the mmc layer may call back and cause us to
626 * violate the "don't submit new operations from the
627 * completion callback" rule of the dma engine
628 * framework.
629 */
630 mci_writel(host, IER, MCI_NOTBUSY);
631 }
632 }
633
634 static int
635 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
636 {
637 struct dma_chan *chan;
638 struct dma_async_tx_descriptor *desc;
639 struct scatterlist *sg;
640 unsigned int i;
641 enum dma_data_direction direction;
642 unsigned int sglen;
643
644 /*
645 * We don't do DMA on "complex" transfers, i.e. with
646 * non-word-aligned buffers or lengths. Also, we don't bother
647 * with all the DMA setup overhead for short transfers.
648 */
649 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
650 return -EINVAL;
651 if (data->blksz & 3)
652 return -EINVAL;
653
654 for_each_sg(data->sg, sg, data->sg_len, i) {
655 if (sg->offset & 3 || sg->length & 3)
656 return -EINVAL;
657 }
658
659 /* If we don't have a channel, we can't do DMA */
660 chan = host->dma.chan;
661 if (chan)
662 host->data_chan = chan;
663
664 if (!chan)
665 return -ENODEV;
666
667 if (atmci_is_mci2())
668 mci_writel(host, DMA, MCI_DMA_CHKSIZE(3) | MCI_DMAEN);
669
670 if (data->flags & MMC_DATA_READ)
671 direction = DMA_FROM_DEVICE;
672 else
673 direction = DMA_TO_DEVICE;
674
675 sglen = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, direction);
676 if (sglen != data->sg_len)
677 goto unmap_exit;
678 desc = chan->device->device_prep_slave_sg(chan,
679 data->sg, data->sg_len, direction,
680 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
681 if (!desc)
682 goto unmap_exit;
683
684 host->dma.data_desc = desc;
685 desc->callback = atmci_dma_complete;
686 desc->callback_param = host;
687
688 return 0;
689 unmap_exit:
690 dma_unmap_sg(&host->pdev->dev, data->sg, sglen, direction);
691 return -ENOMEM;
692 }
693
694 static void atmci_submit_data(struct atmel_mci *host)
695 {
696 struct dma_chan *chan = host->data_chan;
697 struct dma_async_tx_descriptor *desc = host->dma.data_desc;
698
699 if (chan) {
700 desc->tx_submit(desc);
701 chan->device->device_issue_pending(chan);
702 }
703 }
704
705 #else /* CONFIG_MMC_ATMELMCI_DMA */
706
707 static int atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
708 {
709 return -ENOSYS;
710 }
711
712 static void atmci_submit_data(struct atmel_mci *host) {}
713
714 static void atmci_stop_dma(struct atmel_mci *host)
715 {
716 /* Data transfer was stopped by the interrupt handler */
717 atmci_set_pending(host, EVENT_XFER_COMPLETE);
718 mci_writel(host, IER, MCI_NOTBUSY);
719 }
720
721 #endif /* CONFIG_MMC_ATMELMCI_DMA */
722
723 /*
724 * Returns a mask of interrupt flags to be enabled after the whole
725 * request has been prepared.
726 */
727 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
728 {
729 u32 iflags;
730
731 data->error = -EINPROGRESS;
732
733 WARN_ON(host->data);
734 host->sg = NULL;
735 host->data = data;
736
737 iflags = ATMCI_DATA_ERROR_FLAGS;
738 if (atmci_prepare_data_dma(host, data)) {
739 host->data_chan = NULL;
740
741 /*
742 * Errata: MMC data write operation with less than 12
743 * bytes is impossible.
744 *
745 * Errata: MCI Transmit Data Register (TDR) FIFO
746 * corruption when length is not multiple of 4.
747 */
748 if (data->blocks * data->blksz < 12
749 || (data->blocks * data->blksz) & 3)
750 host->need_reset = true;
751
752 host->sg = data->sg;
753 host->pio_offset = 0;
754 if (data->flags & MMC_DATA_READ)
755 iflags |= MCI_RXRDY;
756 else
757 iflags |= MCI_TXRDY;
758 }
759
760 return iflags;
761 }
762
763 static void atmci_start_request(struct atmel_mci *host,
764 struct atmel_mci_slot *slot)
765 {
766 struct mmc_request *mrq;
767 struct mmc_command *cmd;
768 struct mmc_data *data;
769 u32 iflags;
770 u32 cmdflags;
771
772 mrq = slot->mrq;
773 host->cur_slot = slot;
774 host->mrq = mrq;
775
776 host->pending_events = 0;
777 host->completed_events = 0;
778 host->data_status = 0;
779
780 if (host->need_reset) {
781 mci_writel(host, CR, MCI_CR_SWRST);
782 mci_writel(host, CR, MCI_CR_MCIEN);
783 mci_writel(host, MR, host->mode_reg);
784 if (atmci_is_mci2())
785 mci_writel(host, CFG, host->cfg_reg);
786 host->need_reset = false;
787 }
788 mci_writel(host, SDCR, slot->sdc_reg);
789
790 iflags = mci_readl(host, IMR);
791 if (iflags)
792 dev_warn(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
793 iflags);
794
795 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
796 /* Send init sequence (74 clock cycles) */
797 mci_writel(host, CMDR, MCI_CMDR_SPCMD_INIT);
798 while (!(mci_readl(host, SR) & MCI_CMDRDY))
799 cpu_relax();
800 }
801 iflags = 0;
802 data = mrq->data;
803 if (data) {
804 atmci_set_timeout(host, slot, data);
805
806 /* Must set block count/size before sending command */
807 mci_writel(host, BLKR, MCI_BCNT(data->blocks)
808 | MCI_BLKLEN(data->blksz));
809 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
810 MCI_BCNT(data->blocks) | MCI_BLKLEN(data->blksz));
811
812 iflags |= atmci_prepare_data(host, data);
813 }
814
815 iflags |= MCI_CMDRDY;
816 cmd = mrq->cmd;
817 cmdflags = atmci_prepare_command(slot->mmc, cmd);
818 atmci_start_command(host, cmd, cmdflags);
819
820 if (data)
821 atmci_submit_data(host);
822
823 if (mrq->stop) {
824 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
825 host->stop_cmdr |= MCI_CMDR_STOP_XFER;
826 if (!(data->flags & MMC_DATA_WRITE))
827 host->stop_cmdr |= MCI_CMDR_TRDIR_READ;
828 if (data->flags & MMC_DATA_STREAM)
829 host->stop_cmdr |= MCI_CMDR_STREAM;
830 else
831 host->stop_cmdr |= MCI_CMDR_MULTI_BLOCK;
832 }
833
834 /*
835 * We could have enabled interrupts earlier, but I suspect
836 * that would open up a nice can of interesting race
837 * conditions (e.g. command and data complete, but stop not
838 * prepared yet.)
839 */
840 mci_writel(host, IER, iflags);
841 }
842
843 static void atmci_queue_request(struct atmel_mci *host,
844 struct atmel_mci_slot *slot, struct mmc_request *mrq)
845 {
846 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
847 host->state);
848
849 spin_lock_bh(&host->lock);
850 slot->mrq = mrq;
851 if (host->state == STATE_IDLE) {
852 host->state = STATE_SENDING_CMD;
853 atmci_start_request(host, slot);
854 } else {
855 list_add_tail(&slot->queue_node, &host->queue);
856 }
857 spin_unlock_bh(&host->lock);
858 }
859
860 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
861 {
862 struct atmel_mci_slot *slot = mmc_priv(mmc);
863 struct atmel_mci *host = slot->host;
864 struct mmc_data *data;
865
866 WARN_ON(slot->mrq);
867
868 /*
869 * We may "know" the card is gone even though there's still an
870 * electrical connection. If so, we really need to communicate
871 * this to the MMC core since there won't be any more
872 * interrupts as the card is completely removed. Otherwise,
873 * the MMC core might believe the card is still there even
874 * though the card was just removed very slowly.
875 */
876 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
877 mrq->cmd->error = -ENOMEDIUM;
878 mmc_request_done(mmc, mrq);
879 return;
880 }
881
882 /* We don't support multiple blocks of weird lengths. */
883 data = mrq->data;
884 if (data && data->blocks > 1 && data->blksz & 3) {
885 mrq->cmd->error = -EINVAL;
886 mmc_request_done(mmc, mrq);
887 }
888
889 atmci_queue_request(host, slot, mrq);
890 }
891
892 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
893 {
894 struct atmel_mci_slot *slot = mmc_priv(mmc);
895 struct atmel_mci *host = slot->host;
896 unsigned int i;
897
898 slot->sdc_reg &= ~MCI_SDCBUS_MASK;
899 switch (ios->bus_width) {
900 case MMC_BUS_WIDTH_1:
901 slot->sdc_reg |= MCI_SDCBUS_1BIT;
902 break;
903 case MMC_BUS_WIDTH_4:
904 slot->sdc_reg |= MCI_SDCBUS_4BIT;
905 break;
906 }
907
908 if (ios->clock) {
909 unsigned int clock_min = ~0U;
910 u32 clkdiv;
911
912 spin_lock_bh(&host->lock);
913 if (!host->mode_reg) {
914 clk_enable(host->mck);
915 mci_writel(host, CR, MCI_CR_SWRST);
916 mci_writel(host, CR, MCI_CR_MCIEN);
917 if (atmci_is_mci2())
918 mci_writel(host, CFG, host->cfg_reg);
919 }
920
921 /*
922 * Use mirror of ios->clock to prevent race with mmc
923 * core ios update when finding the minimum.
924 */
925 slot->clock = ios->clock;
926 for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) {
927 if (host->slot[i] && host->slot[i]->clock
928 && host->slot[i]->clock < clock_min)
929 clock_min = host->slot[i]->clock;
930 }
931
932 /* Calculate clock divider */
933 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
934 if (clkdiv > 255) {
935 dev_warn(&mmc->class_dev,
936 "clock %u too slow; using %lu\n",
937 clock_min, host->bus_hz / (2 * 256));
938 clkdiv = 255;
939 }
940
941 host->mode_reg = MCI_MR_CLKDIV(clkdiv);
942
943 /*
944 * WRPROOF and RDPROOF prevent overruns/underruns by
945 * stopping the clock when the FIFO is full/empty.
946 * This state is not expected to last for long.
947 */
948 if (mci_has_rwproof())
949 host->mode_reg |= (MCI_MR_WRPROOF | MCI_MR_RDPROOF);
950
951 if (list_empty(&host->queue))
952 mci_writel(host, MR, host->mode_reg);
953 else
954 host->need_clock_update = true;
955
956 spin_unlock_bh(&host->lock);
957 } else {
958 bool any_slot_active = false;
959
960 spin_lock_bh(&host->lock);
961 slot->clock = 0;
962 for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) {
963 if (host->slot[i] && host->slot[i]->clock) {
964 any_slot_active = true;
965 break;
966 }
967 }
968 if (!any_slot_active) {
969 mci_writel(host, CR, MCI_CR_MCIDIS);
970 if (host->mode_reg) {
971 mci_readl(host, MR);
972 clk_disable(host->mck);
973 }
974 host->mode_reg = 0;
975 }
976 spin_unlock_bh(&host->lock);
977 }
978
979 switch (ios->power_mode) {
980 case MMC_POWER_UP:
981 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
982 break;
983 default:
984 /*
985 * TODO: None of the currently available AVR32-based
986 * boards allow MMC power to be turned off. Implement
987 * power control when this can be tested properly.
988 *
989 * We also need to hook this into the clock management
990 * somehow so that newly inserted cards aren't
991 * subjected to a fast clock before we have a chance
992 * to figure out what the maximum rate is. Currently,
993 * there's no way to avoid this, and there never will
994 * be for boards that don't support power control.
995 */
996 break;
997 }
998 }
999
1000 static int atmci_get_ro(struct mmc_host *mmc)
1001 {
1002 int read_only = -ENOSYS;
1003 struct atmel_mci_slot *slot = mmc_priv(mmc);
1004
1005 if (gpio_is_valid(slot->wp_pin)) {
1006 read_only = gpio_get_value(slot->wp_pin);
1007 dev_dbg(&mmc->class_dev, "card is %s\n",
1008 read_only ? "read-only" : "read-write");
1009 }
1010
1011 return read_only;
1012 }
1013
1014 static int atmci_get_cd(struct mmc_host *mmc)
1015 {
1016 int present = -ENOSYS;
1017 struct atmel_mci_slot *slot = mmc_priv(mmc);
1018
1019 if (gpio_is_valid(slot->detect_pin)) {
1020 present = !(gpio_get_value(slot->detect_pin) ^
1021 slot->detect_is_active_high);
1022 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1023 present ? "" : "not ");
1024 }
1025
1026 return present;
1027 }
1028
1029 static const struct mmc_host_ops atmci_ops = {
1030 .request = atmci_request,
1031 .set_ios = atmci_set_ios,
1032 .get_ro = atmci_get_ro,
1033 .get_cd = atmci_get_cd,
1034 };
1035
1036 /* Called with host->lock held */
1037 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1038 __releases(&host->lock)
1039 __acquires(&host->lock)
1040 {
1041 struct atmel_mci_slot *slot = NULL;
1042 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1043
1044 WARN_ON(host->cmd || host->data);
1045
1046 /*
1047 * Update the MMC clock rate if necessary. This may be
1048 * necessary if set_ios() is called when a different slot is
1049 * busy transfering data.
1050 */
1051 if (host->need_clock_update)
1052 mci_writel(host, MR, host->mode_reg);
1053
1054 host->cur_slot->mrq = NULL;
1055 host->mrq = NULL;
1056 if (!list_empty(&host->queue)) {
1057 slot = list_entry(host->queue.next,
1058 struct atmel_mci_slot, queue_node);
1059 list_del(&slot->queue_node);
1060 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1061 mmc_hostname(slot->mmc));
1062 host->state = STATE_SENDING_CMD;
1063 atmci_start_request(host, slot);
1064 } else {
1065 dev_vdbg(&host->pdev->dev, "list empty\n");
1066 host->state = STATE_IDLE;
1067 }
1068
1069 spin_unlock(&host->lock);
1070 mmc_request_done(prev_mmc, mrq);
1071 spin_lock(&host->lock);
1072 }
1073
1074 static void atmci_command_complete(struct atmel_mci *host,
1075 struct mmc_command *cmd)
1076 {
1077 u32 status = host->cmd_status;
1078
1079 /* Read the response from the card (up to 16 bytes) */
1080 cmd->resp[0] = mci_readl(host, RSPR);
1081 cmd->resp[1] = mci_readl(host, RSPR);
1082 cmd->resp[2] = mci_readl(host, RSPR);
1083 cmd->resp[3] = mci_readl(host, RSPR);
1084
1085 if (status & MCI_RTOE)
1086 cmd->error = -ETIMEDOUT;
1087 else if ((cmd->flags & MMC_RSP_CRC) && (status & MCI_RCRCE))
1088 cmd->error = -EILSEQ;
1089 else if (status & (MCI_RINDE | MCI_RDIRE | MCI_RENDE))
1090 cmd->error = -EIO;
1091 else
1092 cmd->error = 0;
1093
1094 if (cmd->error) {
1095 dev_dbg(&host->pdev->dev,
1096 "command error: status=0x%08x\n", status);
1097
1098 if (cmd->data) {
1099 host->data = NULL;
1100 atmci_stop_dma(host);
1101 mci_writel(host, IDR, MCI_NOTBUSY
1102 | MCI_TXRDY | MCI_RXRDY
1103 | ATMCI_DATA_ERROR_FLAGS);
1104 }
1105 }
1106 }
1107
1108 static void atmci_detect_change(unsigned long data)
1109 {
1110 struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data;
1111 bool present;
1112 bool present_old;
1113
1114 /*
1115 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1116 * freeing the interrupt. We must not re-enable the interrupt
1117 * if it has been freed, and if we're shutting down, it
1118 * doesn't really matter whether the card is present or not.
1119 */
1120 smp_rmb();
1121 if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1122 return;
1123
1124 enable_irq(gpio_to_irq(slot->detect_pin));
1125 present = !(gpio_get_value(slot->detect_pin) ^
1126 slot->detect_is_active_high);
1127 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1128
1129 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1130 present, present_old);
1131
1132 if (present != present_old) {
1133 struct atmel_mci *host = slot->host;
1134 struct mmc_request *mrq;
1135
1136 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1137 present ? "inserted" : "removed");
1138
1139 spin_lock(&host->lock);
1140
1141 if (!present)
1142 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1143 else
1144 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1145
1146 /* Clean up queue if present */
1147 mrq = slot->mrq;
1148 if (mrq) {
1149 if (mrq == host->mrq) {
1150 /*
1151 * Reset controller to terminate any ongoing
1152 * commands or data transfers.
1153 */
1154 mci_writel(host, CR, MCI_CR_SWRST);
1155 mci_writel(host, CR, MCI_CR_MCIEN);
1156 mci_writel(host, MR, host->mode_reg);
1157 if (atmci_is_mci2())
1158 mci_writel(host, CFG, host->cfg_reg);
1159
1160 host->data = NULL;
1161 host->cmd = NULL;
1162
1163 switch (host->state) {
1164 case STATE_IDLE:
1165 break;
1166 case STATE_SENDING_CMD:
1167 mrq->cmd->error = -ENOMEDIUM;
1168 if (!mrq->data)
1169 break;
1170 /* fall through */
1171 case STATE_SENDING_DATA:
1172 mrq->data->error = -ENOMEDIUM;
1173 atmci_stop_dma(host);
1174 break;
1175 case STATE_DATA_BUSY:
1176 case STATE_DATA_ERROR:
1177 if (mrq->data->error == -EINPROGRESS)
1178 mrq->data->error = -ENOMEDIUM;
1179 if (!mrq->stop)
1180 break;
1181 /* fall through */
1182 case STATE_SENDING_STOP:
1183 mrq->stop->error = -ENOMEDIUM;
1184 break;
1185 }
1186
1187 atmci_request_end(host, mrq);
1188 } else {
1189 list_del(&slot->queue_node);
1190 mrq->cmd->error = -ENOMEDIUM;
1191 if (mrq->data)
1192 mrq->data->error = -ENOMEDIUM;
1193 if (mrq->stop)
1194 mrq->stop->error = -ENOMEDIUM;
1195
1196 spin_unlock(&host->lock);
1197 mmc_request_done(slot->mmc, mrq);
1198 spin_lock(&host->lock);
1199 }
1200 }
1201 spin_unlock(&host->lock);
1202
1203 mmc_detect_change(slot->mmc, 0);
1204 }
1205 }
1206
1207 static void atmci_tasklet_func(unsigned long priv)
1208 {
1209 struct atmel_mci *host = (struct atmel_mci *)priv;
1210 struct mmc_request *mrq = host->mrq;
1211 struct mmc_data *data = host->data;
1212 struct mmc_command *cmd = host->cmd;
1213 enum atmel_mci_state state = host->state;
1214 enum atmel_mci_state prev_state;
1215 u32 status;
1216
1217 spin_lock(&host->lock);
1218
1219 state = host->state;
1220
1221 dev_vdbg(&host->pdev->dev,
1222 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1223 state, host->pending_events, host->completed_events,
1224 mci_readl(host, IMR));
1225
1226 do {
1227 prev_state = state;
1228
1229 switch (state) {
1230 case STATE_IDLE:
1231 break;
1232
1233 case STATE_SENDING_CMD:
1234 if (!atmci_test_and_clear_pending(host,
1235 EVENT_CMD_COMPLETE))
1236 break;
1237
1238 host->cmd = NULL;
1239 atmci_set_completed(host, EVENT_CMD_COMPLETE);
1240 atmci_command_complete(host, mrq->cmd);
1241 if (!mrq->data || cmd->error) {
1242 atmci_request_end(host, host->mrq);
1243 goto unlock;
1244 }
1245
1246 prev_state = state = STATE_SENDING_DATA;
1247 /* fall through */
1248
1249 case STATE_SENDING_DATA:
1250 if (atmci_test_and_clear_pending(host,
1251 EVENT_DATA_ERROR)) {
1252 atmci_stop_dma(host);
1253 if (data->stop)
1254 send_stop_cmd(host, data);
1255 state = STATE_DATA_ERROR;
1256 break;
1257 }
1258
1259 if (!atmci_test_and_clear_pending(host,
1260 EVENT_XFER_COMPLETE))
1261 break;
1262
1263 atmci_set_completed(host, EVENT_XFER_COMPLETE);
1264 prev_state = state = STATE_DATA_BUSY;
1265 /* fall through */
1266
1267 case STATE_DATA_BUSY:
1268 if (!atmci_test_and_clear_pending(host,
1269 EVENT_DATA_COMPLETE))
1270 break;
1271
1272 host->data = NULL;
1273 atmci_set_completed(host, EVENT_DATA_COMPLETE);
1274 status = host->data_status;
1275 if (unlikely(status & ATMCI_DATA_ERROR_FLAGS)) {
1276 if (status & MCI_DTOE) {
1277 dev_dbg(&host->pdev->dev,
1278 "data timeout error\n");
1279 data->error = -ETIMEDOUT;
1280 } else if (status & MCI_DCRCE) {
1281 dev_dbg(&host->pdev->dev,
1282 "data CRC error\n");
1283 data->error = -EILSEQ;
1284 } else {
1285 dev_dbg(&host->pdev->dev,
1286 "data FIFO error (status=%08x)\n",
1287 status);
1288 data->error = -EIO;
1289 }
1290 } else {
1291 data->bytes_xfered = data->blocks * data->blksz;
1292 data->error = 0;
1293 }
1294
1295 if (!data->stop) {
1296 atmci_request_end(host, host->mrq);
1297 goto unlock;
1298 }
1299
1300 prev_state = state = STATE_SENDING_STOP;
1301 if (!data->error)
1302 send_stop_cmd(host, data);
1303 /* fall through */
1304
1305 case STATE_SENDING_STOP:
1306 if (!atmci_test_and_clear_pending(host,
1307 EVENT_CMD_COMPLETE))
1308 break;
1309
1310 host->cmd = NULL;
1311 atmci_command_complete(host, mrq->stop);
1312 atmci_request_end(host, host->mrq);
1313 goto unlock;
1314
1315 case STATE_DATA_ERROR:
1316 if (!atmci_test_and_clear_pending(host,
1317 EVENT_XFER_COMPLETE))
1318 break;
1319
1320 state = STATE_DATA_BUSY;
1321 break;
1322 }
1323 } while (state != prev_state);
1324
1325 host->state = state;
1326
1327 unlock:
1328 spin_unlock(&host->lock);
1329 }
1330
1331 static void atmci_read_data_pio(struct atmel_mci *host)
1332 {
1333 struct scatterlist *sg = host->sg;
1334 void *buf = sg_virt(sg);
1335 unsigned int offset = host->pio_offset;
1336 struct mmc_data *data = host->data;
1337 u32 value;
1338 u32 status;
1339 unsigned int nbytes = 0;
1340
1341 do {
1342 value = mci_readl(host, RDR);
1343 if (likely(offset + 4 <= sg->length)) {
1344 put_unaligned(value, (u32 *)(buf + offset));
1345
1346 offset += 4;
1347 nbytes += 4;
1348
1349 if (offset == sg->length) {
1350 flush_dcache_page(sg_page(sg));
1351 host->sg = sg = sg_next(sg);
1352 if (!sg)
1353 goto done;
1354
1355 offset = 0;
1356 buf = sg_virt(sg);
1357 }
1358 } else {
1359 unsigned int remaining = sg->length - offset;
1360 memcpy(buf + offset, &value, remaining);
1361 nbytes += remaining;
1362
1363 flush_dcache_page(sg_page(sg));
1364 host->sg = sg = sg_next(sg);
1365 if (!sg)
1366 goto done;
1367
1368 offset = 4 - remaining;
1369 buf = sg_virt(sg);
1370 memcpy(buf, (u8 *)&value + remaining, offset);
1371 nbytes += offset;
1372 }
1373
1374 status = mci_readl(host, SR);
1375 if (status & ATMCI_DATA_ERROR_FLAGS) {
1376 mci_writel(host, IDR, (MCI_NOTBUSY | MCI_RXRDY
1377 | ATMCI_DATA_ERROR_FLAGS));
1378 host->data_status = status;
1379 data->bytes_xfered += nbytes;
1380 smp_wmb();
1381 atmci_set_pending(host, EVENT_DATA_ERROR);
1382 tasklet_schedule(&host->tasklet);
1383 return;
1384 }
1385 } while (status & MCI_RXRDY);
1386
1387 host->pio_offset = offset;
1388 data->bytes_xfered += nbytes;
1389
1390 return;
1391
1392 done:
1393 mci_writel(host, IDR, MCI_RXRDY);
1394 mci_writel(host, IER, MCI_NOTBUSY);
1395 data->bytes_xfered += nbytes;
1396 smp_wmb();
1397 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1398 }
1399
1400 static void atmci_write_data_pio(struct atmel_mci *host)
1401 {
1402 struct scatterlist *sg = host->sg;
1403 void *buf = sg_virt(sg);
1404 unsigned int offset = host->pio_offset;
1405 struct mmc_data *data = host->data;
1406 u32 value;
1407 u32 status;
1408 unsigned int nbytes = 0;
1409
1410 do {
1411 if (likely(offset + 4 <= sg->length)) {
1412 value = get_unaligned((u32 *)(buf + offset));
1413 mci_writel(host, TDR, value);
1414
1415 offset += 4;
1416 nbytes += 4;
1417 if (offset == sg->length) {
1418 host->sg = sg = sg_next(sg);
1419 if (!sg)
1420 goto done;
1421
1422 offset = 0;
1423 buf = sg_virt(sg);
1424 }
1425 } else {
1426 unsigned int remaining = sg->length - offset;
1427
1428 value = 0;
1429 memcpy(&value, buf + offset, remaining);
1430 nbytes += remaining;
1431
1432 host->sg = sg = sg_next(sg);
1433 if (!sg) {
1434 mci_writel(host, TDR, value);
1435 goto done;
1436 }
1437
1438 offset = 4 - remaining;
1439 buf = sg_virt(sg);
1440 memcpy((u8 *)&value + remaining, buf, offset);
1441 mci_writel(host, TDR, value);
1442 nbytes += offset;
1443 }
1444
1445 status = mci_readl(host, SR);
1446 if (status & ATMCI_DATA_ERROR_FLAGS) {
1447 mci_writel(host, IDR, (MCI_NOTBUSY | MCI_TXRDY
1448 | ATMCI_DATA_ERROR_FLAGS));
1449 host->data_status = status;
1450 data->bytes_xfered += nbytes;
1451 smp_wmb();
1452 atmci_set_pending(host, EVENT_DATA_ERROR);
1453 tasklet_schedule(&host->tasklet);
1454 return;
1455 }
1456 } while (status & MCI_TXRDY);
1457
1458 host->pio_offset = offset;
1459 data->bytes_xfered += nbytes;
1460
1461 return;
1462
1463 done:
1464 mci_writel(host, IDR, MCI_TXRDY);
1465 mci_writel(host, IER, MCI_NOTBUSY);
1466 data->bytes_xfered += nbytes;
1467 smp_wmb();
1468 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1469 }
1470
1471 static void atmci_cmd_interrupt(struct atmel_mci *host, u32 status)
1472 {
1473 mci_writel(host, IDR, MCI_CMDRDY);
1474
1475 host->cmd_status = status;
1476 smp_wmb();
1477 atmci_set_pending(host, EVENT_CMD_COMPLETE);
1478 tasklet_schedule(&host->tasklet);
1479 }
1480
1481 static irqreturn_t atmci_interrupt(int irq, void *dev_id)
1482 {
1483 struct atmel_mci *host = dev_id;
1484 u32 status, mask, pending;
1485 unsigned int pass_count = 0;
1486
1487 do {
1488 status = mci_readl(host, SR);
1489 mask = mci_readl(host, IMR);
1490 pending = status & mask;
1491 if (!pending)
1492 break;
1493
1494 if (pending & ATMCI_DATA_ERROR_FLAGS) {
1495 mci_writel(host, IDR, ATMCI_DATA_ERROR_FLAGS
1496 | MCI_RXRDY | MCI_TXRDY);
1497 pending &= mci_readl(host, IMR);
1498
1499 host->data_status = status;
1500 smp_wmb();
1501 atmci_set_pending(host, EVENT_DATA_ERROR);
1502 tasklet_schedule(&host->tasklet);
1503 }
1504 if (pending & MCI_NOTBUSY) {
1505 mci_writel(host, IDR,
1506 ATMCI_DATA_ERROR_FLAGS | MCI_NOTBUSY);
1507 if (!host->data_status)
1508 host->data_status = status;
1509 smp_wmb();
1510 atmci_set_pending(host, EVENT_DATA_COMPLETE);
1511 tasklet_schedule(&host->tasklet);
1512 }
1513 if (pending & MCI_RXRDY)
1514 atmci_read_data_pio(host);
1515 if (pending & MCI_TXRDY)
1516 atmci_write_data_pio(host);
1517
1518 if (pending & MCI_CMDRDY)
1519 atmci_cmd_interrupt(host, status);
1520 } while (pass_count++ < 5);
1521
1522 return pass_count ? IRQ_HANDLED : IRQ_NONE;
1523 }
1524
1525 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
1526 {
1527 struct atmel_mci_slot *slot = dev_id;
1528
1529 /*
1530 * Disable interrupts until the pin has stabilized and check
1531 * the state then. Use mod_timer() since we may be in the
1532 * middle of the timer routine when this interrupt triggers.
1533 */
1534 disable_irq_nosync(irq);
1535 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
1536
1537 return IRQ_HANDLED;
1538 }
1539
1540 static int __init atmci_init_slot(struct atmel_mci *host,
1541 struct mci_slot_pdata *slot_data, unsigned int id,
1542 u32 sdc_reg)
1543 {
1544 struct mmc_host *mmc;
1545 struct atmel_mci_slot *slot;
1546
1547 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
1548 if (!mmc)
1549 return -ENOMEM;
1550
1551 slot = mmc_priv(mmc);
1552 slot->mmc = mmc;
1553 slot->host = host;
1554 slot->detect_pin = slot_data->detect_pin;
1555 slot->wp_pin = slot_data->wp_pin;
1556 slot->detect_is_active_high = slot_data->detect_is_active_high;
1557 slot->sdc_reg = sdc_reg;
1558
1559 mmc->ops = &atmci_ops;
1560 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
1561 mmc->f_max = host->bus_hz / 2;
1562 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1563 if (slot_data->bus_width >= 4)
1564 mmc->caps |= MMC_CAP_4_BIT_DATA;
1565
1566 mmc->max_hw_segs = 64;
1567 mmc->max_phys_segs = 64;
1568 mmc->max_req_size = 32768 * 512;
1569 mmc->max_blk_size = 32768;
1570 mmc->max_blk_count = 512;
1571
1572 /* Assume card is present initially */
1573 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1574 if (gpio_is_valid(slot->detect_pin)) {
1575 if (gpio_request(slot->detect_pin, "mmc_detect")) {
1576 dev_dbg(&mmc->class_dev, "no detect pin available\n");
1577 slot->detect_pin = -EBUSY;
1578 } else if (gpio_get_value(slot->detect_pin) ^
1579 slot->detect_is_active_high) {
1580 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1581 }
1582 }
1583
1584 if (!gpio_is_valid(slot->detect_pin))
1585 mmc->caps |= MMC_CAP_NEEDS_POLL;
1586
1587 if (gpio_is_valid(slot->wp_pin)) {
1588 if (gpio_request(slot->wp_pin, "mmc_wp")) {
1589 dev_dbg(&mmc->class_dev, "no WP pin available\n");
1590 slot->wp_pin = -EBUSY;
1591 }
1592 }
1593
1594 host->slot[id] = slot;
1595 mmc_add_host(mmc);
1596
1597 if (gpio_is_valid(slot->detect_pin)) {
1598 int ret;
1599
1600 setup_timer(&slot->detect_timer, atmci_detect_change,
1601 (unsigned long)slot);
1602
1603 ret = request_irq(gpio_to_irq(slot->detect_pin),
1604 atmci_detect_interrupt,
1605 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
1606 "mmc-detect", slot);
1607 if (ret) {
1608 dev_dbg(&mmc->class_dev,
1609 "could not request IRQ %d for detect pin\n",
1610 gpio_to_irq(slot->detect_pin));
1611 gpio_free(slot->detect_pin);
1612 slot->detect_pin = -EBUSY;
1613 }
1614 }
1615
1616 atmci_init_debugfs(slot);
1617
1618 return 0;
1619 }
1620
1621 static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot,
1622 unsigned int id)
1623 {
1624 /* Debugfs stuff is cleaned up by mmc core */
1625
1626 set_bit(ATMCI_SHUTDOWN, &slot->flags);
1627 smp_wmb();
1628
1629 mmc_remove_host(slot->mmc);
1630
1631 if (gpio_is_valid(slot->detect_pin)) {
1632 int pin = slot->detect_pin;
1633
1634 free_irq(gpio_to_irq(pin), slot);
1635 del_timer_sync(&slot->detect_timer);
1636 gpio_free(pin);
1637 }
1638 if (gpio_is_valid(slot->wp_pin))
1639 gpio_free(slot->wp_pin);
1640
1641 slot->host->slot[id] = NULL;
1642 mmc_free_host(slot->mmc);
1643 }
1644
1645 #ifdef CONFIG_MMC_ATMELMCI_DMA
1646 static struct device *find_slave_dev(void *slave)
1647 {
1648 if (!slave)
1649 return NULL;
1650
1651 if (cpu_is_at32ap7000())
1652 return ((struct dw_dma_slave *)slave)->dma_dev;
1653 else
1654 return ((struct at_dma_slave *)slave)->dma_dev;
1655 }
1656
1657 static void setup_dma_addr(struct mci_platform_data *pdata,
1658 dma_addr_t tx_addr, dma_addr_t rx_addr)
1659 {
1660 if (!pdata)
1661 return;
1662
1663 if (cpu_is_at32ap7000()) {
1664 struct dw_dma_slave *dws = pdata->dma_slave;
1665
1666 dws->tx_reg = tx_addr;
1667 dws->rx_reg = rx_addr;
1668 } else {
1669 struct at_dma_slave *ats = pdata->dma_slave;
1670
1671 ats->tx_reg = tx_addr;
1672 ats->rx_reg = rx_addr;
1673 }
1674 }
1675
1676 static bool filter(struct dma_chan *chan, void *slave)
1677 {
1678 if (find_slave_dev(slave) == chan->device->dev) {
1679 chan->private = slave;
1680 return true;
1681 } else {
1682 return false;
1683 }
1684 }
1685
1686 static void atmci_configure_dma(struct atmel_mci *host)
1687 {
1688 struct mci_platform_data *pdata;
1689
1690 if (host == NULL)
1691 return;
1692
1693 pdata = host->pdev->dev.platform_data;
1694
1695 if (pdata && find_slave_dev(pdata->dma_slave)) {
1696 dma_cap_mask_t mask;
1697
1698 setup_dma_addr(pdata, host->mapbase + MCI_TDR,
1699 host->mapbase + MCI_RDR);
1700
1701 /* Try to grab a DMA channel */
1702 dma_cap_zero(mask);
1703 dma_cap_set(DMA_SLAVE, mask);
1704 host->dma.chan = dma_request_channel(mask, filter, pdata->dma_slave);
1705 }
1706 if (!host->dma.chan)
1707 dev_notice(&host->pdev->dev, "DMA not available, using PIO\n");
1708 else
1709 dev_info(&host->pdev->dev,
1710 "Using %s for DMA transfers\n",
1711 dma_chan_name(host->dma.chan));
1712 }
1713 #else
1714 static void atmci_configure_dma(struct atmel_mci *host) {}
1715 #endif
1716
1717 static int __init atmci_probe(struct platform_device *pdev)
1718 {
1719 struct mci_platform_data *pdata;
1720 struct atmel_mci *host;
1721 struct resource *regs;
1722 unsigned int nr_slots;
1723 int irq;
1724 int ret;
1725
1726 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1727 if (!regs)
1728 return -ENXIO;
1729 pdata = pdev->dev.platform_data;
1730 if (!pdata)
1731 return -ENXIO;
1732 irq = platform_get_irq(pdev, 0);
1733 if (irq < 0)
1734 return irq;
1735
1736 host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL);
1737 if (!host)
1738 return -ENOMEM;
1739
1740 host->pdev = pdev;
1741 spin_lock_init(&host->lock);
1742 INIT_LIST_HEAD(&host->queue);
1743
1744 host->mck = clk_get(&pdev->dev, "mci_clk");
1745 if (IS_ERR(host->mck)) {
1746 ret = PTR_ERR(host->mck);
1747 goto err_clk_get;
1748 }
1749
1750 ret = -ENOMEM;
1751 host->regs = ioremap(regs->start, regs->end - regs->start + 1);
1752 if (!host->regs)
1753 goto err_ioremap;
1754
1755 clk_enable(host->mck);
1756 mci_writel(host, CR, MCI_CR_SWRST);
1757 host->bus_hz = clk_get_rate(host->mck);
1758 clk_disable(host->mck);
1759
1760 host->mapbase = regs->start;
1761
1762 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
1763
1764 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
1765 if (ret)
1766 goto err_request_irq;
1767
1768 atmci_configure_dma(host);
1769
1770 platform_set_drvdata(pdev, host);
1771
1772 /* We need at least one slot to succeed */
1773 nr_slots = 0;
1774 ret = -ENODEV;
1775 if (pdata->slot[0].bus_width) {
1776 ret = atmci_init_slot(host, &pdata->slot[0],
1777 MCI_SDCSEL_SLOT_A, 0);
1778 if (!ret)
1779 nr_slots++;
1780 }
1781 if (pdata->slot[1].bus_width) {
1782 ret = atmci_init_slot(host, &pdata->slot[1],
1783 MCI_SDCSEL_SLOT_B, 1);
1784 if (!ret)
1785 nr_slots++;
1786 }
1787
1788 if (!nr_slots) {
1789 dev_err(&pdev->dev, "init failed: no slot defined\n");
1790 goto err_init_slot;
1791 }
1792
1793 dev_info(&pdev->dev,
1794 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
1795 host->mapbase, irq, nr_slots);
1796
1797 return 0;
1798
1799 err_init_slot:
1800 #ifdef CONFIG_MMC_ATMELMCI_DMA
1801 if (host->dma.chan)
1802 dma_release_channel(host->dma.chan);
1803 #endif
1804 free_irq(irq, host);
1805 err_request_irq:
1806 iounmap(host->regs);
1807 err_ioremap:
1808 clk_put(host->mck);
1809 err_clk_get:
1810 kfree(host);
1811 return ret;
1812 }
1813
1814 static int __exit atmci_remove(struct platform_device *pdev)
1815 {
1816 struct atmel_mci *host = platform_get_drvdata(pdev);
1817 unsigned int i;
1818
1819 platform_set_drvdata(pdev, NULL);
1820
1821 for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) {
1822 if (host->slot[i])
1823 atmci_cleanup_slot(host->slot[i], i);
1824 }
1825
1826 clk_enable(host->mck);
1827 mci_writel(host, IDR, ~0UL);
1828 mci_writel(host, CR, MCI_CR_MCIDIS);
1829 mci_readl(host, SR);
1830 clk_disable(host->mck);
1831
1832 #ifdef CONFIG_MMC_ATMELMCI_DMA
1833 if (host->dma.chan)
1834 dma_release_channel(host->dma.chan);
1835 #endif
1836
1837 free_irq(platform_get_irq(pdev, 0), host);
1838 iounmap(host->regs);
1839
1840 clk_put(host->mck);
1841 kfree(host);
1842
1843 return 0;
1844 }
1845
1846 static struct platform_driver atmci_driver = {
1847 .remove = __exit_p(atmci_remove),
1848 .driver = {
1849 .name = "atmel_mci",
1850 },
1851 };
1852
1853 static int __init atmci_init(void)
1854 {
1855 return platform_driver_probe(&atmci_driver, atmci_probe);
1856 }
1857
1858 static void __exit atmci_exit(void)
1859 {
1860 platform_driver_unregister(&atmci_driver);
1861 }
1862
1863 late_initcall(atmci_init); /* try to load after dma driver when built-in */
1864 module_exit(atmci_exit);
1865
1866 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
1867 MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen@atmel.com>");
1868 MODULE_LICENSE("GPL v2");
mm of the moment repository