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On Tue, Nov 06, 2007 at 02:33:53AM -0800, akpm@linux-foundation.org wrote:
[mmotm.git] / drivers / net / igb / igb_ethtool.c
blobdd94992242e0f3bf26059e01c18b1bac4ca06a8f
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* ethtool support for igb */
29
30 #include <linux/vmalloc.h>
31 #include <linux/netdevice.h>
32 #include <linux/pci.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/if_ether.h>
36 #include <linux/ethtool.h>
37 #include <linux/sched.h>
38
39 #include "igb.h"
40
41 struct igb_stats {
42 char stat_string[ETH_GSTRING_LEN];
43 int sizeof_stat;
44 int stat_offset;
45 };
46
47 #define IGB_STAT(m) FIELD_SIZEOF(struct igb_adapter, m), \
48 offsetof(struct igb_adapter, m)
49 #define IGB_NETDEV_STAT(m) FIELD_SIZEOF(struct net_device, m), \
50 offsetof(struct net_device, m)
51 static const struct igb_stats igb_gstrings_stats[] = {
52 { "rx_packets", IGB_STAT(stats.gprc) },
53 { "tx_packets", IGB_STAT(stats.gptc) },
54 { "rx_bytes", IGB_STAT(stats.gorc) },
55 { "tx_bytes", IGB_STAT(stats.gotc) },
56 { "rx_broadcast", IGB_STAT(stats.bprc) },
57 { "tx_broadcast", IGB_STAT(stats.bptc) },
58 { "rx_multicast", IGB_STAT(stats.mprc) },
59 { "tx_multicast", IGB_STAT(stats.mptc) },
60 { "rx_errors", IGB_NETDEV_STAT(stats.rx_errors) },
61 { "tx_errors", IGB_NETDEV_STAT(stats.tx_errors) },
62 { "tx_dropped", IGB_NETDEV_STAT(stats.tx_dropped) },
63 { "multicast", IGB_STAT(stats.mprc) },
64 { "collisions", IGB_STAT(stats.colc) },
65 { "rx_length_errors", IGB_NETDEV_STAT(stats.rx_length_errors) },
66 { "rx_over_errors", IGB_NETDEV_STAT(stats.rx_over_errors) },
67 { "rx_crc_errors", IGB_STAT(stats.crcerrs) },
68 { "rx_frame_errors", IGB_NETDEV_STAT(stats.rx_frame_errors) },
69 { "rx_no_buffer_count", IGB_STAT(stats.rnbc) },
70 { "rx_queue_drop_packet_count", IGB_NETDEV_STAT(stats.rx_fifo_errors) },
71 { "rx_missed_errors", IGB_STAT(stats.mpc) },
72 { "tx_aborted_errors", IGB_STAT(stats.ecol) },
73 { "tx_carrier_errors", IGB_STAT(stats.tncrs) },
74 { "tx_fifo_errors", IGB_NETDEV_STAT(stats.tx_fifo_errors) },
75 { "tx_heartbeat_errors", IGB_NETDEV_STAT(stats.tx_heartbeat_errors) },
76 { "tx_window_errors", IGB_STAT(stats.latecol) },
77 { "tx_abort_late_coll", IGB_STAT(stats.latecol) },
78 { "tx_deferred_ok", IGB_STAT(stats.dc) },
79 { "tx_single_coll_ok", IGB_STAT(stats.scc) },
80 { "tx_multi_coll_ok", IGB_STAT(stats.mcc) },
81 { "tx_timeout_count", IGB_STAT(tx_timeout_count) },
82 { "tx_restart_queue", IGB_STAT(restart_queue) },
83 { "rx_long_length_errors", IGB_STAT(stats.roc) },
84 { "rx_short_length_errors", IGB_STAT(stats.ruc) },
85 { "rx_align_errors", IGB_STAT(stats.algnerrc) },
86 { "tx_tcp_seg_good", IGB_STAT(stats.tsctc) },
87 { "tx_tcp_seg_failed", IGB_STAT(stats.tsctfc) },
88 { "rx_flow_control_xon", IGB_STAT(stats.xonrxc) },
89 { "rx_flow_control_xoff", IGB_STAT(stats.xoffrxc) },
90 { "tx_flow_control_xon", IGB_STAT(stats.xontxc) },
91 { "tx_flow_control_xoff", IGB_STAT(stats.xofftxc) },
92 { "rx_long_byte_count", IGB_STAT(stats.gorc) },
93 { "rx_csum_offload_good", IGB_STAT(hw_csum_good) },
94 { "rx_csum_offload_errors", IGB_STAT(hw_csum_err) },
95 { "tx_dma_out_of_sync", IGB_STAT(stats.doosync) },
96 { "alloc_rx_buff_failed", IGB_STAT(alloc_rx_buff_failed) },
97 { "tx_smbus", IGB_STAT(stats.mgptc) },
98 { "rx_smbus", IGB_STAT(stats.mgprc) },
99 { "dropped_smbus", IGB_STAT(stats.mgpdc) },
100 };
101
102 #define IGB_QUEUE_STATS_LEN \
103 (((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues)* \
104 (sizeof(struct igb_rx_queue_stats) / sizeof(u64))) + \
105 ((((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues) * \
106 (sizeof(struct igb_tx_queue_stats) / sizeof(u64))))
107 #define IGB_GLOBAL_STATS_LEN \
108 sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)
109 #define IGB_STATS_LEN (IGB_GLOBAL_STATS_LEN + IGB_QUEUE_STATS_LEN)
110 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
111 "Register test (offline)", "Eeprom test (offline)",
112 "Interrupt test (offline)", "Loopback test (offline)",
113 "Link test (on/offline)"
114 };
115 #define IGB_TEST_LEN sizeof(igb_gstrings_test) / ETH_GSTRING_LEN
116
117 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
118 {
119 struct igb_adapter *adapter = netdev_priv(netdev);
120 struct e1000_hw *hw = &adapter->hw;
121
122 if (hw->phy.media_type == e1000_media_type_copper) {
123
124 ecmd->supported = (SUPPORTED_10baseT_Half |
125 SUPPORTED_10baseT_Full |
126 SUPPORTED_100baseT_Half |
127 SUPPORTED_100baseT_Full |
128 SUPPORTED_1000baseT_Full|
129 SUPPORTED_Autoneg |
130 SUPPORTED_TP);
131 ecmd->advertising = ADVERTISED_TP;
132
133 if (hw->mac.autoneg == 1) {
134 ecmd->advertising |= ADVERTISED_Autoneg;
135 /* the e1000 autoneg seems to match ethtool nicely */
136 ecmd->advertising |= hw->phy.autoneg_advertised;
137 }
138
139 ecmd->port = PORT_TP;
140 ecmd->phy_address = hw->phy.addr;
141 } else {
142 ecmd->supported = (SUPPORTED_1000baseT_Full |
143 SUPPORTED_FIBRE |
144 SUPPORTED_Autoneg);
145
146 ecmd->advertising = (ADVERTISED_1000baseT_Full |
147 ADVERTISED_FIBRE |
148 ADVERTISED_Autoneg);
149
150 ecmd->port = PORT_FIBRE;
151 }
152
153 ecmd->transceiver = XCVR_INTERNAL;
154
155 if (rd32(E1000_STATUS) & E1000_STATUS_LU) {
156
157 adapter->hw.mac.ops.get_speed_and_duplex(hw,
158 &adapter->link_speed,
159 &adapter->link_duplex);
160 ecmd->speed = adapter->link_speed;
161
162 /* unfortunately FULL_DUPLEX != DUPLEX_FULL
163 * and HALF_DUPLEX != DUPLEX_HALF */
164
165 if (adapter->link_duplex == FULL_DUPLEX)
166 ecmd->duplex = DUPLEX_FULL;
167 else
168 ecmd->duplex = DUPLEX_HALF;
169 } else {
170 ecmd->speed = -1;
171 ecmd->duplex = -1;
172 }
173
174 ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
175 return 0;
176 }
177
178 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
179 {
180 struct igb_adapter *adapter = netdev_priv(netdev);
181 struct e1000_hw *hw = &adapter->hw;
182
183 /* When SoL/IDER sessions are active, autoneg/speed/duplex
184 * cannot be changed */
185 if (igb_check_reset_block(hw)) {
186 dev_err(&adapter->pdev->dev, "Cannot change link "
187 "characteristics when SoL/IDER is active.\n");
188 return -EINVAL;
189 }
190
191 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
192 msleep(1);
193
194 if (ecmd->autoneg == AUTONEG_ENABLE) {
195 hw->mac.autoneg = 1;
196 hw->phy.autoneg_advertised = ecmd->advertising |
197 ADVERTISED_TP |
198 ADVERTISED_Autoneg;
199 ecmd->advertising = hw->phy.autoneg_advertised;
200 if (adapter->fc_autoneg)
201 hw->fc.requested_mode = e1000_fc_default;
202 } else {
203 if (igb_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
204 clear_bit(__IGB_RESETTING, &adapter->state);
205 return -EINVAL;
206 }
207 }
208
209 /* reset the link */
210 if (netif_running(adapter->netdev)) {
211 igb_down(adapter);
212 igb_up(adapter);
213 } else
214 igb_reset(adapter);
215
216 clear_bit(__IGB_RESETTING, &adapter->state);
217 return 0;
218 }
219
220 static void igb_get_pauseparam(struct net_device *netdev,
221 struct ethtool_pauseparam *pause)
222 {
223 struct igb_adapter *adapter = netdev_priv(netdev);
224 struct e1000_hw *hw = &adapter->hw;
225
226 pause->autoneg =
227 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
228
229 if (hw->fc.current_mode == e1000_fc_rx_pause)
230 pause->rx_pause = 1;
231 else if (hw->fc.current_mode == e1000_fc_tx_pause)
232 pause->tx_pause = 1;
233 else if (hw->fc.current_mode == e1000_fc_full) {
234 pause->rx_pause = 1;
235 pause->tx_pause = 1;
236 }
237 }
238
239 static int igb_set_pauseparam(struct net_device *netdev,
240 struct ethtool_pauseparam *pause)
241 {
242 struct igb_adapter *adapter = netdev_priv(netdev);
243 struct e1000_hw *hw = &adapter->hw;
244 int retval = 0;
245
246 adapter->fc_autoneg = pause->autoneg;
247
248 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
249 msleep(1);
250
251 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
252 hw->fc.requested_mode = e1000_fc_default;
253 if (netif_running(adapter->netdev)) {
254 igb_down(adapter);
255 igb_up(adapter);
256 } else
257 igb_reset(adapter);
258 } else {
259 if (pause->rx_pause && pause->tx_pause)
260 hw->fc.requested_mode = e1000_fc_full;
261 else if (pause->rx_pause && !pause->tx_pause)
262 hw->fc.requested_mode = e1000_fc_rx_pause;
263 else if (!pause->rx_pause && pause->tx_pause)
264 hw->fc.requested_mode = e1000_fc_tx_pause;
265 else if (!pause->rx_pause && !pause->tx_pause)
266 hw->fc.requested_mode = e1000_fc_none;
267
268 hw->fc.current_mode = hw->fc.requested_mode;
269
270 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
271 igb_force_mac_fc(hw) : igb_setup_link(hw));
272 }
273
274 clear_bit(__IGB_RESETTING, &adapter->state);
275 return retval;
276 }
277
278 static u32 igb_get_rx_csum(struct net_device *netdev)
279 {
280 struct igb_adapter *adapter = netdev_priv(netdev);
281 return !(adapter->flags & IGB_FLAG_RX_CSUM_DISABLED);
282 }
283
284 static int igb_set_rx_csum(struct net_device *netdev, u32 data)
285 {
286 struct igb_adapter *adapter = netdev_priv(netdev);
287
288 if (data)
289 adapter->flags &= ~IGB_FLAG_RX_CSUM_DISABLED;
290 else
291 adapter->flags |= IGB_FLAG_RX_CSUM_DISABLED;
292
293 return 0;
294 }
295
296 static u32 igb_get_tx_csum(struct net_device *netdev)
297 {
298 return (netdev->features & NETIF_F_IP_CSUM) != 0;
299 }
300
301 static int igb_set_tx_csum(struct net_device *netdev, u32 data)
302 {
303 struct igb_adapter *adapter = netdev_priv(netdev);
304
305 if (data) {
306 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
307 if (adapter->hw.mac.type == e1000_82576)
308 netdev->features |= NETIF_F_SCTP_CSUM;
309 } else {
310 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
311 NETIF_F_SCTP_CSUM);
312 }
313
314 return 0;
315 }
316
317 static int igb_set_tso(struct net_device *netdev, u32 data)
318 {
319 struct igb_adapter *adapter = netdev_priv(netdev);
320
321 if (data) {
322 netdev->features |= NETIF_F_TSO;
323 netdev->features |= NETIF_F_TSO6;
324 } else {
325 netdev->features &= ~NETIF_F_TSO;
326 netdev->features &= ~NETIF_F_TSO6;
327 }
328
329 dev_info(&adapter->pdev->dev, "TSO is %s\n",
330 data ? "Enabled" : "Disabled");
331 return 0;
332 }
333
334 static u32 igb_get_msglevel(struct net_device *netdev)
335 {
336 struct igb_adapter *adapter = netdev_priv(netdev);
337 return adapter->msg_enable;
338 }
339
340 static void igb_set_msglevel(struct net_device *netdev, u32 data)
341 {
342 struct igb_adapter *adapter = netdev_priv(netdev);
343 adapter->msg_enable = data;
344 }
345
346 static int igb_get_regs_len(struct net_device *netdev)
347 {
348 #define IGB_REGS_LEN 551
349 return IGB_REGS_LEN * sizeof(u32);
350 }
351
352 static void igb_get_regs(struct net_device *netdev,
353 struct ethtool_regs *regs, void *p)
354 {
355 struct igb_adapter *adapter = netdev_priv(netdev);
356 struct e1000_hw *hw = &adapter->hw;
357 u32 *regs_buff = p;
358 u8 i;
359
360 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
361
362 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
363
364 /* General Registers */
365 regs_buff[0] = rd32(E1000_CTRL);
366 regs_buff[1] = rd32(E1000_STATUS);
367 regs_buff[2] = rd32(E1000_CTRL_EXT);
368 regs_buff[3] = rd32(E1000_MDIC);
369 regs_buff[4] = rd32(E1000_SCTL);
370 regs_buff[5] = rd32(E1000_CONNSW);
371 regs_buff[6] = rd32(E1000_VET);
372 regs_buff[7] = rd32(E1000_LEDCTL);
373 regs_buff[8] = rd32(E1000_PBA);
374 regs_buff[9] = rd32(E1000_PBS);
375 regs_buff[10] = rd32(E1000_FRTIMER);
376 regs_buff[11] = rd32(E1000_TCPTIMER);
377
378 /* NVM Register */
379 regs_buff[12] = rd32(E1000_EECD);
380
381 /* Interrupt */
382 /* Reading EICS for EICR because they read the
383 * same but EICS does not clear on read */
384 regs_buff[13] = rd32(E1000_EICS);
385 regs_buff[14] = rd32(E1000_EICS);
386 regs_buff[15] = rd32(E1000_EIMS);
387 regs_buff[16] = rd32(E1000_EIMC);
388 regs_buff[17] = rd32(E1000_EIAC);
389 regs_buff[18] = rd32(E1000_EIAM);
390 /* Reading ICS for ICR because they read the
391 * same but ICS does not clear on read */
392 regs_buff[19] = rd32(E1000_ICS);
393 regs_buff[20] = rd32(E1000_ICS);
394 regs_buff[21] = rd32(E1000_IMS);
395 regs_buff[22] = rd32(E1000_IMC);
396 regs_buff[23] = rd32(E1000_IAC);
397 regs_buff[24] = rd32(E1000_IAM);
398 regs_buff[25] = rd32(E1000_IMIRVP);
399
400 /* Flow Control */
401 regs_buff[26] = rd32(E1000_FCAL);
402 regs_buff[27] = rd32(E1000_FCAH);
403 regs_buff[28] = rd32(E1000_FCTTV);
404 regs_buff[29] = rd32(E1000_FCRTL);
405 regs_buff[30] = rd32(E1000_FCRTH);
406 regs_buff[31] = rd32(E1000_FCRTV);
407
408 /* Receive */
409 regs_buff[32] = rd32(E1000_RCTL);
410 regs_buff[33] = rd32(E1000_RXCSUM);
411 regs_buff[34] = rd32(E1000_RLPML);
412 regs_buff[35] = rd32(E1000_RFCTL);
413 regs_buff[36] = rd32(E1000_MRQC);
414 regs_buff[37] = rd32(E1000_VT_CTL);
415
416 /* Transmit */
417 regs_buff[38] = rd32(E1000_TCTL);
418 regs_buff[39] = rd32(E1000_TCTL_EXT);
419 regs_buff[40] = rd32(E1000_TIPG);
420 regs_buff[41] = rd32(E1000_DTXCTL);
421
422 /* Wake Up */
423 regs_buff[42] = rd32(E1000_WUC);
424 regs_buff[43] = rd32(E1000_WUFC);
425 regs_buff[44] = rd32(E1000_WUS);
426 regs_buff[45] = rd32(E1000_IPAV);
427 regs_buff[46] = rd32(E1000_WUPL);
428
429 /* MAC */
430 regs_buff[47] = rd32(E1000_PCS_CFG0);
431 regs_buff[48] = rd32(E1000_PCS_LCTL);
432 regs_buff[49] = rd32(E1000_PCS_LSTAT);
433 regs_buff[50] = rd32(E1000_PCS_ANADV);
434 regs_buff[51] = rd32(E1000_PCS_LPAB);
435 regs_buff[52] = rd32(E1000_PCS_NPTX);
436 regs_buff[53] = rd32(E1000_PCS_LPABNP);
437
438 /* Statistics */
439 regs_buff[54] = adapter->stats.crcerrs;
440 regs_buff[55] = adapter->stats.algnerrc;
441 regs_buff[56] = adapter->stats.symerrs;
442 regs_buff[57] = adapter->stats.rxerrc;
443 regs_buff[58] = adapter->stats.mpc;
444 regs_buff[59] = adapter->stats.scc;
445 regs_buff[60] = adapter->stats.ecol;
446 regs_buff[61] = adapter->stats.mcc;
447 regs_buff[62] = adapter->stats.latecol;
448 regs_buff[63] = adapter->stats.colc;
449 regs_buff[64] = adapter->stats.dc;
450 regs_buff[65] = adapter->stats.tncrs;
451 regs_buff[66] = adapter->stats.sec;
452 regs_buff[67] = adapter->stats.htdpmc;
453 regs_buff[68] = adapter->stats.rlec;
454 regs_buff[69] = adapter->stats.xonrxc;
455 regs_buff[70] = adapter->stats.xontxc;
456 regs_buff[71] = adapter->stats.xoffrxc;
457 regs_buff[72] = adapter->stats.xofftxc;
458 regs_buff[73] = adapter->stats.fcruc;
459 regs_buff[74] = adapter->stats.prc64;
460 regs_buff[75] = adapter->stats.prc127;
461 regs_buff[76] = adapter->stats.prc255;
462 regs_buff[77] = adapter->stats.prc511;
463 regs_buff[78] = adapter->stats.prc1023;
464 regs_buff[79] = adapter->stats.prc1522;
465 regs_buff[80] = adapter->stats.gprc;
466 regs_buff[81] = adapter->stats.bprc;
467 regs_buff[82] = adapter->stats.mprc;
468 regs_buff[83] = adapter->stats.gptc;
469 regs_buff[84] = adapter->stats.gorc;
470 regs_buff[86] = adapter->stats.gotc;
471 regs_buff[88] = adapter->stats.rnbc;
472 regs_buff[89] = adapter->stats.ruc;
473 regs_buff[90] = adapter->stats.rfc;
474 regs_buff[91] = adapter->stats.roc;
475 regs_buff[92] = adapter->stats.rjc;
476 regs_buff[93] = adapter->stats.mgprc;
477 regs_buff[94] = adapter->stats.mgpdc;
478 regs_buff[95] = adapter->stats.mgptc;
479 regs_buff[96] = adapter->stats.tor;
480 regs_buff[98] = adapter->stats.tot;
481 regs_buff[100] = adapter->stats.tpr;
482 regs_buff[101] = adapter->stats.tpt;
483 regs_buff[102] = adapter->stats.ptc64;
484 regs_buff[103] = adapter->stats.ptc127;
485 regs_buff[104] = adapter->stats.ptc255;
486 regs_buff[105] = adapter->stats.ptc511;
487 regs_buff[106] = adapter->stats.ptc1023;
488 regs_buff[107] = adapter->stats.ptc1522;
489 regs_buff[108] = adapter->stats.mptc;
490 regs_buff[109] = adapter->stats.bptc;
491 regs_buff[110] = adapter->stats.tsctc;
492 regs_buff[111] = adapter->stats.iac;
493 regs_buff[112] = adapter->stats.rpthc;
494 regs_buff[113] = adapter->stats.hgptc;
495 regs_buff[114] = adapter->stats.hgorc;
496 regs_buff[116] = adapter->stats.hgotc;
497 regs_buff[118] = adapter->stats.lenerrs;
498 regs_buff[119] = adapter->stats.scvpc;
499 regs_buff[120] = adapter->stats.hrmpc;
500
501 /* These should probably be added to e1000_regs.h instead */
502 #define E1000_PSRTYPE_REG(_i) (0x05480 + ((_i) * 4))
503 #define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8))
504 #define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4))
505 #define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4))
506 #define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8))
507 #define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8))
508 #define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8))
509
510 for (i = 0; i < 4; i++)
511 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
512 for (i = 0; i < 4; i++)
513 regs_buff[125 + i] = rd32(E1000_PSRTYPE_REG(i));
514 for (i = 0; i < 4; i++)
515 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
516 for (i = 0; i < 4; i++)
517 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
518 for (i = 0; i < 4; i++)
519 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
520 for (i = 0; i < 4; i++)
521 regs_buff[141 + i] = rd32(E1000_RDH(i));
522 for (i = 0; i < 4; i++)
523 regs_buff[145 + i] = rd32(E1000_RDT(i));
524 for (i = 0; i < 4; i++)
525 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
526
527 for (i = 0; i < 10; i++)
528 regs_buff[153 + i] = rd32(E1000_EITR(i));
529 for (i = 0; i < 8; i++)
530 regs_buff[163 + i] = rd32(E1000_IMIR(i));
531 for (i = 0; i < 8; i++)
532 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
533 for (i = 0; i < 16; i++)
534 regs_buff[179 + i] = rd32(E1000_RAL(i));
535 for (i = 0; i < 16; i++)
536 regs_buff[195 + i] = rd32(E1000_RAH(i));
537
538 for (i = 0; i < 4; i++)
539 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
540 for (i = 0; i < 4; i++)
541 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
542 for (i = 0; i < 4; i++)
543 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
544 for (i = 0; i < 4; i++)
545 regs_buff[223 + i] = rd32(E1000_TDH(i));
546 for (i = 0; i < 4; i++)
547 regs_buff[227 + i] = rd32(E1000_TDT(i));
548 for (i = 0; i < 4; i++)
549 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
550 for (i = 0; i < 4; i++)
551 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
552 for (i = 0; i < 4; i++)
553 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
554 for (i = 0; i < 4; i++)
555 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
556
557 for (i = 0; i < 4; i++)
558 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
559 for (i = 0; i < 4; i++)
560 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
561 for (i = 0; i < 32; i++)
562 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
563 for (i = 0; i < 128; i++)
564 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
565 for (i = 0; i < 128; i++)
566 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
567 for (i = 0; i < 4; i++)
568 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
569
570 regs_buff[547] = rd32(E1000_TDFH);
571 regs_buff[548] = rd32(E1000_TDFT);
572 regs_buff[549] = rd32(E1000_TDFHS);
573 regs_buff[550] = rd32(E1000_TDFPC);
574
575 }
576
577 static int igb_get_eeprom_len(struct net_device *netdev)
578 {
579 struct igb_adapter *adapter = netdev_priv(netdev);
580 return adapter->hw.nvm.word_size * 2;
581 }
582
583 static int igb_get_eeprom(struct net_device *netdev,
584 struct ethtool_eeprom *eeprom, u8 *bytes)
585 {
586 struct igb_adapter *adapter = netdev_priv(netdev);
587 struct e1000_hw *hw = &adapter->hw;
588 u16 *eeprom_buff;
589 int first_word, last_word;
590 int ret_val = 0;
591 u16 i;
592
593 if (eeprom->len == 0)
594 return -EINVAL;
595
596 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
597
598 first_word = eeprom->offset >> 1;
599 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
600
601 eeprom_buff = kmalloc(sizeof(u16) *
602 (last_word - first_word + 1), GFP_KERNEL);
603 if (!eeprom_buff)
604 return -ENOMEM;
605
606 if (hw->nvm.type == e1000_nvm_eeprom_spi)
607 ret_val = hw->nvm.ops.read(hw, first_word,
608 last_word - first_word + 1,
609 eeprom_buff);
610 else {
611 for (i = 0; i < last_word - first_word + 1; i++) {
612 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
613 &eeprom_buff[i]);
614 if (ret_val)
615 break;
616 }
617 }
618
619 /* Device's eeprom is always little-endian, word addressable */
620 for (i = 0; i < last_word - first_word + 1; i++)
621 le16_to_cpus(&eeprom_buff[i]);
622
623 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
624 eeprom->len);
625 kfree(eeprom_buff);
626
627 return ret_val;
628 }
629
630 static int igb_set_eeprom(struct net_device *netdev,
631 struct ethtool_eeprom *eeprom, u8 *bytes)
632 {
633 struct igb_adapter *adapter = netdev_priv(netdev);
634 struct e1000_hw *hw = &adapter->hw;
635 u16 *eeprom_buff;
636 void *ptr;
637 int max_len, first_word, last_word, ret_val = 0;
638 u16 i;
639
640 if (eeprom->len == 0)
641 return -EOPNOTSUPP;
642
643 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
644 return -EFAULT;
645
646 max_len = hw->nvm.word_size * 2;
647
648 first_word = eeprom->offset >> 1;
649 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
650 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
651 if (!eeprom_buff)
652 return -ENOMEM;
653
654 ptr = (void *)eeprom_buff;
655
656 if (eeprom->offset & 1) {
657 /* need read/modify/write of first changed EEPROM word */
658 /* only the second byte of the word is being modified */
659 ret_val = hw->nvm.ops.read(hw, first_word, 1,
660 &eeprom_buff[0]);
661 ptr++;
662 }
663 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
664 /* need read/modify/write of last changed EEPROM word */
665 /* only the first byte of the word is being modified */
666 ret_val = hw->nvm.ops.read(hw, last_word, 1,
667 &eeprom_buff[last_word - first_word]);
668 }
669
670 /* Device's eeprom is always little-endian, word addressable */
671 for (i = 0; i < last_word - first_word + 1; i++)
672 le16_to_cpus(&eeprom_buff[i]);
673
674 memcpy(ptr, bytes, eeprom->len);
675
676 for (i = 0; i < last_word - first_word + 1; i++)
677 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
678
679 ret_val = hw->nvm.ops.write(hw, first_word,
680 last_word - first_word + 1, eeprom_buff);
681
682 /* Update the checksum over the first part of the EEPROM if needed
683 * and flush shadow RAM for 82573 controllers */
684 if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
685 igb_update_nvm_checksum(hw);
686
687 kfree(eeprom_buff);
688 return ret_val;
689 }
690
691 static void igb_get_drvinfo(struct net_device *netdev,
692 struct ethtool_drvinfo *drvinfo)
693 {
694 struct igb_adapter *adapter = netdev_priv(netdev);
695 char firmware_version[32];
696 u16 eeprom_data;
697
698 strncpy(drvinfo->driver, igb_driver_name, 32);
699 strncpy(drvinfo->version, igb_driver_version, 32);
700
701 /* EEPROM image version # is reported as firmware version # for
702 * 82575 controllers */
703 adapter->hw.nvm.ops.read(&adapter->hw, 5, 1, &eeprom_data);
704 sprintf(firmware_version, "%d.%d-%d",
705 (eeprom_data & 0xF000) >> 12,
706 (eeprom_data & 0x0FF0) >> 4,
707 eeprom_data & 0x000F);
708
709 strncpy(drvinfo->fw_version, firmware_version, 32);
710 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
711 drvinfo->n_stats = IGB_STATS_LEN;
712 drvinfo->testinfo_len = IGB_TEST_LEN;
713 drvinfo->regdump_len = igb_get_regs_len(netdev);
714 drvinfo->eedump_len = igb_get_eeprom_len(netdev);
715 }
716
717 static void igb_get_ringparam(struct net_device *netdev,
718 struct ethtool_ringparam *ring)
719 {
720 struct igb_adapter *adapter = netdev_priv(netdev);
721
722 ring->rx_max_pending = IGB_MAX_RXD;
723 ring->tx_max_pending = IGB_MAX_TXD;
724 ring->rx_mini_max_pending = 0;
725 ring->rx_jumbo_max_pending = 0;
726 ring->rx_pending = adapter->rx_ring_count;
727 ring->tx_pending = adapter->tx_ring_count;
728 ring->rx_mini_pending = 0;
729 ring->rx_jumbo_pending = 0;
730 }
731
732 static int igb_set_ringparam(struct net_device *netdev,
733 struct ethtool_ringparam *ring)
734 {
735 struct igb_adapter *adapter = netdev_priv(netdev);
736 struct igb_ring *temp_ring;
737 int i, err;
738 u32 new_rx_count, new_tx_count;
739
740 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
741 return -EINVAL;
742
743 new_rx_count = max(ring->rx_pending, (u32)IGB_MIN_RXD);
744 new_rx_count = min(new_rx_count, (u32)IGB_MAX_RXD);
745 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
746
747 new_tx_count = max(ring->tx_pending, (u32)IGB_MIN_TXD);
748 new_tx_count = min(new_tx_count, (u32)IGB_MAX_TXD);
749 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
750
751 if ((new_tx_count == adapter->tx_ring_count) &&
752 (new_rx_count == adapter->rx_ring_count)) {
753 /* nothing to do */
754 return 0;
755 }
756
757 if (adapter->num_tx_queues > adapter->num_rx_queues)
758 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring));
759 else
760 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring));
761 if (!temp_ring)
762 return -ENOMEM;
763
764 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
765 msleep(1);
766
767 if (netif_running(adapter->netdev))
768 igb_down(adapter);
769
770 /*
771 * We can't just free everything and then setup again,
772 * because the ISRs in MSI-X mode get passed pointers
773 * to the tx and rx ring structs.
774 */
775 if (new_tx_count != adapter->tx_ring_count) {
776 memcpy(temp_ring, adapter->tx_ring,
777 adapter->num_tx_queues * sizeof(struct igb_ring));
778
779 for (i = 0; i < adapter->num_tx_queues; i++) {
780 temp_ring[i].count = new_tx_count;
781 err = igb_setup_tx_resources(adapter, &temp_ring[i]);
782 if (err) {
783 while (i) {
784 i--;
785 igb_free_tx_resources(&temp_ring[i]);
786 }
787 goto err_setup;
788 }
789 }
790
791 for (i = 0; i < adapter->num_tx_queues; i++)
792 igb_free_tx_resources(&adapter->tx_ring[i]);
793
794 memcpy(adapter->tx_ring, temp_ring,
795 adapter->num_tx_queues * sizeof(struct igb_ring));
796
797 adapter->tx_ring_count = new_tx_count;
798 }
799
800 if (new_rx_count != adapter->rx_ring->count) {
801 memcpy(temp_ring, adapter->rx_ring,
802 adapter->num_rx_queues * sizeof(struct igb_ring));
803
804 for (i = 0; i < adapter->num_rx_queues; i++) {
805 temp_ring[i].count = new_rx_count;
806 err = igb_setup_rx_resources(adapter, &temp_ring[i]);
807 if (err) {
808 while (i) {
809 i--;
810 igb_free_rx_resources(&temp_ring[i]);
811 }
812 goto err_setup;
813 }
814
815 }
816
817 for (i = 0; i < adapter->num_rx_queues; i++)
818 igb_free_rx_resources(&adapter->rx_ring[i]);
819
820 memcpy(adapter->rx_ring, temp_ring,
821 adapter->num_rx_queues * sizeof(struct igb_ring));
822
823 adapter->rx_ring_count = new_rx_count;
824 }
825
826 err = 0;
827 err_setup:
828 if (netif_running(adapter->netdev))
829 igb_up(adapter);
830
831 clear_bit(__IGB_RESETTING, &adapter->state);
832 vfree(temp_ring);
833 return err;
834 }
835
836 /* ethtool register test data */
837 struct igb_reg_test {
838 u16 reg;
839 u16 reg_offset;
840 u16 array_len;
841 u16 test_type;
842 u32 mask;
843 u32 write;
844 };
845
846 /* In the hardware, registers are laid out either singly, in arrays
847 * spaced 0x100 bytes apart, or in contiguous tables. We assume
848 * most tests take place on arrays or single registers (handled
849 * as a single-element array) and special-case the tables.
850 * Table tests are always pattern tests.
851 *
852 * We also make provision for some required setup steps by specifying
853 * registers to be written without any read-back testing.
854 */
855
856 #define PATTERN_TEST 1
857 #define SET_READ_TEST 2
858 #define WRITE_NO_TEST 3
859 #define TABLE32_TEST 4
860 #define TABLE64_TEST_LO 5
861 #define TABLE64_TEST_HI 6
862
863 /* 82576 reg test */
864 static struct igb_reg_test reg_test_82576[] = {
865 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
866 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
867 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
868 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
869 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
870 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
871 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
872 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
873 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
874 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
875 /* Enable all RX queues before testing. */
876 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
877 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
878 /* RDH is read-only for 82576, only test RDT. */
879 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
880 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
881 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
882 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
883 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
884 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
885 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
886 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
887 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
888 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
889 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
890 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
891 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
892 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
893 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
894 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
895 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
896 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
897 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
898 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
899 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
900 { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
901 { 0, 0, 0, 0 }
902 };
903
904 /* 82575 register test */
905 static struct igb_reg_test reg_test_82575[] = {
906 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
907 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
908 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
909 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
910 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
911 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
912 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
913 /* Enable all four RX queues before testing. */
914 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
915 /* RDH is read-only for 82575, only test RDT. */
916 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
917 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
918 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
919 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
920 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
921 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
922 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
923 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
924 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
925 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
926 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
927 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
928 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
929 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
930 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
931 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
932 { 0, 0, 0, 0 }
933 };
934
935 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
936 int reg, u32 mask, u32 write)
937 {
938 struct e1000_hw *hw = &adapter->hw;
939 u32 pat, val;
940 u32 _test[] =
941 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
942 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
943 wr32(reg, (_test[pat] & write));
944 val = rd32(reg);
945 if (val != (_test[pat] & write & mask)) {
946 dev_err(&adapter->pdev->dev, "pattern test reg %04X "
947 "failed: got 0x%08X expected 0x%08X\n",
948 reg, val, (_test[pat] & write & mask));
949 *data = reg;
950 return 1;
951 }
952 }
953 return 0;
954 }
955
956 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
957 int reg, u32 mask, u32 write)
958 {
959 struct e1000_hw *hw = &adapter->hw;
960 u32 val;
961 wr32(reg, write & mask);
962 val = rd32(reg);
963 if ((write & mask) != (val & mask)) {
964 dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:"
965 " got 0x%08X expected 0x%08X\n", reg,
966 (val & mask), (write & mask));
967 *data = reg;
968 return 1;
969 }
970 return 0;
971 }
972
973 #define REG_PATTERN_TEST(reg, mask, write) \
974 do { \
975 if (reg_pattern_test(adapter, data, reg, mask, write)) \
976 return 1; \
977 } while (0)
978
979 #define REG_SET_AND_CHECK(reg, mask, write) \
980 do { \
981 if (reg_set_and_check(adapter, data, reg, mask, write)) \
982 return 1; \
983 } while (0)
984
985 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
986 {
987 struct e1000_hw *hw = &adapter->hw;
988 struct igb_reg_test *test;
989 u32 value, before, after;
990 u32 i, toggle;
991
992 toggle = 0x7FFFF3FF;
993
994 switch (adapter->hw.mac.type) {
995 case e1000_82576:
996 test = reg_test_82576;
997 break;
998 default:
999 test = reg_test_82575;
1000 break;
1001 }
1002
1003 /* Because the status register is such a special case,
1004 * we handle it separately from the rest of the register
1005 * tests. Some bits are read-only, some toggle, and some
1006 * are writable on newer MACs.
1007 */
1008 before = rd32(E1000_STATUS);
1009 value = (rd32(E1000_STATUS) & toggle);
1010 wr32(E1000_STATUS, toggle);
1011 after = rd32(E1000_STATUS) & toggle;
1012 if (value != after) {
1013 dev_err(&adapter->pdev->dev, "failed STATUS register test "
1014 "got: 0x%08X expected: 0x%08X\n", after, value);
1015 *data = 1;
1016 return 1;
1017 }
1018 /* restore previous status */
1019 wr32(E1000_STATUS, before);
1020
1021 /* Perform the remainder of the register test, looping through
1022 * the test table until we either fail or reach the null entry.
1023 */
1024 while (test->reg) {
1025 for (i = 0; i < test->array_len; i++) {
1026 switch (test->test_type) {
1027 case PATTERN_TEST:
1028 REG_PATTERN_TEST(test->reg +
1029 (i * test->reg_offset),
1030 test->mask,
1031 test->write);
1032 break;
1033 case SET_READ_TEST:
1034 REG_SET_AND_CHECK(test->reg +
1035 (i * test->reg_offset),
1036 test->mask,
1037 test->write);
1038 break;
1039 case WRITE_NO_TEST:
1040 writel(test->write,
1041 (adapter->hw.hw_addr + test->reg)
1042 + (i * test->reg_offset));
1043 break;
1044 case TABLE32_TEST:
1045 REG_PATTERN_TEST(test->reg + (i * 4),
1046 test->mask,
1047 test->write);
1048 break;
1049 case TABLE64_TEST_LO:
1050 REG_PATTERN_TEST(test->reg + (i * 8),
1051 test->mask,
1052 test->write);
1053 break;
1054 case TABLE64_TEST_HI:
1055 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1056 test->mask,
1057 test->write);
1058 break;
1059 }
1060 }
1061 test++;
1062 }
1063
1064 *data = 0;
1065 return 0;
1066 }
1067
1068 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1069 {
1070 u16 temp;
1071 u16 checksum = 0;
1072 u16 i;
1073
1074 *data = 0;
1075 /* Read and add up the contents of the EEPROM */
1076 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1077 if ((adapter->hw.nvm.ops.read(&adapter->hw, i, 1, &temp))
1078 < 0) {
1079 *data = 1;
1080 break;
1081 }
1082 checksum += temp;
1083 }
1084
1085 /* If Checksum is not Correct return error else test passed */
1086 if ((checksum != (u16) NVM_SUM) && !(*data))
1087 *data = 2;
1088
1089 return *data;
1090 }
1091
1092 static irqreturn_t igb_test_intr(int irq, void *data)
1093 {
1094 struct net_device *netdev = (struct net_device *) data;
1095 struct igb_adapter *adapter = netdev_priv(netdev);
1096 struct e1000_hw *hw = &adapter->hw;
1097
1098 adapter->test_icr |= rd32(E1000_ICR);
1099
1100 return IRQ_HANDLED;
1101 }
1102
1103 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1104 {
1105 struct e1000_hw *hw = &adapter->hw;
1106 struct net_device *netdev = adapter->netdev;
1107 u32 mask, ics_mask, i = 0, shared_int = true;
1108 u32 irq = adapter->pdev->irq;
1109
1110 *data = 0;
1111
1112 /* Hook up test interrupt handler just for this test */
1113 if (adapter->msix_entries)
1114 /* NOTE: we don't test MSI-X interrupts here, yet */
1115 return 0;
1116
1117 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1118 shared_int = false;
1119 if (request_irq(irq, &igb_test_intr, 0, netdev->name, netdev)) {
1120 *data = 1;
1121 return -1;
1122 }
1123 } else if (!request_irq(irq, &igb_test_intr, IRQF_PROBE_SHARED,
1124 netdev->name, netdev)) {
1125 shared_int = false;
1126 } else if (request_irq(irq, &igb_test_intr, IRQF_SHARED,
1127 netdev->name, netdev)) {
1128 *data = 1;
1129 return -1;
1130 }
1131 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1132 (shared_int ? "shared" : "unshared"));
1133 /* Disable all the interrupts */
1134 wr32(E1000_IMC, 0xFFFFFFFF);
1135 msleep(10);
1136
1137 /* Define all writable bits for ICS */
1138 switch(hw->mac.type) {
1139 case e1000_82575:
1140 ics_mask = 0x37F47EDD;
1141 break;
1142 case e1000_82576:
1143 ics_mask = 0x77D4FBFD;
1144 break;
1145 default:
1146 ics_mask = 0x7FFFFFFF;
1147 break;
1148 }
1149
1150 /* Test each interrupt */
1151 for (; i < 31; i++) {
1152 /* Interrupt to test */
1153 mask = 1 << i;
1154
1155 if (!(mask & ics_mask))
1156 continue;
1157
1158 if (!shared_int) {
1159 /* Disable the interrupt to be reported in
1160 * the cause register and then force the same
1161 * interrupt and see if one gets posted. If
1162 * an interrupt was posted to the bus, the
1163 * test failed.
1164 */
1165 adapter->test_icr = 0;
1166
1167 /* Flush any pending interrupts */
1168 wr32(E1000_ICR, ~0);
1169
1170 wr32(E1000_IMC, mask);
1171 wr32(E1000_ICS, mask);
1172 msleep(10);
1173
1174 if (adapter->test_icr & mask) {
1175 *data = 3;
1176 break;
1177 }
1178 }
1179
1180 /* Enable the interrupt to be reported in
1181 * the cause register and then force the same
1182 * interrupt and see if one gets posted. If
1183 * an interrupt was not posted to the bus, the
1184 * test failed.
1185 */
1186 adapter->test_icr = 0;
1187
1188 /* Flush any pending interrupts */
1189 wr32(E1000_ICR, ~0);
1190
1191 wr32(E1000_IMS, mask);
1192 wr32(E1000_ICS, mask);
1193 msleep(10);
1194
1195 if (!(adapter->test_icr & mask)) {
1196 *data = 4;
1197 break;
1198 }
1199
1200 if (!shared_int) {
1201 /* Disable the other interrupts to be reported in
1202 * the cause register and then force the other
1203 * interrupts and see if any get posted. If
1204 * an interrupt was posted to the bus, the
1205 * test failed.
1206 */
1207 adapter->test_icr = 0;
1208
1209 /* Flush any pending interrupts */
1210 wr32(E1000_ICR, ~0);
1211
1212 wr32(E1000_IMC, ~mask);
1213 wr32(E1000_ICS, ~mask);
1214 msleep(10);
1215
1216 if (adapter->test_icr & mask) {
1217 *data = 5;
1218 break;
1219 }
1220 }
1221 }
1222
1223 /* Disable all the interrupts */
1224 wr32(E1000_IMC, ~0);
1225 msleep(10);
1226
1227 /* Unhook test interrupt handler */
1228 free_irq(irq, netdev);
1229
1230 return *data;
1231 }
1232
1233 static void igb_free_desc_rings(struct igb_adapter *adapter)
1234 {
1235 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1236 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1237 struct pci_dev *pdev = adapter->pdev;
1238 int i;
1239
1240 if (tx_ring->desc && tx_ring->buffer_info) {
1241 for (i = 0; i < tx_ring->count; i++) {
1242 struct igb_buffer *buf = &(tx_ring->buffer_info[i]);
1243 if (buf->dma)
1244 pci_unmap_single(pdev, buf->dma, buf->length,
1245 PCI_DMA_TODEVICE);
1246 if (buf->skb)
1247 dev_kfree_skb(buf->skb);
1248 }
1249 }
1250
1251 if (rx_ring->desc && rx_ring->buffer_info) {
1252 for (i = 0; i < rx_ring->count; i++) {
1253 struct igb_buffer *buf = &(rx_ring->buffer_info[i]);
1254 if (buf->dma)
1255 pci_unmap_single(pdev, buf->dma,
1256 IGB_RXBUFFER_2048,
1257 PCI_DMA_FROMDEVICE);
1258 if (buf->skb)
1259 dev_kfree_skb(buf->skb);
1260 }
1261 }
1262
1263 if (tx_ring->desc) {
1264 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1265 tx_ring->dma);
1266 tx_ring->desc = NULL;
1267 }
1268 if (rx_ring->desc) {
1269 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1270 rx_ring->dma);
1271 rx_ring->desc = NULL;
1272 }
1273
1274 kfree(tx_ring->buffer_info);
1275 tx_ring->buffer_info = NULL;
1276 kfree(rx_ring->buffer_info);
1277 rx_ring->buffer_info = NULL;
1278
1279 return;
1280 }
1281
1282 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1283 {
1284 struct e1000_hw *hw = &adapter->hw;
1285 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1286 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1287 struct pci_dev *pdev = adapter->pdev;
1288 struct igb_buffer *buffer_info;
1289 u32 rctl;
1290 int i, ret_val;
1291
1292 /* Setup Tx descriptor ring and Tx buffers */
1293
1294 if (!tx_ring->count)
1295 tx_ring->count = IGB_DEFAULT_TXD;
1296
1297 tx_ring->buffer_info = kcalloc(tx_ring->count,
1298 sizeof(struct igb_buffer),
1299 GFP_KERNEL);
1300 if (!tx_ring->buffer_info) {
1301 ret_val = 1;
1302 goto err_nomem;
1303 }
1304
1305 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
1306 tx_ring->size = ALIGN(tx_ring->size, 4096);
1307 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1308 &tx_ring->dma);
1309 if (!tx_ring->desc) {
1310 ret_val = 2;
1311 goto err_nomem;
1312 }
1313 tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1314
1315 wr32(E1000_TDBAL(0),
1316 ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1317 wr32(E1000_TDBAH(0), ((u64) tx_ring->dma >> 32));
1318 wr32(E1000_TDLEN(0),
1319 tx_ring->count * sizeof(union e1000_adv_tx_desc));
1320 wr32(E1000_TDH(0), 0);
1321 wr32(E1000_TDT(0), 0);
1322 wr32(E1000_TCTL,
1323 E1000_TCTL_PSP | E1000_TCTL_EN |
1324 E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT |
1325 E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT);
1326
1327 for (i = 0; i < tx_ring->count; i++) {
1328 union e1000_adv_tx_desc *tx_desc;
1329 struct sk_buff *skb;
1330 unsigned int size = 1024;
1331
1332 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
1333 skb = alloc_skb(size, GFP_KERNEL);
1334 if (!skb) {
1335 ret_val = 3;
1336 goto err_nomem;
1337 }
1338 skb_put(skb, size);
1339 buffer_info = &tx_ring->buffer_info[i];
1340 buffer_info->skb = skb;
1341 buffer_info->length = skb->len;
1342 buffer_info->dma = pci_map_single(pdev, skb->data, skb->len,
1343 PCI_DMA_TODEVICE);
1344 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
1345 tx_desc->read.olinfo_status = cpu_to_le32(skb->len) <<
1346 E1000_ADVTXD_PAYLEN_SHIFT;
1347 tx_desc->read.cmd_type_len = cpu_to_le32(skb->len);
1348 tx_desc->read.cmd_type_len |= cpu_to_le32(E1000_TXD_CMD_EOP |
1349 E1000_TXD_CMD_IFCS |
1350 E1000_TXD_CMD_RS |
1351 E1000_ADVTXD_DTYP_DATA |
1352 E1000_ADVTXD_DCMD_DEXT);
1353 }
1354
1355 /* Setup Rx descriptor ring and Rx buffers */
1356
1357 if (!rx_ring->count)
1358 rx_ring->count = IGB_DEFAULT_RXD;
1359
1360 rx_ring->buffer_info = kcalloc(rx_ring->count,
1361 sizeof(struct igb_buffer),
1362 GFP_KERNEL);
1363 if (!rx_ring->buffer_info) {
1364 ret_val = 4;
1365 goto err_nomem;
1366 }
1367
1368 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
1369 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1370 &rx_ring->dma);
1371 if (!rx_ring->desc) {
1372 ret_val = 5;
1373 goto err_nomem;
1374 }
1375 rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1376
1377 rctl = rd32(E1000_RCTL);
1378 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1379 wr32(E1000_RDBAL(0),
1380 ((u64) rx_ring->dma & 0xFFFFFFFF));
1381 wr32(E1000_RDBAH(0),
1382 ((u64) rx_ring->dma >> 32));
1383 wr32(E1000_RDLEN(0), rx_ring->size);
1384 wr32(E1000_RDH(0), 0);
1385 wr32(E1000_RDT(0), 0);
1386 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1387 rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
1388 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1389 wr32(E1000_RCTL, rctl);
1390 wr32(E1000_SRRCTL(0), E1000_SRRCTL_DESCTYPE_ADV_ONEBUF);
1391
1392 for (i = 0; i < rx_ring->count; i++) {
1393 union e1000_adv_rx_desc *rx_desc;
1394 struct sk_buff *skb;
1395
1396 buffer_info = &rx_ring->buffer_info[i];
1397 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
1398 skb = alloc_skb(IGB_RXBUFFER_2048 + NET_IP_ALIGN,
1399 GFP_KERNEL);
1400 if (!skb) {
1401 ret_val = 6;
1402 goto err_nomem;
1403 }
1404 skb_reserve(skb, NET_IP_ALIGN);
1405 buffer_info->skb = skb;
1406 buffer_info->dma = pci_map_single(pdev, skb->data,
1407 IGB_RXBUFFER_2048,
1408 PCI_DMA_FROMDEVICE);
1409 rx_desc->read.pkt_addr = cpu_to_le64(buffer_info->dma);
1410 memset(skb->data, 0x00, skb->len);
1411 }
1412
1413 return 0;
1414
1415 err_nomem:
1416 igb_free_desc_rings(adapter);
1417 return ret_val;
1418 }
1419
1420 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1421 {
1422 struct e1000_hw *hw = &adapter->hw;
1423
1424 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1425 igb_write_phy_reg(hw, 29, 0x001F);
1426 igb_write_phy_reg(hw, 30, 0x8FFC);
1427 igb_write_phy_reg(hw, 29, 0x001A);
1428 igb_write_phy_reg(hw, 30, 0x8FF0);
1429 }
1430
1431 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1432 {
1433 struct e1000_hw *hw = &adapter->hw;
1434 u32 ctrl_reg = 0;
1435
1436 hw->mac.autoneg = false;
1437
1438 if (hw->phy.type == e1000_phy_m88) {
1439 /* Auto-MDI/MDIX Off */
1440 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1441 /* reset to update Auto-MDI/MDIX */
1442 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1443 /* autoneg off */
1444 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1445 }
1446
1447 ctrl_reg = rd32(E1000_CTRL);
1448
1449 /* force 1000, set loopback */
1450 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1451
1452 /* Now set up the MAC to the same speed/duplex as the PHY. */
1453 ctrl_reg = rd32(E1000_CTRL);
1454 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1455 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1456 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1457 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1458 E1000_CTRL_FD | /* Force Duplex to FULL */
1459 E1000_CTRL_SLU); /* Set link up enable bit */
1460
1461 if (hw->phy.type == e1000_phy_m88)
1462 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1463
1464 wr32(E1000_CTRL, ctrl_reg);
1465
1466 /* Disable the receiver on the PHY so when a cable is plugged in, the
1467 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1468 */
1469 if (hw->phy.type == e1000_phy_m88)
1470 igb_phy_disable_receiver(adapter);
1471
1472 udelay(500);
1473
1474 return 0;
1475 }
1476
1477 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1478 {
1479 return igb_integrated_phy_loopback(adapter);
1480 }
1481
1482 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1483 {
1484 struct e1000_hw *hw = &adapter->hw;
1485 u32 reg;
1486
1487 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1488 reg = rd32(E1000_RCTL);
1489 reg |= E1000_RCTL_LBM_TCVR;
1490 wr32(E1000_RCTL, reg);
1491
1492 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1493
1494 reg = rd32(E1000_CTRL);
1495 reg &= ~(E1000_CTRL_RFCE |
1496 E1000_CTRL_TFCE |
1497 E1000_CTRL_LRST);
1498 reg |= E1000_CTRL_SLU |
1499 E1000_CTRL_FD;
1500 wr32(E1000_CTRL, reg);
1501
1502 /* Unset switch control to serdes energy detect */
1503 reg = rd32(E1000_CONNSW);
1504 reg &= ~E1000_CONNSW_ENRGSRC;
1505 wr32(E1000_CONNSW, reg);
1506
1507 /* Set PCS register for forced speed */
1508 reg = rd32(E1000_PCS_LCTL);
1509 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1510 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1511 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1512 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1513 E1000_PCS_LCTL_FSD | /* Force Speed */
1514 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1515 wr32(E1000_PCS_LCTL, reg);
1516
1517 return 0;
1518 } else if (hw->phy.media_type == e1000_media_type_copper) {
1519 return igb_set_phy_loopback(adapter);
1520 }
1521
1522 return 7;
1523 }
1524
1525 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1526 {
1527 struct e1000_hw *hw = &adapter->hw;
1528 u32 rctl;
1529 u16 phy_reg;
1530
1531 rctl = rd32(E1000_RCTL);
1532 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1533 wr32(E1000_RCTL, rctl);
1534
1535 hw->mac.autoneg = true;
1536 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1537 if (phy_reg & MII_CR_LOOPBACK) {
1538 phy_reg &= ~MII_CR_LOOPBACK;
1539 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1540 igb_phy_sw_reset(hw);
1541 }
1542 }
1543
1544 static void igb_create_lbtest_frame(struct sk_buff *skb,
1545 unsigned int frame_size)
1546 {
1547 memset(skb->data, 0xFF, frame_size);
1548 frame_size &= ~1;
1549 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1550 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1551 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1552 }
1553
1554 static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1555 {
1556 frame_size &= ~1;
1557 if (*(skb->data + 3) == 0xFF)
1558 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1559 (*(skb->data + frame_size / 2 + 12) == 0xAF))
1560 return 0;
1561 return 13;
1562 }
1563
1564 static int igb_run_loopback_test(struct igb_adapter *adapter)
1565 {
1566 struct e1000_hw *hw = &adapter->hw;
1567 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1568 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1569 struct pci_dev *pdev = adapter->pdev;
1570 int i, j, k, l, lc, good_cnt;
1571 int ret_val = 0;
1572 unsigned long time;
1573
1574 wr32(E1000_RDT(0), rx_ring->count - 1);
1575
1576 /* Calculate the loop count based on the largest descriptor ring
1577 * The idea is to wrap the largest ring a number of times using 64
1578 * send/receive pairs during each loop
1579 */
1580
1581 if (rx_ring->count <= tx_ring->count)
1582 lc = ((tx_ring->count / 64) * 2) + 1;
1583 else
1584 lc = ((rx_ring->count / 64) * 2) + 1;
1585
1586 k = l = 0;
1587 for (j = 0; j <= lc; j++) { /* loop count loop */
1588 for (i = 0; i < 64; i++) { /* send the packets */
1589 igb_create_lbtest_frame(tx_ring->buffer_info[k].skb,
1590 1024);
1591 pci_dma_sync_single_for_device(pdev,
1592 tx_ring->buffer_info[k].dma,
1593 tx_ring->buffer_info[k].length,
1594 PCI_DMA_TODEVICE);
1595 k++;
1596 if (k == tx_ring->count)
1597 k = 0;
1598 }
1599 wr32(E1000_TDT(0), k);
1600 msleep(200);
1601 time = jiffies; /* set the start time for the receive */
1602 good_cnt = 0;
1603 do { /* receive the sent packets */
1604 pci_dma_sync_single_for_cpu(pdev,
1605 rx_ring->buffer_info[l].dma,
1606 IGB_RXBUFFER_2048,
1607 PCI_DMA_FROMDEVICE);
1608
1609 ret_val = igb_check_lbtest_frame(
1610 rx_ring->buffer_info[l].skb, 1024);
1611 if (!ret_val)
1612 good_cnt++;
1613 l++;
1614 if (l == rx_ring->count)
1615 l = 0;
1616 /* time + 20 msecs (200 msecs on 2.4) is more than
1617 * enough time to complete the receives, if it's
1618 * exceeded, break and error off
1619 */
1620 } while (good_cnt < 64 && jiffies < (time + 20));
1621 if (good_cnt != 64) {
1622 ret_val = 13; /* ret_val is the same as mis-compare */
1623 break;
1624 }
1625 if (jiffies >= (time + 20)) {
1626 ret_val = 14; /* error code for time out error */
1627 break;
1628 }
1629 } /* end loop count loop */
1630 return ret_val;
1631 }
1632
1633 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1634 {
1635 /* PHY loopback cannot be performed if SoL/IDER
1636 * sessions are active */
1637 if (igb_check_reset_block(&adapter->hw)) {
1638 dev_err(&adapter->pdev->dev,
1639 "Cannot do PHY loopback test "
1640 "when SoL/IDER is active.\n");
1641 *data = 0;
1642 goto out;
1643 }
1644 *data = igb_setup_desc_rings(adapter);
1645 if (*data)
1646 goto out;
1647 *data = igb_setup_loopback_test(adapter);
1648 if (*data)
1649 goto err_loopback;
1650 *data = igb_run_loopback_test(adapter);
1651 igb_loopback_cleanup(adapter);
1652
1653 err_loopback:
1654 igb_free_desc_rings(adapter);
1655 out:
1656 return *data;
1657 }
1658
1659 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1660 {
1661 struct e1000_hw *hw = &adapter->hw;
1662 *data = 0;
1663 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1664 int i = 0;
1665 hw->mac.serdes_has_link = false;
1666
1667 /* On some blade server designs, link establishment
1668 * could take as long as 2-3 minutes */
1669 do {
1670 hw->mac.ops.check_for_link(&adapter->hw);
1671 if (hw->mac.serdes_has_link)
1672 return *data;
1673 msleep(20);
1674 } while (i++ < 3750);
1675
1676 *data = 1;
1677 } else {
1678 hw->mac.ops.check_for_link(&adapter->hw);
1679 if (hw->mac.autoneg)
1680 msleep(4000);
1681
1682 if (!(rd32(E1000_STATUS) &
1683 E1000_STATUS_LU))
1684 *data = 1;
1685 }
1686 return *data;
1687 }
1688
1689 static void igb_diag_test(struct net_device *netdev,
1690 struct ethtool_test *eth_test, u64 *data)
1691 {
1692 struct igb_adapter *adapter = netdev_priv(netdev);
1693 u16 autoneg_advertised;
1694 u8 forced_speed_duplex, autoneg;
1695 bool if_running = netif_running(netdev);
1696
1697 set_bit(__IGB_TESTING, &adapter->state);
1698 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1699 /* Offline tests */
1700
1701 /* save speed, duplex, autoneg settings */
1702 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1703 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1704 autoneg = adapter->hw.mac.autoneg;
1705
1706 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1707
1708 /* Link test performed before hardware reset so autoneg doesn't
1709 * interfere with test result */
1710 if (igb_link_test(adapter, &data[4]))
1711 eth_test->flags |= ETH_TEST_FL_FAILED;
1712
1713 if (if_running)
1714 /* indicate we're in test mode */
1715 dev_close(netdev);
1716 else
1717 igb_reset(adapter);
1718
1719 if (igb_reg_test(adapter, &data[0]))
1720 eth_test->flags |= ETH_TEST_FL_FAILED;
1721
1722 igb_reset(adapter);
1723 if (igb_eeprom_test(adapter, &data[1]))
1724 eth_test->flags |= ETH_TEST_FL_FAILED;
1725
1726 igb_reset(adapter);
1727 if (igb_intr_test(adapter, &data[2]))
1728 eth_test->flags |= ETH_TEST_FL_FAILED;
1729
1730 igb_reset(adapter);
1731 if (igb_loopback_test(adapter, &data[3]))
1732 eth_test->flags |= ETH_TEST_FL_FAILED;
1733
1734 /* restore speed, duplex, autoneg settings */
1735 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1736 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1737 adapter->hw.mac.autoneg = autoneg;
1738
1739 /* force this routine to wait until autoneg complete/timeout */
1740 adapter->hw.phy.autoneg_wait_to_complete = true;
1741 igb_reset(adapter);
1742 adapter->hw.phy.autoneg_wait_to_complete = false;
1743
1744 clear_bit(__IGB_TESTING, &adapter->state);
1745 if (if_running)
1746 dev_open(netdev);
1747 } else {
1748 dev_info(&adapter->pdev->dev, "online testing starting\n");
1749 /* Online tests */
1750 if (igb_link_test(adapter, &data[4]))
1751 eth_test->flags |= ETH_TEST_FL_FAILED;
1752
1753 /* Online tests aren't run; pass by default */
1754 data[0] = 0;
1755 data[1] = 0;
1756 data[2] = 0;
1757 data[3] = 0;
1758
1759 clear_bit(__IGB_TESTING, &adapter->state);
1760 }
1761 msleep_interruptible(4 * 1000);
1762 }
1763
1764 static int igb_wol_exclusion(struct igb_adapter *adapter,
1765 struct ethtool_wolinfo *wol)
1766 {
1767 struct e1000_hw *hw = &adapter->hw;
1768 int retval = 1; /* fail by default */
1769
1770 switch (hw->device_id) {
1771 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1772 /* WoL not supported */
1773 wol->supported = 0;
1774 break;
1775 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1776 case E1000_DEV_ID_82576_FIBER:
1777 case E1000_DEV_ID_82576_SERDES:
1778 /* Wake events not supported on port B */
1779 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1780 wol->supported = 0;
1781 break;
1782 }
1783 /* return success for non excluded adapter ports */
1784 retval = 0;
1785 break;
1786 case E1000_DEV_ID_82576_QUAD_COPPER:
1787 /* quad port adapters only support WoL on port A */
1788 if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) {
1789 wol->supported = 0;
1790 break;
1791 }
1792 /* return success for non excluded adapter ports */
1793 retval = 0;
1794 break;
1795 default:
1796 /* dual port cards only support WoL on port A from now on
1797 * unless it was enabled in the eeprom for port B
1798 * so exclude FUNC_1 ports from having WoL enabled */
1799 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1 &&
1800 !adapter->eeprom_wol) {
1801 wol->supported = 0;
1802 break;
1803 }
1804
1805 retval = 0;
1806 }
1807
1808 return retval;
1809 }
1810
1811 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1812 {
1813 struct igb_adapter *adapter = netdev_priv(netdev);
1814
1815 wol->supported = WAKE_UCAST | WAKE_MCAST |
1816 WAKE_BCAST | WAKE_MAGIC;
1817 wol->wolopts = 0;
1818
1819 /* this function will set ->supported = 0 and return 1 if wol is not
1820 * supported by this hardware */
1821 if (igb_wol_exclusion(adapter, wol) ||
1822 !device_can_wakeup(&adapter->pdev->dev))
1823 return;
1824
1825 /* apply any specific unsupported masks here */
1826 switch (adapter->hw.device_id) {
1827 default:
1828 break;
1829 }
1830
1831 if (adapter->wol & E1000_WUFC_EX)
1832 wol->wolopts |= WAKE_UCAST;
1833 if (adapter->wol & E1000_WUFC_MC)
1834 wol->wolopts |= WAKE_MCAST;
1835 if (adapter->wol & E1000_WUFC_BC)
1836 wol->wolopts |= WAKE_BCAST;
1837 if (adapter->wol & E1000_WUFC_MAG)
1838 wol->wolopts |= WAKE_MAGIC;
1839
1840 return;
1841 }
1842
1843 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1844 {
1845 struct igb_adapter *adapter = netdev_priv(netdev);
1846
1847 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1848 return -EOPNOTSUPP;
1849
1850 if (igb_wol_exclusion(adapter, wol) ||
1851 !device_can_wakeup(&adapter->pdev->dev))
1852 return wol->wolopts ? -EOPNOTSUPP : 0;
1853
1854 /* these settings will always override what we currently have */
1855 adapter->wol = 0;
1856
1857 if (wol->wolopts & WAKE_UCAST)
1858 adapter->wol |= E1000_WUFC_EX;
1859 if (wol->wolopts & WAKE_MCAST)
1860 adapter->wol |= E1000_WUFC_MC;
1861 if (wol->wolopts & WAKE_BCAST)
1862 adapter->wol |= E1000_WUFC_BC;
1863 if (wol->wolopts & WAKE_MAGIC)
1864 adapter->wol |= E1000_WUFC_MAG;
1865
1866 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1867
1868 return 0;
1869 }
1870
1871 /* bit defines for adapter->led_status */
1872 #define IGB_LED_ON 0
1873
1874 static int igb_phys_id(struct net_device *netdev, u32 data)
1875 {
1876 struct igb_adapter *adapter = netdev_priv(netdev);
1877 struct e1000_hw *hw = &adapter->hw;
1878
1879 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
1880 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
1881
1882 igb_blink_led(hw);
1883 msleep_interruptible(data * 1000);
1884
1885 igb_led_off(hw);
1886 clear_bit(IGB_LED_ON, &adapter->led_status);
1887 igb_cleanup_led(hw);
1888
1889 return 0;
1890 }
1891
1892 static int igb_set_coalesce(struct net_device *netdev,
1893 struct ethtool_coalesce *ec)
1894 {
1895 struct igb_adapter *adapter = netdev_priv(netdev);
1896 struct e1000_hw *hw = &adapter->hw;
1897 int i;
1898
1899 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1900 ((ec->rx_coalesce_usecs > 3) &&
1901 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1902 (ec->rx_coalesce_usecs == 2))
1903 return -EINVAL;
1904
1905 /* convert to rate of irq's per second */
1906 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) {
1907 adapter->itr_setting = ec->rx_coalesce_usecs;
1908 adapter->itr = IGB_START_ITR;
1909 } else {
1910 adapter->itr_setting = ec->rx_coalesce_usecs << 2;
1911 adapter->itr = adapter->itr_setting;
1912 }
1913
1914 for (i = 0; i < adapter->num_rx_queues; i++)
1915 wr32(adapter->rx_ring[i].itr_register, adapter->itr);
1916
1917 return 0;
1918 }
1919
1920 static int igb_get_coalesce(struct net_device *netdev,
1921 struct ethtool_coalesce *ec)
1922 {
1923 struct igb_adapter *adapter = netdev_priv(netdev);
1924
1925 if (adapter->itr_setting <= 3)
1926 ec->rx_coalesce_usecs = adapter->itr_setting;
1927 else
1928 ec->rx_coalesce_usecs = adapter->itr_setting >> 2;
1929
1930 return 0;
1931 }
1932
1933
1934 static int igb_nway_reset(struct net_device *netdev)
1935 {
1936 struct igb_adapter *adapter = netdev_priv(netdev);
1937 if (netif_running(netdev))
1938 igb_reinit_locked(adapter);
1939 return 0;
1940 }
1941
1942 static int igb_get_sset_count(struct net_device *netdev, int sset)
1943 {
1944 switch (sset) {
1945 case ETH_SS_STATS:
1946 return IGB_STATS_LEN;
1947 case ETH_SS_TEST:
1948 return IGB_TEST_LEN;
1949 default:
1950 return -ENOTSUPP;
1951 }
1952 }
1953
1954 static void igb_get_ethtool_stats(struct net_device *netdev,
1955 struct ethtool_stats *stats, u64 *data)
1956 {
1957 struct igb_adapter *adapter = netdev_priv(netdev);
1958 u64 *queue_stat;
1959 int stat_count_tx = sizeof(struct igb_tx_queue_stats) / sizeof(u64);
1960 int stat_count_rx = sizeof(struct igb_rx_queue_stats) / sizeof(u64);
1961 int j;
1962 int i;
1963
1964 igb_update_stats(adapter);
1965 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1966 char *p = (char *)adapter+igb_gstrings_stats[i].stat_offset;
1967 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
1968 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1969 }
1970 for (j = 0; j < adapter->num_tx_queues; j++) {
1971 int k;
1972 queue_stat = (u64 *)&adapter->tx_ring[j].tx_stats;
1973 for (k = 0; k < stat_count_tx; k++)
1974 data[i + k] = queue_stat[k];
1975 i += k;
1976 }
1977 for (j = 0; j < adapter->num_rx_queues; j++) {
1978 int k;
1979 queue_stat = (u64 *)&adapter->rx_ring[j].rx_stats;
1980 for (k = 0; k < stat_count_rx; k++)
1981 data[i + k] = queue_stat[k];
1982 i += k;
1983 }
1984 }
1985
1986 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
1987 {
1988 struct igb_adapter *adapter = netdev_priv(netdev);
1989 u8 *p = data;
1990 int i;
1991
1992 switch (stringset) {
1993 case ETH_SS_TEST:
1994 memcpy(data, *igb_gstrings_test,
1995 IGB_TEST_LEN*ETH_GSTRING_LEN);
1996 break;
1997 case ETH_SS_STATS:
1998 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1999 memcpy(p, igb_gstrings_stats[i].stat_string,
2000 ETH_GSTRING_LEN);
2001 p += ETH_GSTRING_LEN;
2002 }
2003 for (i = 0; i < adapter->num_tx_queues; i++) {
2004 sprintf(p, "tx_queue_%u_packets", i);
2005 p += ETH_GSTRING_LEN;
2006 sprintf(p, "tx_queue_%u_bytes", i);
2007 p += ETH_GSTRING_LEN;
2008 }
2009 for (i = 0; i < adapter->num_rx_queues; i++) {
2010 sprintf(p, "rx_queue_%u_packets", i);
2011 p += ETH_GSTRING_LEN;
2012 sprintf(p, "rx_queue_%u_bytes", i);
2013 p += ETH_GSTRING_LEN;
2014 sprintf(p, "rx_queue_%u_drops", i);
2015 p += ETH_GSTRING_LEN;
2016 }
2017 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2018 break;
2019 }
2020 }
2021
2022 static const struct ethtool_ops igb_ethtool_ops = {
2023 .get_settings = igb_get_settings,
2024 .set_settings = igb_set_settings,
2025 .get_drvinfo = igb_get_drvinfo,
2026 .get_regs_len = igb_get_regs_len,
2027 .get_regs = igb_get_regs,
2028 .get_wol = igb_get_wol,
2029 .set_wol = igb_set_wol,
2030 .get_msglevel = igb_get_msglevel,
2031 .set_msglevel = igb_set_msglevel,
2032 .nway_reset = igb_nway_reset,
2033 .get_link = ethtool_op_get_link,
2034 .get_eeprom_len = igb_get_eeprom_len,
2035 .get_eeprom = igb_get_eeprom,
2036 .set_eeprom = igb_set_eeprom,
2037 .get_ringparam = igb_get_ringparam,
2038 .set_ringparam = igb_set_ringparam,
2039 .get_pauseparam = igb_get_pauseparam,
2040 .set_pauseparam = igb_set_pauseparam,
2041 .get_rx_csum = igb_get_rx_csum,
2042 .set_rx_csum = igb_set_rx_csum,
2043 .get_tx_csum = igb_get_tx_csum,
2044 .set_tx_csum = igb_set_tx_csum,
2045 .get_sg = ethtool_op_get_sg,
2046 .set_sg = ethtool_op_set_sg,
2047 .get_tso = ethtool_op_get_tso,
2048 .set_tso = igb_set_tso,
2049 .self_test = igb_diag_test,
2050 .get_strings = igb_get_strings,
2051 .phys_id = igb_phys_id,
2052 .get_sset_count = igb_get_sset_count,
2053 .get_ethtool_stats = igb_get_ethtool_stats,
2054 .get_coalesce = igb_get_coalesce,
2055 .set_coalesce = igb_set_coalesce,
2056 };
2057
2058 void igb_set_ethtool_ops(struct net_device *netdev)
2059 {
2060 SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
2061 }
mm of the moment repository