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On Tue, Nov 06, 2007 at 02:33:53AM -0800, akpm@linux-foundation.org wrote:
[mmotm.git] / drivers / net / ixgbe / ixgbe_82599.c
blobae27c41222e300f0f1967032acba0e9e77029957
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34
35 #define IXGBE_82599_MAX_TX_QUEUES 128
36 #define IXGBE_82599_MAX_RX_QUEUES 128
37 #define IXGBE_82599_RAR_ENTRIES 128
38 #define IXGBE_82599_MC_TBL_SIZE 128
39 #define IXGBE_82599_VFT_TBL_SIZE 128
40
41 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
42 ixgbe_link_speed speed,
43 bool autoneg,
44 bool autoneg_wait_to_complete);
45 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
46 ixgbe_link_speed speed,
47 bool autoneg,
48 bool autoneg_wait_to_complete);
49 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
50 bool autoneg_wait_to_complete);
51 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
52 ixgbe_link_speed speed,
53 bool autoneg,
54 bool autoneg_wait_to_complete);
55 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
56 ixgbe_link_speed *speed,
57 bool *autoneg);
58 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
59 ixgbe_link_speed speed,
60 bool autoneg,
61 bool autoneg_wait_to_complete);
62 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
63
64 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
65 {
66 struct ixgbe_mac_info *mac = &hw->mac;
67 if (hw->phy.multispeed_fiber) {
68 /* Set up dual speed SFP+ support */
69 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
70 } else {
71 if ((mac->ops.get_media_type(hw) ==
72 ixgbe_media_type_backplane) &&
73 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
74 hw->phy.smart_speed == ixgbe_smart_speed_on))
75 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
76 else
77 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
78 }
79 }
80
81 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
82 {
83 s32 ret_val = 0;
84 u16 list_offset, data_offset, data_value;
85
86 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
87 ixgbe_init_mac_link_ops_82599(hw);
88
89 hw->phy.ops.reset = NULL;
90
91 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
92 &data_offset);
93
94 if (ret_val != 0)
95 goto setup_sfp_out;
96
97 /* PHY config will finish before releasing the semaphore */
98 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
99 if (ret_val != 0) {
100 ret_val = IXGBE_ERR_SWFW_SYNC;
101 goto setup_sfp_out;
102 }
103
104 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
105 while (data_value != 0xffff) {
106 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
107 IXGBE_WRITE_FLUSH(hw);
108 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
109 }
110 /* Now restart DSP by setting Restart_AN */
111 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
112 (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
113
114 /* Release the semaphore */
115 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
116 /* Delay obtaining semaphore again to allow FW access */
117 msleep(hw->eeprom.semaphore_delay);
118 }
119
120 setup_sfp_out:
121 return ret_val;
122 }
123
124 /**
125 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
126 * @hw: pointer to hardware structure
127 *
128 * Read PCIe configuration space, and get the MSI-X vector count from
129 * the capabilities table.
130 **/
131 static u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
132 {
133 struct ixgbe_adapter *adapter = hw->back;
134 u16 msix_count;
135 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
136 &msix_count);
137 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
138
139 /* MSI-X count is zero-based in HW, so increment to give proper value */
140 msix_count++;
141
142 return msix_count;
143 }
144
145 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
146 {
147 struct ixgbe_mac_info *mac = &hw->mac;
148
149 ixgbe_init_mac_link_ops_82599(hw);
150
151 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
152 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
153 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
154 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
155 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
156 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
157
158 return 0;
159 }
160
161 /**
162 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
163 * @hw: pointer to hardware structure
164 *
165 * Initialize any function pointers that were not able to be
166 * set during get_invariants because the PHY/SFP type was
167 * not known. Perform the SFP init if necessary.
168 *
169 **/
170 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
171 {
172 struct ixgbe_mac_info *mac = &hw->mac;
173 struct ixgbe_phy_info *phy = &hw->phy;
174 s32 ret_val = 0;
175
176 /* Identify the PHY or SFP module */
177 ret_val = phy->ops.identify(hw);
178
179 /* Setup function pointers based on detected SFP module and speeds */
180 ixgbe_init_mac_link_ops_82599(hw);
181
182 /* If copper media, overwrite with copper function pointers */
183 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
184 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
185 mac->ops.get_link_capabilities =
186 &ixgbe_get_copper_link_capabilities_82599;
187 }
188
189 /* Set necessary function pointers based on phy type */
190 switch (hw->phy.type) {
191 case ixgbe_phy_tn:
192 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
193 phy->ops.get_firmware_version =
194 &ixgbe_get_phy_firmware_version_tnx;
195 break;
196 default:
197 break;
198 }
199
200 return ret_val;
201 }
202
203 /**
204 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
205 * @hw: pointer to hardware structure
206 * @speed: pointer to link speed
207 * @negotiation: true when autoneg or autotry is enabled
208 *
209 * Determines the link capabilities by reading the AUTOC register.
210 **/
211 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
212 ixgbe_link_speed *speed,
213 bool *negotiation)
214 {
215 s32 status = 0;
216 u32 autoc = 0;
217
218 /*
219 * Determine link capabilities based on the stored value of AUTOC,
220 * which represents EEPROM defaults. If AUTOC value has not been
221 * stored, use the current register value.
222 */
223 if (hw->mac.orig_link_settings_stored)
224 autoc = hw->mac.orig_autoc;
225 else
226 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
227
228 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
229 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
230 *speed = IXGBE_LINK_SPEED_1GB_FULL;
231 *negotiation = false;
232 break;
233
234 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
235 *speed = IXGBE_LINK_SPEED_10GB_FULL;
236 *negotiation = false;
237 break;
238
239 case IXGBE_AUTOC_LMS_1G_AN:
240 *speed = IXGBE_LINK_SPEED_1GB_FULL;
241 *negotiation = true;
242 break;
243
244 case IXGBE_AUTOC_LMS_10G_SERIAL:
245 *speed = IXGBE_LINK_SPEED_10GB_FULL;
246 *negotiation = false;
247 break;
248
249 case IXGBE_AUTOC_LMS_KX4_KX_KR:
250 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
251 *speed = IXGBE_LINK_SPEED_UNKNOWN;
252 if (autoc & IXGBE_AUTOC_KR_SUPP)
253 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
254 if (autoc & IXGBE_AUTOC_KX4_SUPP)
255 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
256 if (autoc & IXGBE_AUTOC_KX_SUPP)
257 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
258 *negotiation = true;
259 break;
260
261 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
262 *speed = IXGBE_LINK_SPEED_100_FULL;
263 if (autoc & IXGBE_AUTOC_KR_SUPP)
264 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
265 if (autoc & IXGBE_AUTOC_KX4_SUPP)
266 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
267 if (autoc & IXGBE_AUTOC_KX_SUPP)
268 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
269 *negotiation = true;
270 break;
271
272 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
273 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
274 *negotiation = false;
275 break;
276
277 default:
278 status = IXGBE_ERR_LINK_SETUP;
279 goto out;
280 break;
281 }
282
283 if (hw->phy.multispeed_fiber) {
284 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
285 IXGBE_LINK_SPEED_1GB_FULL;
286 *negotiation = true;
287 }
288
289 out:
290 return status;
291 }
292
293 /**
294 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
295 * @hw: pointer to hardware structure
296 * @speed: pointer to link speed
297 * @autoneg: boolean auto-negotiation value
298 *
299 * Determines the link capabilities by reading the AUTOC register.
300 **/
301 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
302 ixgbe_link_speed *speed,
303 bool *autoneg)
304 {
305 s32 status = IXGBE_ERR_LINK_SETUP;
306 u16 speed_ability;
307
308 *speed = 0;
309 *autoneg = true;
310
311 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
312 &speed_ability);
313
314 if (status == 0) {
315 if (speed_ability & MDIO_SPEED_10G)
316 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
317 if (speed_ability & MDIO_PMA_SPEED_1000)
318 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
319 }
320
321 return status;
322 }
323
324 /**
325 * ixgbe_get_media_type_82599 - Get media type
326 * @hw: pointer to hardware structure
327 *
328 * Returns the media type (fiber, copper, backplane)
329 **/
330 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
331 {
332 enum ixgbe_media_type media_type;
333
334 /* Detect if there is a copper PHY attached. */
335 if (hw->phy.type == ixgbe_phy_cu_unknown ||
336 hw->phy.type == ixgbe_phy_tn) {
337 media_type = ixgbe_media_type_copper;
338 goto out;
339 }
340
341 switch (hw->device_id) {
342 case IXGBE_DEV_ID_82599_KX4:
343 case IXGBE_DEV_ID_82599_KX4_MEZZ:
344 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
345 case IXGBE_DEV_ID_82599_XAUI_LOM:
346 /* Default device ID is mezzanine card KX/KX4 */
347 media_type = ixgbe_media_type_backplane;
348 break;
349 case IXGBE_DEV_ID_82599_SFP:
350 case IXGBE_DEV_ID_82599_SFP_EM:
351 media_type = ixgbe_media_type_fiber;
352 break;
353 case IXGBE_DEV_ID_82599_CX4:
354 media_type = ixgbe_media_type_cx4;
355 break;
356 default:
357 media_type = ixgbe_media_type_unknown;
358 break;
359 }
360 out:
361 return media_type;
362 }
363
364 /**
365 * ixgbe_start_mac_link_82599 - Setup MAC link settings
366 * @hw: pointer to hardware structure
367 * @autoneg_wait_to_complete: true when waiting for completion is needed
368 *
369 * Configures link settings based on values in the ixgbe_hw struct.
370 * Restarts the link. Performs autonegotiation if needed.
371 **/
372 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
373 bool autoneg_wait_to_complete)
374 {
375 u32 autoc_reg;
376 u32 links_reg;
377 u32 i;
378 s32 status = 0;
379
380 /* Restart link */
381 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
382 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
383 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
384
385 /* Only poll for autoneg to complete if specified to do so */
386 if (autoneg_wait_to_complete) {
387 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
388 IXGBE_AUTOC_LMS_KX4_KX_KR ||
389 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
390 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
391 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
392 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
393 links_reg = 0; /* Just in case Autoneg time = 0 */
394 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
395 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
396 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
397 break;
398 msleep(100);
399 }
400 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
401 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
402 hw_dbg(hw, "Autoneg did not complete.\n");
403 }
404 }
405 }
406
407 /* Add delay to filter out noises during initial link setup */
408 msleep(50);
409
410 return status;
411 }
412
413 /**
414 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
415 * @hw: pointer to hardware structure
416 * @speed: new link speed
417 * @autoneg: true if autonegotiation enabled
418 * @autoneg_wait_to_complete: true when waiting for completion is needed
419 *
420 * Set the link speed in the AUTOC register and restarts link.
421 **/
422 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
423 ixgbe_link_speed speed,
424 bool autoneg,
425 bool autoneg_wait_to_complete)
426 {
427 s32 status = 0;
428 ixgbe_link_speed phy_link_speed;
429 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
430 u32 speedcnt = 0;
431 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
432 bool link_up = false;
433 bool negotiation;
434 int i;
435
436 /* Mask off requested but non-supported speeds */
437 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
438 speed &= phy_link_speed;
439
440 /*
441 * When the driver changes the link speeds that it can support,
442 * it sets autotry_restart to true to indicate that we need to
443 * initiate a new autotry session with the link partner. To do
444 * so, we set the speed then disable and re-enable the tx laser, to
445 * alert the link partner that it also needs to restart autotry on its
446 * end. This is consistent with true clause 37 autoneg, which also
447 * involves a loss of signal.
448 */
449
450 /*
451 * Try each speed one by one, highest priority first. We do this in
452 * software because 10gb fiber doesn't support speed autonegotiation.
453 */
454 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
455 speedcnt++;
456 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
457
458 /* If we already have link at this speed, just jump out */
459 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
460
461 if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
462 goto out;
463
464 /* Set the module link speed */
465 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
466 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
467
468 /* Allow module to change analog characteristics (1G->10G) */
469 msleep(40);
470
471 status = ixgbe_setup_mac_link_82599(hw,
472 IXGBE_LINK_SPEED_10GB_FULL,
473 autoneg,
474 autoneg_wait_to_complete);
475 if (status != 0)
476 return status;
477
478 /* Flap the tx laser if it has not already been done */
479 if (hw->mac.autotry_restart) {
480 /* Disable tx laser; allow 100us to go dark per spec */
481 esdp_reg |= IXGBE_ESDP_SDP3;
482 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
483 udelay(100);
484
485 /* Enable tx laser; allow 2ms to light up per spec */
486 esdp_reg &= ~IXGBE_ESDP_SDP3;
487 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
488 msleep(2);
489
490 hw->mac.autotry_restart = false;
491 }
492
493 /*
494 * Wait for the controller to acquire link. Per IEEE 802.3ap,
495 * Section 73.10.2, we may have to wait up to 500ms if KR is
496 * attempted. 82599 uses the same timing for 10g SFI.
497 */
498
499 for (i = 0; i < 5; i++) {
500 /* Wait for the link partner to also set speed */
501 msleep(100);
502
503 /* If we have link, just jump out */
504 hw->mac.ops.check_link(hw, &phy_link_speed,
505 &link_up, false);
506 if (link_up)
507 goto out;
508 }
509 }
510
511 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
512 speedcnt++;
513 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
514 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
515
516 /* If we already have link at this speed, just jump out */
517 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
518
519 if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
520 goto out;
521
522 /* Set the module link speed */
523 esdp_reg &= ~IXGBE_ESDP_SDP5;
524 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
525 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
526
527 /* Allow module to change analog characteristics (10G->1G) */
528 msleep(40);
529
530 status = ixgbe_setup_mac_link_82599(hw,
531 IXGBE_LINK_SPEED_1GB_FULL,
532 autoneg,
533 autoneg_wait_to_complete);
534 if (status != 0)
535 return status;
536
537 /* Flap the tx laser if it has not already been done */
538 if (hw->mac.autotry_restart) {
539 /* Disable tx laser; allow 100us to go dark per spec */
540 esdp_reg |= IXGBE_ESDP_SDP3;
541 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
542 udelay(100);
543
544 /* Enable tx laser; allow 2ms to light up per spec */
545 esdp_reg &= ~IXGBE_ESDP_SDP3;
546 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
547 msleep(2);
548
549 hw->mac.autotry_restart = false;
550 }
551
552 /* Wait for the link partner to also set speed */
553 msleep(100);
554
555 /* If we have link, just jump out */
556 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
557 if (link_up)
558 goto out;
559 }
560
561 /*
562 * We didn't get link. Configure back to the highest speed we tried,
563 * (if there was more than one). We call ourselves back with just the
564 * single highest speed that the user requested.
565 */
566 if (speedcnt > 1)
567 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
568 highest_link_speed,
569 autoneg,
570 autoneg_wait_to_complete);
571
572 out:
573 /* Set autoneg_advertised value based on input link speed */
574 hw->phy.autoneg_advertised = 0;
575
576 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
577 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
578
579 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
580 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
581
582 return status;
583 }
584
585 /**
586 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
587 * @hw: pointer to hardware structure
588 * @speed: new link speed
589 * @autoneg: true if autonegotiation enabled
590 * @autoneg_wait_to_complete: true when waiting for completion is needed
591 *
592 * Implements the Intel SmartSpeed algorithm.
593 **/
594 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
595 ixgbe_link_speed speed, bool autoneg,
596 bool autoneg_wait_to_complete)
597 {
598 s32 status = 0;
599 ixgbe_link_speed link_speed;
600 s32 i, j;
601 bool link_up = false;
602 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
603
604 hw_dbg(hw, "ixgbe_setup_mac_link_smartspeed.\n");
605
606 /* Set autoneg_advertised value based on input link speed */
607 hw->phy.autoneg_advertised = 0;
608
609 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
610 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
611
612 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
613 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
614
615 if (speed & IXGBE_LINK_SPEED_100_FULL)
616 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
617
618 /*
619 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
620 * autoneg advertisement if link is unable to be established at the
621 * highest negotiated rate. This can sometimes happen due to integrity
622 * issues with the physical media connection.
623 */
624
625 /* First, try to get link with full advertisement */
626 hw->phy.smart_speed_active = false;
627 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
628 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
629 autoneg_wait_to_complete);
630 if (status)
631 goto out;
632
633 /*
634 * Wait for the controller to acquire link. Per IEEE 802.3ap,
635 * Section 73.10.2, we may have to wait up to 500ms if KR is
636 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
637 * Table 9 in the AN MAS.
638 */
639 for (i = 0; i < 5; i++) {
640 mdelay(100);
641
642 /* If we have link, just jump out */
643 hw->mac.ops.check_link(hw, &link_speed,
644 &link_up, false);
645 if (link_up)
646 goto out;
647 }
648 }
649
650 /*
651 * We didn't get link. If we advertised KR plus one of KX4/KX
652 * (or BX4/BX), then disable KR and try again.
653 */
654 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
655 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
656 goto out;
657
658 /* Turn SmartSpeed on to disable KR support */
659 hw->phy.smart_speed_active = true;
660 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
661 autoneg_wait_to_complete);
662 if (status)
663 goto out;
664
665 /*
666 * Wait for the controller to acquire link. 600ms will allow for
667 * the AN link_fail_inhibit_timer as well for multiple cycles of
668 * parallel detect, both 10g and 1g. This allows for the maximum
669 * connect attempts as defined in the AN MAS table 73-7.
670 */
671 for (i = 0; i < 6; i++) {
672 mdelay(100);
673
674 /* If we have link, just jump out */
675 hw->mac.ops.check_link(hw, &link_speed,
676 &link_up, false);
677 if (link_up)
678 goto out;
679 }
680
681 /* We didn't get link. Turn SmartSpeed back off. */
682 hw->phy.smart_speed_active = false;
683 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
684 autoneg_wait_to_complete);
685
686 out:
687 return status;
688 }
689
690 /**
691 * ixgbe_check_mac_link_82599 - Determine link and speed status
692 * @hw: pointer to hardware structure
693 * @speed: pointer to link speed
694 * @link_up: true when link is up
695 * @link_up_wait_to_complete: bool used to wait for link up or not
696 *
697 * Reads the links register to determine if link is up and the current speed
698 **/
699 static s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
700 ixgbe_link_speed *speed,
701 bool *link_up,
702 bool link_up_wait_to_complete)
703 {
704 u32 links_reg;
705 u32 i;
706
707 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
708 if (link_up_wait_to_complete) {
709 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
710 if (links_reg & IXGBE_LINKS_UP) {
711 *link_up = true;
712 break;
713 } else {
714 *link_up = false;
715 }
716 msleep(100);
717 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
718 }
719 } else {
720 if (links_reg & IXGBE_LINKS_UP)
721 *link_up = true;
722 else
723 *link_up = false;
724 }
725
726 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
727 IXGBE_LINKS_SPEED_10G_82599)
728 *speed = IXGBE_LINK_SPEED_10GB_FULL;
729 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
730 IXGBE_LINKS_SPEED_1G_82599)
731 *speed = IXGBE_LINK_SPEED_1GB_FULL;
732 else
733 *speed = IXGBE_LINK_SPEED_100_FULL;
734
735 /* if link is down, zero out the current_mode */
736 if (*link_up == false) {
737 hw->fc.current_mode = ixgbe_fc_none;
738 hw->fc.fc_was_autonegged = false;
739 }
740
741 return 0;
742 }
743
744 /**
745 * ixgbe_setup_mac_link_82599 - Set MAC link speed
746 * @hw: pointer to hardware structure
747 * @speed: new link speed
748 * @autoneg: true if autonegotiation enabled
749 * @autoneg_wait_to_complete: true when waiting for completion is needed
750 *
751 * Set the link speed in the AUTOC register and restarts link.
752 **/
753 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
754 ixgbe_link_speed speed, bool autoneg,
755 bool autoneg_wait_to_complete)
756 {
757 s32 status = 0;
758 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
759 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
760 u32 start_autoc = autoc;
761 u32 orig_autoc = 0;
762 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
763 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
764 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
765 u32 links_reg;
766 u32 i;
767 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
768
769 /* Check to see if speed passed in is supported. */
770 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
771 speed &= link_capabilities;
772
773 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
774 status = IXGBE_ERR_LINK_SETUP;
775 goto out;
776 }
777
778 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
779 if (hw->mac.orig_link_settings_stored)
780 orig_autoc = hw->mac.orig_autoc;
781 else
782 orig_autoc = autoc;
783
784
785 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
786 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
787 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
788 /* Set KX4/KX/KR support according to speed requested */
789 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
790 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
791 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
792 autoc |= IXGBE_AUTOC_KX4_SUPP;
793 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
794 (hw->phy.smart_speed_active == false))
795 autoc |= IXGBE_AUTOC_KR_SUPP;
796 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
797 autoc |= IXGBE_AUTOC_KX_SUPP;
798 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
799 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
800 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
801 /* Switch from 1G SFI to 10G SFI if requested */
802 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
803 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
804 autoc &= ~IXGBE_AUTOC_LMS_MASK;
805 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
806 }
807 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
808 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
809 /* Switch from 10G SFI to 1G SFI if requested */
810 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
811 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
812 autoc &= ~IXGBE_AUTOC_LMS_MASK;
813 if (autoneg)
814 autoc |= IXGBE_AUTOC_LMS_1G_AN;
815 else
816 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
817 }
818 }
819
820 if (autoc != start_autoc) {
821 /* Restart link */
822 autoc |= IXGBE_AUTOC_AN_RESTART;
823 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
824
825 /* Only poll for autoneg to complete if specified to do so */
826 if (autoneg_wait_to_complete) {
827 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
828 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
829 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
830 links_reg = 0; /*Just in case Autoneg time=0*/
831 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
832 links_reg =
833 IXGBE_READ_REG(hw, IXGBE_LINKS);
834 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
835 break;
836 msleep(100);
837 }
838 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
839 status =
840 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
841 hw_dbg(hw, "Autoneg did not "
842 "complete.\n");
843 }
844 }
845 }
846
847 /* Add delay to filter out noises during initial link setup */
848 msleep(50);
849 }
850
851 out:
852 return status;
853 }
854
855 /**
856 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
857 * @hw: pointer to hardware structure
858 * @speed: new link speed
859 * @autoneg: true if autonegotiation enabled
860 * @autoneg_wait_to_complete: true if waiting is needed to complete
861 *
862 * Restarts link on PHY and MAC based on settings passed in.
863 **/
864 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
865 ixgbe_link_speed speed,
866 bool autoneg,
867 bool autoneg_wait_to_complete)
868 {
869 s32 status;
870
871 /* Setup the PHY according to input speed */
872 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
873 autoneg_wait_to_complete);
874 /* Set up MAC */
875 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
876
877 return status;
878 }
879
880 /**
881 * ixgbe_reset_hw_82599 - Perform hardware reset
882 * @hw: pointer to hardware structure
883 *
884 * Resets the hardware by resetting the transmit and receive units, masks
885 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
886 * reset.
887 **/
888 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
889 {
890 s32 status = 0;
891 u32 ctrl, ctrl_ext;
892 u32 i;
893 u32 autoc;
894 u32 autoc2;
895
896 /* Call adapter stop to disable tx/rx and clear interrupts */
897 hw->mac.ops.stop_adapter(hw);
898
899 /* PHY ops must be identified and initialized prior to reset */
900
901 /* Init PHY and function pointers, perform SFP setup */
902 status = hw->phy.ops.init(hw);
903
904 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
905 goto reset_hw_out;
906
907 /* Setup SFP module if there is one present. */
908 if (hw->phy.sfp_setup_needed) {
909 status = hw->mac.ops.setup_sfp(hw);
910 hw->phy.sfp_setup_needed = false;
911 }
912
913 /* Reset PHY */
914 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
915 hw->phy.ops.reset(hw);
916
917 /*
918 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
919 * access and verify no pending requests before reset
920 */
921 status = ixgbe_disable_pcie_master(hw);
922 if (status != 0) {
923 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
924 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
925 }
926
927 /*
928 * Issue global reset to the MAC. This needs to be a SW reset.
929 * If link reset is used, it might reset the MAC when mng is using it
930 */
931 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
932 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
933 IXGBE_WRITE_FLUSH(hw);
934
935 /* Poll for reset bit to self-clear indicating reset is complete */
936 for (i = 0; i < 10; i++) {
937 udelay(1);
938 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
939 if (!(ctrl & IXGBE_CTRL_RST))
940 break;
941 }
942 if (ctrl & IXGBE_CTRL_RST) {
943 status = IXGBE_ERR_RESET_FAILED;
944 hw_dbg(hw, "Reset polling failed to complete.\n");
945 }
946 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
947 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
948 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
949 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
950
951 msleep(50);
952
953
954
955 /*
956 * Store the original AUTOC/AUTOC2 values if they have not been
957 * stored off yet. Otherwise restore the stored original
958 * values since the reset operation sets back to defaults.
959 */
960 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
961 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
962 if (hw->mac.orig_link_settings_stored == false) {
963 hw->mac.orig_autoc = autoc;
964 hw->mac.orig_autoc2 = autoc2;
965 hw->mac.orig_link_settings_stored = true;
966 } else {
967 if (autoc != hw->mac.orig_autoc)
968 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
969 IXGBE_AUTOC_AN_RESTART));
970
971 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
972 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
973 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
974 autoc2 |= (hw->mac.orig_autoc2 &
975 IXGBE_AUTOC2_UPPER_MASK);
976 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
977 }
978 }
979
980 /*
981 * Store MAC address from RAR0, clear receive address registers, and
982 * clear the multicast table. Also reset num_rar_entries to 128,
983 * since we modify this value when programming the SAN MAC address.
984 */
985 hw->mac.num_rar_entries = 128;
986 hw->mac.ops.init_rx_addrs(hw);
987
988 /* Store the permanent mac address */
989 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
990
991 /* Store the permanent SAN mac address */
992 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
993
994 /* Add the SAN MAC address to the RAR only if it's a valid address */
995 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
996 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
997 hw->mac.san_addr, 0, IXGBE_RAH_AV);
998
999 /* Reserve the last RAR for the SAN MAC address */
1000 hw->mac.num_rar_entries--;
1001 }
1002
1003 reset_hw_out:
1004 return status;
1005 }
1006
1007 /**
1008 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
1009 * @hw: pointer to hardware struct
1010 * @rar: receive address register index to disassociate
1011 * @vmdq: VMDq pool index to remove from the rar
1012 **/
1013 static s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
1014 {
1015 u32 mpsar_lo, mpsar_hi;
1016 u32 rar_entries = hw->mac.num_rar_entries;
1017
1018 if (rar < rar_entries) {
1019 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
1020 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
1021
1022 if (!mpsar_lo && !mpsar_hi)
1023 goto done;
1024
1025 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
1026 if (mpsar_lo) {
1027 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
1028 mpsar_lo = 0;
1029 }
1030 if (mpsar_hi) {
1031 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
1032 mpsar_hi = 0;
1033 }
1034 } else if (vmdq < 32) {
1035 mpsar_lo &= ~(1 << vmdq);
1036 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
1037 } else {
1038 mpsar_hi &= ~(1 << (vmdq - 32));
1039 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
1040 }
1041
1042 /* was that the last pool using this rar? */
1043 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
1044 hw->mac.ops.clear_rar(hw, rar);
1045 } else {
1046 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
1047 }
1048
1049 done:
1050 return 0;
1051 }
1052
1053 /**
1054 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
1055 * @hw: pointer to hardware struct
1056 * @rar: receive address register index to associate with a VMDq index
1057 * @vmdq: VMDq pool index
1058 **/
1059 static s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
1060 {
1061 u32 mpsar;
1062 u32 rar_entries = hw->mac.num_rar_entries;
1063
1064 if (rar < rar_entries) {
1065 if (vmdq < 32) {
1066 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
1067 mpsar |= 1 << vmdq;
1068 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
1069 } else {
1070 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
1071 mpsar |= 1 << (vmdq - 32);
1072 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
1073 }
1074 } else {
1075 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
1076 }
1077 return 0;
1078 }
1079
1080 /**
1081 * ixgbe_set_vfta_82599 - Set VLAN filter table
1082 * @hw: pointer to hardware structure
1083 * @vlan: VLAN id to write to VLAN filter
1084 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
1085 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
1086 *
1087 * Turn on/off specified VLAN in the VLAN filter table.
1088 **/
1089 static s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
1090 bool vlan_on)
1091 {
1092 u32 regindex;
1093 u32 bitindex;
1094 u32 bits;
1095 u32 first_empty_slot;
1096
1097 if (vlan > 4095)
1098 return IXGBE_ERR_PARAM;
1099
1100 /*
1101 * this is a 2 part operation - first the VFTA, then the
1102 * VLVF and VLVFB if vind is set
1103 */
1104
1105 /* Part 1
1106 * The VFTA is a bitstring made up of 128 32-bit registers
1107 * that enable the particular VLAN id, much like the MTA:
1108 * bits[11-5]: which register
1109 * bits[4-0]: which bit in the register
1110 */
1111 regindex = (vlan >> 5) & 0x7F;
1112 bitindex = vlan & 0x1F;
1113 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
1114 if (vlan_on)
1115 bits |= (1 << bitindex);
1116 else
1117 bits &= ~(1 << bitindex);
1118 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
1119
1120
1121 /* Part 2
1122 * If the vind is set
1123 * Either vlan_on
1124 * make sure the vlan is in VLVF
1125 * set the vind bit in the matching VLVFB
1126 * Or !vlan_on
1127 * clear the pool bit and possibly the vind
1128 */
1129 if (vind) {
1130 /* find the vlanid or the first empty slot */
1131 first_empty_slot = 0;
1132
1133 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
1134 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
1135 if (!bits && !first_empty_slot)
1136 first_empty_slot = regindex;
1137 else if ((bits & 0x0FFF) == vlan)
1138 break;
1139 }
1140
1141 if (regindex >= IXGBE_VLVF_ENTRIES) {
1142 if (first_empty_slot)
1143 regindex = first_empty_slot;
1144 else {
1145 hw_dbg(hw, "No space in VLVF.\n");
1146 goto out;
1147 }
1148 }
1149
1150 if (vlan_on) {
1151 /* set the pool bit */
1152 if (vind < 32) {
1153 bits = IXGBE_READ_REG(hw,
1154 IXGBE_VLVFB(regindex * 2));
1155 bits |= (1 << vind);
1156 IXGBE_WRITE_REG(hw,
1157 IXGBE_VLVFB(regindex * 2), bits);
1158 } else {
1159 bits = IXGBE_READ_REG(hw,
1160 IXGBE_VLVFB((regindex * 2) + 1));
1161 bits |= (1 << vind);
1162 IXGBE_WRITE_REG(hw,
1163 IXGBE_VLVFB((regindex * 2) + 1), bits);
1164 }
1165 } else {
1166 /* clear the pool bit */
1167 if (vind < 32) {
1168 bits = IXGBE_READ_REG(hw,
1169 IXGBE_VLVFB(regindex * 2));
1170 bits &= ~(1 << vind);
1171 IXGBE_WRITE_REG(hw,
1172 IXGBE_VLVFB(regindex * 2), bits);
1173 bits |= IXGBE_READ_REG(hw,
1174 IXGBE_VLVFB((regindex * 2) + 1));
1175 } else {
1176 bits = IXGBE_READ_REG(hw,
1177 IXGBE_VLVFB((regindex * 2) + 1));
1178 bits &= ~(1 << vind);
1179 IXGBE_WRITE_REG(hw,
1180 IXGBE_VLVFB((regindex * 2) + 1), bits);
1181 bits |= IXGBE_READ_REG(hw,
1182 IXGBE_VLVFB(regindex * 2));
1183 }
1184 }
1185
1186 if (bits)
1187 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
1188 (IXGBE_VLVF_VIEN | vlan));
1189 else
1190 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
1191 }
1192
1193 out:
1194 return 0;
1195 }
1196
1197 /**
1198 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
1199 * @hw: pointer to hardware structure
1200 *
1201 * Clears the VLAN filer table, and the VMDq index associated with the filter
1202 **/
1203 static s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
1204 {
1205 u32 offset;
1206
1207 for (offset = 0; offset < hw->mac.vft_size; offset++)
1208 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1209
1210 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
1211 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
1212 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
1213 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
1214 }
1215
1216 return 0;
1217 }
1218
1219 /**
1220 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1221 * @hw: pointer to hardware structure
1222 **/
1223 static s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
1224 {
1225 int i;
1226 hw_dbg(hw, " Clearing UTA\n");
1227
1228 for (i = 0; i < 128; i++)
1229 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1230
1231 return 0;
1232 }
1233
1234 /**
1235 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1236 * @hw: pointer to hardware structure
1237 **/
1238 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1239 {
1240 int i;
1241 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1242 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1243
1244 /*
1245 * Before starting reinitialization process,
1246 * FDIRCMD.CMD must be zero.
1247 */
1248 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1249 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1250 IXGBE_FDIRCMD_CMD_MASK))
1251 break;
1252 udelay(10);
1253 }
1254 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1255 hw_dbg(hw ,"Flow Director previous command isn't complete, "
1256 "aborting table re-initialization. \n");
1257 return IXGBE_ERR_FDIR_REINIT_FAILED;
1258 }
1259
1260 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1261 IXGBE_WRITE_FLUSH(hw);
1262 /*
1263 * 82599 adapters flow director init flow cannot be restarted,
1264 * Workaround 82599 silicon errata by performing the following steps
1265 * before re-writing the FDIRCTRL control register with the same value.
1266 * - write 1 to bit 8 of FDIRCMD register &
1267 * - write 0 to bit 8 of FDIRCMD register
1268 */
1269 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1270 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1271 IXGBE_FDIRCMD_CLEARHT));
1272 IXGBE_WRITE_FLUSH(hw);
1273 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1274 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1275 ~IXGBE_FDIRCMD_CLEARHT));
1276 IXGBE_WRITE_FLUSH(hw);
1277 /*
1278 * Clear FDIR Hash register to clear any leftover hashes
1279 * waiting to be programmed.
1280 */
1281 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1282 IXGBE_WRITE_FLUSH(hw);
1283
1284 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1285 IXGBE_WRITE_FLUSH(hw);
1286
1287 /* Poll init-done after we write FDIRCTRL register */
1288 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1289 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1290 IXGBE_FDIRCTRL_INIT_DONE)
1291 break;
1292 udelay(10);
1293 }
1294 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1295 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1296 return IXGBE_ERR_FDIR_REINIT_FAILED;
1297 }
1298
1299 /* Clear FDIR statistics registers (read to clear) */
1300 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1301 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1302 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1303 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1304 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1305
1306 return 0;
1307 }
1308
1309 /**
1310 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1311 * @hw: pointer to hardware structure
1312 * @pballoc: which mode to allocate filters with
1313 **/
1314 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1315 {
1316 u32 fdirctrl = 0;
1317 u32 pbsize;
1318 int i;
1319
1320 /*
1321 * Before enabling Flow Director, the Rx Packet Buffer size
1322 * must be reduced. The new value is the current size minus
1323 * flow director memory usage size.
1324 */
1325 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1326 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1327 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1328
1329 /*
1330 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1331 * intialized to zero for non DCB mode otherwise actual total RX PB
1332 * would be bigger than programmed and filter space would run into
1333 * the PB 0 region.
1334 */
1335 for (i = 1; i < 8; i++)
1336 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1337
1338 /* Send interrupt when 64 filters are left */
1339 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1340
1341 /* Set the maximum length per hash bucket to 0xA filters */
1342 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1343
1344 switch (pballoc) {
1345 case IXGBE_FDIR_PBALLOC_64K:
1346 /* 8k - 1 signature filters */
1347 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1348 break;
1349 case IXGBE_FDIR_PBALLOC_128K:
1350 /* 16k - 1 signature filters */
1351 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1352 break;
1353 case IXGBE_FDIR_PBALLOC_256K:
1354 /* 32k - 1 signature filters */
1355 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1356 break;
1357 default:
1358 /* bad value */
1359 return IXGBE_ERR_CONFIG;
1360 };
1361
1362 /* Move the flexible bytes to use the ethertype - shift 6 words */
1363 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1364
1365 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1366
1367 /* Prime the keys for hashing */
1368 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1369 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1370 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1371 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1372
1373 /*
1374 * Poll init-done after we write the register. Estimated times:
1375 * 10G: PBALLOC = 11b, timing is 60us
1376 * 1G: PBALLOC = 11b, timing is 600us
1377 * 100M: PBALLOC = 11b, timing is 6ms
1378 *
1379 * Multiple these timings by 4 if under full Rx load
1380 *
1381 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1382 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1383 * this might not finish in our poll time, but we can live with that
1384 * for now.
1385 */
1386 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1387 IXGBE_WRITE_FLUSH(hw);
1388 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1389 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1390 IXGBE_FDIRCTRL_INIT_DONE)
1391 break;
1392 msleep(1);
1393 }
1394 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1395 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1396
1397 return 0;
1398 }
1399
1400 /**
1401 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1402 * @hw: pointer to hardware structure
1403 * @pballoc: which mode to allocate filters with
1404 **/
1405 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1406 {
1407 u32 fdirctrl = 0;
1408 u32 pbsize;
1409 int i;
1410
1411 /*
1412 * Before enabling Flow Director, the Rx Packet Buffer size
1413 * must be reduced. The new value is the current size minus
1414 * flow director memory usage size.
1415 */
1416 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1417 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1418 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1419
1420 /*
1421 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1422 * intialized to zero for non DCB mode otherwise actual total RX PB
1423 * would be bigger than programmed and filter space would run into
1424 * the PB 0 region.
1425 */
1426 for (i = 1; i < 8; i++)
1427 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1428
1429 /* Send interrupt when 64 filters are left */
1430 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1431
1432 switch (pballoc) {
1433 case IXGBE_FDIR_PBALLOC_64K:
1434 /* 2k - 1 perfect filters */
1435 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1436 break;
1437 case IXGBE_FDIR_PBALLOC_128K:
1438 /* 4k - 1 perfect filters */
1439 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1440 break;
1441 case IXGBE_FDIR_PBALLOC_256K:
1442 /* 8k - 1 perfect filters */
1443 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1444 break;
1445 default:
1446 /* bad value */
1447 return IXGBE_ERR_CONFIG;
1448 };
1449
1450 /* Turn perfect match filtering on */
1451 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1452 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1453
1454 /* Move the flexible bytes to use the ethertype - shift 6 words */
1455 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1456
1457 /* Prime the keys for hashing */
1458 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1459 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1460 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1461 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1462
1463 /*
1464 * Poll init-done after we write the register. Estimated times:
1465 * 10G: PBALLOC = 11b, timing is 60us
1466 * 1G: PBALLOC = 11b, timing is 600us
1467 * 100M: PBALLOC = 11b, timing is 6ms
1468 *
1469 * Multiple these timings by 4 if under full Rx load
1470 *
1471 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1472 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1473 * this might not finish in our poll time, but we can live with that
1474 * for now.
1475 */
1476
1477 /* Set the maximum length per hash bucket to 0xA filters */
1478 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1479
1480 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1481 IXGBE_WRITE_FLUSH(hw);
1482 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1483 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1484 IXGBE_FDIRCTRL_INIT_DONE)
1485 break;
1486 msleep(1);
1487 }
1488 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1489 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1490
1491 return 0;
1492 }
1493
1494
1495 /**
1496 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1497 * @stream: input bitstream to compute the hash on
1498 * @key: 32-bit hash key
1499 **/
1500 static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input,
1501 u32 key)
1502 {
1503 /*
1504 * The algorithm is as follows:
1505 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1506 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1507 * and A[n] x B[n] is bitwise AND between same length strings
1508 *
1509 * K[n] is 16 bits, defined as:
1510 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1511 * for n modulo 32 < 15, K[n] =
1512 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1513 *
1514 * S[n] is 16 bits, defined as:
1515 * for n >= 15, S[n] = S[n:n - 15]
1516 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1517 *
1518 * To simplify for programming, the algorithm is implemented
1519 * in software this way:
1520 *
1521 * Key[31:0], Stream[335:0]
1522 *
1523 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
1524 * int_key[350:0] = tmp_key[351:1]
1525 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
1526 *
1527 * hash[15:0] = 0;
1528 * for (i = 0; i < 351; i++) {
1529 * if (int_key[i])
1530 * hash ^= int_stream[(i + 15):i];
1531 * }
1532 */
1533
1534 union {
1535 u64 fill[6];
1536 u32 key[11];
1537 u8 key_stream[44];
1538 } tmp_key;
1539
1540 u8 *stream = (u8 *)atr_input;
1541 u8 int_key[44]; /* upper-most bit unused */
1542 u8 hash_str[46]; /* upper-most 2 bits unused */
1543 u16 hash_result = 0;
1544 int i, j, k, h;
1545
1546 /*
1547 * Initialize the fill member to prevent warnings
1548 * on some compilers
1549 */
1550 tmp_key.fill[0] = 0;
1551
1552 /* First load the temporary key stream */
1553 for (i = 0; i < 6; i++) {
1554 u64 fillkey = ((u64)key << 32) | key;
1555 tmp_key.fill[i] = fillkey;
1556 }
1557
1558 /*
1559 * Set the interim key for the hashing. Bit 352 is unused, so we must
1560 * shift and compensate when building the key.
1561 */
1562
1563 int_key[0] = tmp_key.key_stream[0] >> 1;
1564 for (i = 1, j = 0; i < 44; i++) {
1565 unsigned int this_key = tmp_key.key_stream[j] << 7;
1566 j++;
1567 int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
1568 }
1569
1570 /*
1571 * Set the interim bit string for the hashing. Bits 368 and 367 are
1572 * unused, so shift and compensate when building the string.
1573 */
1574 hash_str[0] = (stream[40] & 0x7f) >> 1;
1575 for (i = 1, j = 40; i < 46; i++) {
1576 unsigned int this_str = stream[j] << 7;
1577 j++;
1578 if (j > 41)
1579 j = 0;
1580 hash_str[i] = (u8)(this_str | (stream[j] >> 1));
1581 }
1582
1583 /*
1584 * Now compute the hash. i is the index into hash_str, j is into our
1585 * key stream, k is counting the number of bits, and h interates within
1586 * each byte.
1587 */
1588 for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
1589 for (h = 0; h < 8 && k < 351; h++, k++) {
1590 if (int_key[j] & (1 << h)) {
1591 /*
1592 * Key bit is set, XOR in the current 16-bit
1593 * string. Example of processing:
1594 * h = 0,
1595 * tmp = (hash_str[i - 2] & 0 << 16) |
1596 * (hash_str[i - 1] & 0xff << 8) |
1597 * (hash_str[i] & 0xff >> 0)
1598 * So tmp = hash_str[15 + k:k], since the
1599 * i + 2 clause rolls off the 16-bit value
1600 * h = 7,
1601 * tmp = (hash_str[i - 2] & 0x7f << 9) |
1602 * (hash_str[i - 1] & 0xff << 1) |
1603 * (hash_str[i] & 0x80 >> 7)
1604 */
1605 int tmp = (hash_str[i] >> h);
1606 tmp |= (hash_str[i - 1] << (8 - h));
1607 tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
1608 << (16 - h);
1609 hash_result ^= (u16)tmp;
1610 }
1611 }
1612 }
1613
1614 return hash_result;
1615 }
1616
1617 /**
1618 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
1619 * @input: input stream to modify
1620 * @vlan: the VLAN id to load
1621 **/
1622 s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
1623 {
1624 input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8;
1625 input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff;
1626
1627 return 0;
1628 }
1629
1630 /**
1631 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
1632 * @input: input stream to modify
1633 * @src_addr: the IP address to load
1634 **/
1635 s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
1636 {
1637 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24;
1638 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] =
1639 (src_addr >> 16) & 0xff;
1640 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] =
1641 (src_addr >> 8) & 0xff;
1642 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff;
1643
1644 return 0;
1645 }
1646
1647 /**
1648 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
1649 * @input: input stream to modify
1650 * @dst_addr: the IP address to load
1651 **/
1652 s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
1653 {
1654 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24;
1655 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] =
1656 (dst_addr >> 16) & 0xff;
1657 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] =
1658 (dst_addr >> 8) & 0xff;
1659 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff;
1660
1661 return 0;
1662 }
1663
1664 /**
1665 * ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address
1666 * @input: input stream to modify
1667 * @src_addr_1: the first 4 bytes of the IP address to load
1668 * @src_addr_2: the second 4 bytes of the IP address to load
1669 * @src_addr_3: the third 4 bytes of the IP address to load
1670 * @src_addr_4: the fourth 4 bytes of the IP address to load
1671 **/
1672 s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input,
1673 u32 src_addr_1, u32 src_addr_2,
1674 u32 src_addr_3, u32 src_addr_4)
1675 {
1676 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET] = src_addr_4 & 0xff;
1677 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] =
1678 (src_addr_4 >> 8) & 0xff;
1679 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] =
1680 (src_addr_4 >> 16) & 0xff;
1681 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] = src_addr_4 >> 24;
1682
1683 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4] = src_addr_3 & 0xff;
1684 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] =
1685 (src_addr_3 >> 8) & 0xff;
1686 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] =
1687 (src_addr_3 >> 16) & 0xff;
1688 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] = src_addr_3 >> 24;
1689
1690 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8] = src_addr_2 & 0xff;
1691 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] =
1692 (src_addr_2 >> 8) & 0xff;
1693 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] =
1694 (src_addr_2 >> 16) & 0xff;
1695 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] = src_addr_2 >> 24;
1696
1697 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12] = src_addr_1 & 0xff;
1698 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] =
1699 (src_addr_1 >> 8) & 0xff;
1700 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] =
1701 (src_addr_1 >> 16) & 0xff;
1702 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] = src_addr_1 >> 24;
1703
1704 return 0;
1705 }
1706
1707 /**
1708 * ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address
1709 * @input: input stream to modify
1710 * @dst_addr_1: the first 4 bytes of the IP address to load
1711 * @dst_addr_2: the second 4 bytes of the IP address to load
1712 * @dst_addr_3: the third 4 bytes of the IP address to load
1713 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1714 **/
1715 s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input,
1716 u32 dst_addr_1, u32 dst_addr_2,
1717 u32 dst_addr_3, u32 dst_addr_4)
1718 {
1719 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET] = dst_addr_4 & 0xff;
1720 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] =
1721 (dst_addr_4 >> 8) & 0xff;
1722 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] =
1723 (dst_addr_4 >> 16) & 0xff;
1724 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] = dst_addr_4 >> 24;
1725
1726 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4] = dst_addr_3 & 0xff;
1727 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] =
1728 (dst_addr_3 >> 8) & 0xff;
1729 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] =
1730 (dst_addr_3 >> 16) & 0xff;
1731 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] = dst_addr_3 >> 24;
1732
1733 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8] = dst_addr_2 & 0xff;
1734 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] =
1735 (dst_addr_2 >> 8) & 0xff;
1736 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] =
1737 (dst_addr_2 >> 16) & 0xff;
1738 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] = dst_addr_2 >> 24;
1739
1740 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12] = dst_addr_1 & 0xff;
1741 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] =
1742 (dst_addr_1 >> 8) & 0xff;
1743 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] =
1744 (dst_addr_1 >> 16) & 0xff;
1745 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] = dst_addr_1 >> 24;
1746
1747 return 0;
1748 }
1749
1750 /**
1751 * ixgbe_atr_set_src_port_82599 - Sets the source port
1752 * @input: input stream to modify
1753 * @src_port: the source port to load
1754 **/
1755 s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
1756 {
1757 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8;
1758 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff;
1759
1760 return 0;
1761 }
1762
1763 /**
1764 * ixgbe_atr_set_dst_port_82599 - Sets the destination port
1765 * @input: input stream to modify
1766 * @dst_port: the destination port to load
1767 **/
1768 s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
1769 {
1770 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8;
1771 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff;
1772
1773 return 0;
1774 }
1775
1776 /**
1777 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
1778 * @input: input stream to modify
1779 * @flex_bytes: the flexible bytes to load
1780 **/
1781 s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
1782 {
1783 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8;
1784 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff;
1785
1786 return 0;
1787 }
1788
1789 /**
1790 * ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool
1791 * @input: input stream to modify
1792 * @vm_pool: the Virtual Machine pool to load
1793 **/
1794 s32 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input,
1795 u8 vm_pool)
1796 {
1797 input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET] = vm_pool;
1798
1799 return 0;
1800 }
1801
1802 /**
1803 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
1804 * @input: input stream to modify
1805 * @l4type: the layer 4 type value to load
1806 **/
1807 s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
1808 {
1809 input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type;
1810
1811 return 0;
1812 }
1813
1814 /**
1815 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
1816 * @input: input stream to search
1817 * @vlan: the VLAN id to load
1818 **/
1819 static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input,
1820 u16 *vlan)
1821 {
1822 *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
1823 *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
1824
1825 return 0;
1826 }
1827
1828 /**
1829 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
1830 * @input: input stream to search
1831 * @src_addr: the IP address to load
1832 **/
1833 static s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input,
1834 u32 *src_addr)
1835 {
1836 *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET];
1837 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8;
1838 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16;
1839 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24;
1840
1841 return 0;
1842 }
1843
1844 /**
1845 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
1846 * @input: input stream to search
1847 * @dst_addr: the IP address to load
1848 **/
1849 static s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input,
1850 u32 *dst_addr)
1851 {
1852 *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET];
1853 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8;
1854 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16;
1855 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24;
1856
1857 return 0;
1858 }
1859
1860 /**
1861 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
1862 * @input: input stream to search
1863 * @src_addr_1: the first 4 bytes of the IP address to load
1864 * @src_addr_2: the second 4 bytes of the IP address to load
1865 * @src_addr_3: the third 4 bytes of the IP address to load
1866 * @src_addr_4: the fourth 4 bytes of the IP address to load
1867 **/
1868 static s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
1869 u32 *src_addr_1, u32 *src_addr_2,
1870 u32 *src_addr_3, u32 *src_addr_4)
1871 {
1872 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12];
1873 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8;
1874 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16;
1875 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24;
1876
1877 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8];
1878 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8;
1879 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16;
1880 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24;
1881
1882 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4];
1883 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8;
1884 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16;
1885 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24;
1886
1887 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET];
1888 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8;
1889 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16;
1890 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24;
1891
1892 return 0;
1893 }
1894
1895 /**
1896 * ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address
1897 * @input: input stream to search
1898 * @dst_addr_1: the first 4 bytes of the IP address to load
1899 * @dst_addr_2: the second 4 bytes of the IP address to load
1900 * @dst_addr_3: the third 4 bytes of the IP address to load
1901 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1902 **/
1903 s32 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input,
1904 u32 *dst_addr_1, u32 *dst_addr_2,
1905 u32 *dst_addr_3, u32 *dst_addr_4)
1906 {
1907 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12];
1908 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] << 8;
1909 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] << 16;
1910 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] << 24;
1911
1912 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8];
1913 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] << 8;
1914 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] << 16;
1915 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] << 24;
1916
1917 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4];
1918 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] << 8;
1919 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] << 16;
1920 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] << 24;
1921
1922 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET];
1923 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] << 8;
1924 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] << 16;
1925 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] << 24;
1926
1927 return 0;
1928 }
1929
1930 /**
1931 * ixgbe_atr_get_src_port_82599 - Gets the source port
1932 * @input: input stream to modify
1933 * @src_port: the source port to load
1934 *
1935 * Even though the input is given in big-endian, the FDIRPORT registers
1936 * expect the ports to be programmed in little-endian. Hence the need to swap
1937 * endianness when retrieving the data. This can be confusing since the
1938 * internal hash engine expects it to be big-endian.
1939 **/
1940 static s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input,
1941 u16 *src_port)
1942 {
1943 *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8;
1944 *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1];
1945
1946 return 0;
1947 }
1948
1949 /**
1950 * ixgbe_atr_get_dst_port_82599 - Gets the destination port
1951 * @input: input stream to modify
1952 * @dst_port: the destination port to load
1953 *
1954 * Even though the input is given in big-endian, the FDIRPORT registers
1955 * expect the ports to be programmed in little-endian. Hence the need to swap
1956 * endianness when retrieving the data. This can be confusing since the
1957 * internal hash engine expects it to be big-endian.
1958 **/
1959 static s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input,
1960 u16 *dst_port)
1961 {
1962 *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8;
1963 *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1];
1964
1965 return 0;
1966 }
1967
1968 /**
1969 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
1970 * @input: input stream to modify
1971 * @flex_bytes: the flexible bytes to load
1972 **/
1973 static s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
1974 u16 *flex_byte)
1975 {
1976 *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET];
1977 *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8;
1978
1979 return 0;
1980 }
1981
1982 /**
1983 * ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool
1984 * @input: input stream to modify
1985 * @vm_pool: the Virtual Machine pool to load
1986 **/
1987 s32 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input,
1988 u8 *vm_pool)
1989 {
1990 *vm_pool = input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET];
1991
1992 return 0;
1993 }
1994
1995 /**
1996 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
1997 * @input: input stream to modify
1998 * @l4type: the layer 4 type value to load
1999 **/
2000 static s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input,
2001 u8 *l4type)
2002 {
2003 *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET];
2004
2005 return 0;
2006 }
2007
2008 /**
2009 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
2010 * @hw: pointer to hardware structure
2011 * @stream: input bitstream
2012 * @queue: queue index to direct traffic to
2013 **/
2014 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
2015 struct ixgbe_atr_input *input,
2016 u8 queue)
2017 {
2018 u64 fdirhashcmd;
2019 u64 fdircmd;
2020 u32 fdirhash;
2021 u16 bucket_hash, sig_hash;
2022 u8 l4type;
2023
2024 bucket_hash = ixgbe_atr_compute_hash_82599(input,
2025 IXGBE_ATR_BUCKET_HASH_KEY);
2026
2027 /* bucket_hash is only 15 bits */
2028 bucket_hash &= IXGBE_ATR_HASH_MASK;
2029
2030 sig_hash = ixgbe_atr_compute_hash_82599(input,
2031 IXGBE_ATR_SIGNATURE_HASH_KEY);
2032
2033 /* Get the l4type in order to program FDIRCMD properly */
2034 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
2035 ixgbe_atr_get_l4type_82599(input, &l4type);
2036
2037 /*
2038 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
2039 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
2040 */
2041 fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
2042
2043 fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
2044 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN);
2045
2046 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
2047 case IXGBE_ATR_L4TYPE_TCP:
2048 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
2049 break;
2050 case IXGBE_ATR_L4TYPE_UDP:
2051 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
2052 break;
2053 case IXGBE_ATR_L4TYPE_SCTP:
2054 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
2055 break;
2056 default:
2057 hw_dbg(hw, "Error on l4type input\n");
2058 return IXGBE_ERR_CONFIG;
2059 }
2060
2061 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK)
2062 fdircmd |= IXGBE_FDIRCMD_IPV6;
2063
2064 fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT);
2065 fdirhashcmd = ((fdircmd << 32) | fdirhash);
2066
2067 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
2068
2069 return 0;
2070 }
2071
2072 /**
2073 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
2074 * @hw: pointer to hardware structure
2075 * @input: input bitstream
2076 * @queue: queue index to direct traffic to
2077 *
2078 * Note that the caller to this function must lock before calling, since the
2079 * hardware writes must be protected from one another.
2080 **/
2081 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
2082 struct ixgbe_atr_input *input,
2083 u16 soft_id,
2084 u8 queue)
2085 {
2086 u32 fdircmd = 0;
2087 u32 fdirhash;
2088 u32 src_ipv4, dst_ipv4;
2089 u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4;
2090 u16 src_port, dst_port, vlan_id, flex_bytes;
2091 u16 bucket_hash;
2092 u8 l4type;
2093
2094 /* Get our input values */
2095 ixgbe_atr_get_l4type_82599(input, &l4type);
2096
2097 /*
2098 * Check l4type formatting, and bail out before we touch the hardware
2099 * if there's a configuration issue
2100 */
2101 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
2102 case IXGBE_ATR_L4TYPE_TCP:
2103 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
2104 break;
2105 case IXGBE_ATR_L4TYPE_UDP:
2106 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
2107 break;
2108 case IXGBE_ATR_L4TYPE_SCTP:
2109 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
2110 break;
2111 default:
2112 hw_dbg(hw, "Error on l4type input\n");
2113 return IXGBE_ERR_CONFIG;
2114 }
2115
2116 bucket_hash = ixgbe_atr_compute_hash_82599(input,
2117 IXGBE_ATR_BUCKET_HASH_KEY);
2118
2119 /* bucket_hash is only 15 bits */
2120 bucket_hash &= IXGBE_ATR_HASH_MASK;
2121
2122 ixgbe_atr_get_vlan_id_82599(input, &vlan_id);
2123 ixgbe_atr_get_src_port_82599(input, &src_port);
2124 ixgbe_atr_get_dst_port_82599(input, &dst_port);
2125 ixgbe_atr_get_flex_byte_82599(input, &flex_bytes);
2126
2127 fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
2128
2129 /* Now figure out if we're IPv4 or IPv6 */
2130 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
2131 /* IPv6 */
2132 ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2,
2133 &src_ipv6_3, &src_ipv6_4);
2134
2135 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1);
2136 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2);
2137 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3);
2138 /* The last 4 bytes is the same register as IPv4 */
2139 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4);
2140
2141 fdircmd |= IXGBE_FDIRCMD_IPV6;
2142 fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH;
2143 } else {
2144 /* IPv4 */
2145 ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4);
2146 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4);
2147
2148 }
2149
2150 ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4);
2151 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4);
2152
2153 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id |
2154 (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
2155 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port |
2156 (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
2157
2158 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW;
2159 fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE;
2160 fdircmd |= IXGBE_FDIRCMD_LAST;
2161 fdircmd |= IXGBE_FDIRCMD_QUEUE_EN;
2162 fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
2163
2164 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
2165 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
2166
2167 return 0;
2168 }
2169 /**
2170 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2171 * @hw: pointer to hardware structure
2172 * @reg: analog register to read
2173 * @val: read value
2174 *
2175 * Performs read operation to Omer analog register specified.
2176 **/
2177 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
2178 {
2179 u32 core_ctl;
2180
2181 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2182 (reg << 8));
2183 IXGBE_WRITE_FLUSH(hw);
2184 udelay(10);
2185 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2186 *val = (u8)core_ctl;
2187
2188 return 0;
2189 }
2190
2191 /**
2192 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2193 * @hw: pointer to hardware structure
2194 * @reg: atlas register to write
2195 * @val: value to write
2196 *
2197 * Performs write operation to Omer analog register specified.
2198 **/
2199 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
2200 {
2201 u32 core_ctl;
2202
2203 core_ctl = (reg << 8) | val;
2204 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2205 IXGBE_WRITE_FLUSH(hw);
2206 udelay(10);
2207
2208 return 0;
2209 }
2210
2211 /**
2212 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2213 * @hw: pointer to hardware structure
2214 *
2215 * Starts the hardware using the generic start_hw function.
2216 * Then performs device-specific:
2217 * Clears the rate limiter registers.
2218 **/
2219 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
2220 {
2221 u32 q_num;
2222 s32 ret_val;
2223
2224 ret_val = ixgbe_start_hw_generic(hw);
2225
2226 /* Clear the rate limiters */
2227 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
2228 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
2229 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
2230 }
2231 IXGBE_WRITE_FLUSH(hw);
2232
2233 /* We need to run link autotry after the driver loads */
2234 hw->mac.autotry_restart = true;
2235
2236 if (ret_val == 0)
2237 ret_val = ixgbe_verify_fw_version_82599(hw);
2238
2239 return ret_val;
2240 }
2241
2242 /**
2243 * ixgbe_identify_phy_82599 - Get physical layer module
2244 * @hw: pointer to hardware structure
2245 *
2246 * Determines the physical layer module found on the current adapter.
2247 **/
2248 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2249 {
2250 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
2251 status = ixgbe_identify_phy_generic(hw);
2252 if (status != 0)
2253 status = ixgbe_identify_sfp_module_generic(hw);
2254 return status;
2255 }
2256
2257 /**
2258 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2259 * @hw: pointer to hardware structure
2260 *
2261 * Determines physical layer capabilities of the current configuration.
2262 **/
2263 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2264 {
2265 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2266 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2267 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2268 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2269 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2270 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2271 u16 ext_ability = 0;
2272 u8 comp_codes_10g = 0;
2273
2274 hw->phy.ops.identify(hw);
2275
2276 if (hw->phy.type == ixgbe_phy_tn ||
2277 hw->phy.type == ixgbe_phy_cu_unknown) {
2278 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
2279 &ext_ability);
2280 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
2281 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2282 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
2283 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2284 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
2285 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2286 goto out;
2287 }
2288
2289 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2290 case IXGBE_AUTOC_LMS_1G_AN:
2291 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2292 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2293 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2294 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2295 goto out;
2296 } else
2297 /* SFI mode so read SFP module */
2298 goto sfp_check;
2299 break;
2300 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2301 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2302 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2303 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2304 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2305 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2306 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2307 goto out;
2308 break;
2309 case IXGBE_AUTOC_LMS_10G_SERIAL:
2310 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2311 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2312 goto out;
2313 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2314 goto sfp_check;
2315 break;
2316 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2317 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2318 if (autoc & IXGBE_AUTOC_KX_SUPP)
2319 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2320 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2321 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2322 if (autoc & IXGBE_AUTOC_KR_SUPP)
2323 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2324 goto out;
2325 break;
2326 default:
2327 goto out;
2328 break;
2329 }
2330
2331 sfp_check:
2332 /* SFP check must be done last since DA modules are sometimes used to
2333 * test KR mode - we need to id KR mode correctly before SFP module.
2334 * Call identify_sfp because the pluggable module may have changed */
2335 hw->phy.ops.identify_sfp(hw);
2336 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2337 goto out;
2338
2339 switch (hw->phy.type) {
2340 case ixgbe_phy_tw_tyco:
2341 case ixgbe_phy_tw_unknown:
2342 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2343 break;
2344 case ixgbe_phy_sfp_avago:
2345 case ixgbe_phy_sfp_ftl:
2346 case ixgbe_phy_sfp_intel:
2347 case ixgbe_phy_sfp_unknown:
2348 hw->phy.ops.read_i2c_eeprom(hw,
2349 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2350 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2351 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2352 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2353 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2354 break;
2355 default:
2356 break;
2357 }
2358
2359 out:
2360 return physical_layer;
2361 }
2362
2363 /**
2364 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2365 * @hw: pointer to hardware structure
2366 * @regval: register value to write to RXCTRL
2367 *
2368 * Enables the Rx DMA unit for 82599
2369 **/
2370 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2371 {
2372 #define IXGBE_MAX_SECRX_POLL 30
2373 int i;
2374 int secrxreg;
2375
2376 /*
2377 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2378 * If traffic is incoming before we enable the Rx unit, it could hang
2379 * the Rx DMA unit. Therefore, make sure the security engine is
2380 * completely disabled prior to enabling the Rx unit.
2381 */
2382 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2383 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2384 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2385 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2386 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2387 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2388 break;
2389 else
2390 udelay(10);
2391 }
2392
2393 /* For informational purposes only */
2394 if (i >= IXGBE_MAX_SECRX_POLL)
2395 hw_dbg(hw, "Rx unit being enabled before security "
2396 "path fully disabled. Continuing with init.\n");
2397
2398 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2399 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2400 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2401 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2402 IXGBE_WRITE_FLUSH(hw);
2403
2404 return 0;
2405 }
2406
2407 /**
2408 * ixgbe_get_device_caps_82599 - Get additional device capabilities
2409 * @hw: pointer to hardware structure
2410 * @device_caps: the EEPROM word with the extra device capabilities
2411 *
2412 * This function will read the EEPROM location for the device capabilities,
2413 * and return the word through device_caps.
2414 **/
2415 static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
2416 {
2417 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
2418
2419 return 0;
2420 }
2421
2422 /**
2423 * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599
2424 * @hw: pointer to hardware structure
2425 * @san_mac_offset: SAN MAC address offset
2426 *
2427 * This function will read the EEPROM location for the SAN MAC address
2428 * pointer, and returns the value at that location. This is used in both
2429 * get and set mac_addr routines.
2430 **/
2431 static s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw,
2432 u16 *san_mac_offset)
2433 {
2434 /*
2435 * First read the EEPROM pointer to see if the MAC addresses are
2436 * available.
2437 */
2438 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2439
2440 return 0;
2441 }
2442
2443 /**
2444 * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599
2445 * @hw: pointer to hardware structure
2446 * @san_mac_addr: SAN MAC address
2447 *
2448 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2449 * per-port, so set_lan_id() must be called before reading the addresses.
2450 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2451 * upon for non-SFP connections, so we must call it here.
2452 **/
2453 static s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr)
2454 {
2455 u16 san_mac_data, san_mac_offset;
2456 u8 i;
2457
2458 /*
2459 * First read the EEPROM pointer to see if the MAC addresses are
2460 * available. If they're not, no point in calling set_lan_id() here.
2461 */
2462 ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset);
2463
2464 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2465 /*
2466 * No addresses available in this EEPROM. It's not an
2467 * error though, so just wipe the local address and return.
2468 */
2469 for (i = 0; i < 6; i++)
2470 san_mac_addr[i] = 0xFF;
2471
2472 goto san_mac_addr_out;
2473 }
2474
2475 /* make sure we know which port we need to program */
2476 hw->mac.ops.set_lan_id(hw);
2477 /* apply the port offset to the address offset */
2478 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2479 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2480 for (i = 0; i < 3; i++) {
2481 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2482 san_mac_addr[i * 2] = (u8)(san_mac_data);
2483 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2484 san_mac_offset++;
2485 }
2486
2487 san_mac_addr_out:
2488 return 0;
2489 }
2490
2491 /**
2492 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2493 * @hw: pointer to hardware structure
2494 *
2495 * Verifies that installed the firmware version is 0.6 or higher
2496 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2497 *
2498 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2499 * if the FW version is not supported.
2500 **/
2501 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2502 {
2503 s32 status = IXGBE_ERR_EEPROM_VERSION;
2504 u16 fw_offset, fw_ptp_cfg_offset;
2505 u16 fw_version = 0;
2506
2507 /* firmware check is only necessary for SFI devices */
2508 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2509 status = 0;
2510 goto fw_version_out;
2511 }
2512
2513 /* get the offset to the Firmware Module block */
2514 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2515
2516 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2517 goto fw_version_out;
2518
2519 /* get the offset to the Pass Through Patch Configuration block */
2520 hw->eeprom.ops.read(hw, (fw_offset +
2521 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2522 &fw_ptp_cfg_offset);
2523
2524 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2525 goto fw_version_out;
2526
2527 /* get the firmware version */
2528 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2529 IXGBE_FW_PATCH_VERSION_4),
2530 &fw_version);
2531
2532 if (fw_version > 0x5)
2533 status = 0;
2534
2535 fw_version_out:
2536 return status;
2537 }
2538
2539 static struct ixgbe_mac_operations mac_ops_82599 = {
2540 .init_hw = &ixgbe_init_hw_generic,
2541 .reset_hw = &ixgbe_reset_hw_82599,
2542 .start_hw = &ixgbe_start_hw_82599,
2543 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2544 .get_media_type = &ixgbe_get_media_type_82599,
2545 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2546 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2547 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2548 .get_san_mac_addr = &ixgbe_get_san_mac_addr_82599,
2549 .get_device_caps = &ixgbe_get_device_caps_82599,
2550 .stop_adapter = &ixgbe_stop_adapter_generic,
2551 .get_bus_info = &ixgbe_get_bus_info_generic,
2552 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2553 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2554 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2555 .setup_link = &ixgbe_setup_mac_link_82599,
2556 .check_link = &ixgbe_check_mac_link_82599,
2557 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2558 .led_on = &ixgbe_led_on_generic,
2559 .led_off = &ixgbe_led_off_generic,
2560 .blink_led_start = &ixgbe_blink_led_start_generic,
2561 .blink_led_stop = &ixgbe_blink_led_stop_generic,
2562 .set_rar = &ixgbe_set_rar_generic,
2563 .clear_rar = &ixgbe_clear_rar_generic,
2564 .set_vmdq = &ixgbe_set_vmdq_82599,
2565 .clear_vmdq = &ixgbe_clear_vmdq_82599,
2566 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2567 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
2568 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2569 .enable_mc = &ixgbe_enable_mc_generic,
2570 .disable_mc = &ixgbe_disable_mc_generic,
2571 .clear_vfta = &ixgbe_clear_vfta_82599,
2572 .set_vfta = &ixgbe_set_vfta_82599,
2573 .fc_enable = &ixgbe_fc_enable_generic,
2574 .init_uta_tables = &ixgbe_init_uta_tables_82599,
2575 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2576 };
2577
2578 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2579 .init_params = &ixgbe_init_eeprom_params_generic,
2580 .read = &ixgbe_read_eeprom_generic,
2581 .write = &ixgbe_write_eeprom_generic,
2582 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2583 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2584 };
2585
2586 static struct ixgbe_phy_operations phy_ops_82599 = {
2587 .identify = &ixgbe_identify_phy_82599,
2588 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2589 .init = &ixgbe_init_phy_ops_82599,
2590 .reset = &ixgbe_reset_phy_generic,
2591 .read_reg = &ixgbe_read_phy_reg_generic,
2592 .write_reg = &ixgbe_write_phy_reg_generic,
2593 .setup_link = &ixgbe_setup_phy_link_generic,
2594 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2595 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2596 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2597 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2598 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2599 };
2600
2601 struct ixgbe_info ixgbe_82599_info = {
2602 .mac = ixgbe_mac_82599EB,
2603 .get_invariants = &ixgbe_get_invariants_82599,
2604 .mac_ops = &mac_ops_82599,
2605 .eeprom_ops = &eeprom_ops_82599,
2606 .phy_ops = &phy_ops_82599,
2607 };
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