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On Tue, Nov 06, 2007 at 02:33:53AM -0800, akpm@linux-foundation.org wrote:
[mmotm.git] / drivers / net / wireless / b43 / phy_lp.c
blobc6987b147af4d50a829347b037c51b5d0cb13f9b
1 /*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11a/g LP-PHY driver
5
6 Copyright (c) 2008-2009 Michael Buesch <mb@bu3sch.de>
7 Copyright (c) 2009 Gábor Stefanik <netrolller.3d@gmail.com>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22 Boston, MA 02110-1301, USA.
23
24 */
25
26 #include "b43.h"
27 #include "main.h"
28 #include "phy_lp.h"
29 #include "phy_common.h"
30 #include "tables_lpphy.h"
31
32
33 static inline u16 channel2freq_lp(u8 channel)
34 {
35 if (channel < 14)
36 return (2407 + 5 * channel);
37 else if (channel == 14)
38 return 2484;
39 else if (channel < 184)
40 return (5000 + 5 * channel);
41 else
42 return (4000 + 5 * channel);
43 }
44
45 static unsigned int b43_lpphy_op_get_default_chan(struct b43_wldev *dev)
46 {
47 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
48 return 1;
49 return 36;
50 }
51
52 static int b43_lpphy_op_allocate(struct b43_wldev *dev)
53 {
54 struct b43_phy_lp *lpphy;
55
56 lpphy = kzalloc(sizeof(*lpphy), GFP_KERNEL);
57 if (!lpphy)
58 return -ENOMEM;
59 dev->phy.lp = lpphy;
60
61 return 0;
62 }
63
64 static void b43_lpphy_op_prepare_structs(struct b43_wldev *dev)
65 {
66 struct b43_phy *phy = &dev->phy;
67 struct b43_phy_lp *lpphy = phy->lp;
68
69 memset(lpphy, 0, sizeof(*lpphy));
70
71 //TODO
72 }
73
74 static void b43_lpphy_op_free(struct b43_wldev *dev)
75 {
76 struct b43_phy_lp *lpphy = dev->phy.lp;
77
78 kfree(lpphy);
79 dev->phy.lp = NULL;
80 }
81
82 static void lpphy_read_band_sprom(struct b43_wldev *dev)
83 {
84 struct b43_phy_lp *lpphy = dev->phy.lp;
85 struct ssb_bus *bus = dev->dev->bus;
86 u16 cckpo, maxpwr;
87 u32 ofdmpo;
88 int i;
89
90 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
91 lpphy->tx_isolation_med_band = bus->sprom.tri2g;
92 lpphy->bx_arch = bus->sprom.bxa2g;
93 lpphy->rx_pwr_offset = bus->sprom.rxpo2g;
94 lpphy->rssi_vf = bus->sprom.rssismf2g;
95 lpphy->rssi_vc = bus->sprom.rssismc2g;
96 lpphy->rssi_gs = bus->sprom.rssisav2g;
97 lpphy->txpa[0] = bus->sprom.pa0b0;
98 lpphy->txpa[1] = bus->sprom.pa0b1;
99 lpphy->txpa[2] = bus->sprom.pa0b2;
100 maxpwr = bus->sprom.maxpwr_bg;
101 lpphy->max_tx_pwr_med_band = maxpwr;
102 cckpo = bus->sprom.cck2gpo;
103 ofdmpo = bus->sprom.ofdm2gpo;
104 if (cckpo) {
105 for (i = 0; i < 4; i++) {
106 lpphy->tx_max_rate[i] =
107 maxpwr - (ofdmpo & 0xF) * 2;
108 ofdmpo >>= 4;
109 }
110 ofdmpo = bus->sprom.ofdm2gpo;
111 for (i = 4; i < 15; i++) {
112 lpphy->tx_max_rate[i] =
113 maxpwr - (ofdmpo & 0xF) * 2;
114 ofdmpo >>= 4;
115 }
116 } else {
117 ofdmpo &= 0xFF;
118 for (i = 0; i < 4; i++)
119 lpphy->tx_max_rate[i] = maxpwr;
120 for (i = 4; i < 15; i++)
121 lpphy->tx_max_rate[i] = maxpwr - ofdmpo;
122 }
123 } else { /* 5GHz */
124 lpphy->tx_isolation_low_band = bus->sprom.tri5gl;
125 lpphy->tx_isolation_med_band = bus->sprom.tri5g;
126 lpphy->tx_isolation_hi_band = bus->sprom.tri5gh;
127 lpphy->bx_arch = bus->sprom.bxa5g;
128 lpphy->rx_pwr_offset = bus->sprom.rxpo5g;
129 lpphy->rssi_vf = bus->sprom.rssismf5g;
130 lpphy->rssi_vc = bus->sprom.rssismc5g;
131 lpphy->rssi_gs = bus->sprom.rssisav5g;
132 lpphy->txpa[0] = bus->sprom.pa1b0;
133 lpphy->txpa[1] = bus->sprom.pa1b1;
134 lpphy->txpa[2] = bus->sprom.pa1b2;
135 lpphy->txpal[0] = bus->sprom.pa1lob0;
136 lpphy->txpal[1] = bus->sprom.pa1lob1;
137 lpphy->txpal[2] = bus->sprom.pa1lob2;
138 lpphy->txpah[0] = bus->sprom.pa1hib0;
139 lpphy->txpah[1] = bus->sprom.pa1hib1;
140 lpphy->txpah[2] = bus->sprom.pa1hib2;
141 maxpwr = bus->sprom.maxpwr_al;
142 ofdmpo = bus->sprom.ofdm5glpo;
143 lpphy->max_tx_pwr_low_band = maxpwr;
144 for (i = 4; i < 12; i++) {
145 lpphy->tx_max_ratel[i] = maxpwr - (ofdmpo & 0xF) * 2;
146 ofdmpo >>= 4;
147 }
148 maxpwr = bus->sprom.maxpwr_a;
149 ofdmpo = bus->sprom.ofdm5gpo;
150 lpphy->max_tx_pwr_med_band = maxpwr;
151 for (i = 4; i < 12; i++) {
152 lpphy->tx_max_rate[i] = maxpwr - (ofdmpo & 0xF) * 2;
153 ofdmpo >>= 4;
154 }
155 maxpwr = bus->sprom.maxpwr_ah;
156 ofdmpo = bus->sprom.ofdm5ghpo;
157 lpphy->max_tx_pwr_hi_band = maxpwr;
158 for (i = 4; i < 12; i++) {
159 lpphy->tx_max_rateh[i] = maxpwr - (ofdmpo & 0xF) * 2;
160 ofdmpo >>= 4;
161 }
162 }
163 }
164
165 static void lpphy_adjust_gain_table(struct b43_wldev *dev, u32 freq)
166 {
167 struct b43_phy_lp *lpphy = dev->phy.lp;
168 u16 temp[3];
169 u16 isolation;
170
171 B43_WARN_ON(dev->phy.rev >= 2);
172
173 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
174 isolation = lpphy->tx_isolation_med_band;
175 else if (freq <= 5320)
176 isolation = lpphy->tx_isolation_low_band;
177 else if (freq <= 5700)
178 isolation = lpphy->tx_isolation_med_band;
179 else
180 isolation = lpphy->tx_isolation_hi_band;
181
182 temp[0] = ((isolation - 26) / 12) << 12;
183 temp[1] = temp[0] + 0x1000;
184 temp[2] = temp[0] + 0x2000;
185
186 b43_lptab_write_bulk(dev, B43_LPTAB16(13, 0), 3, temp);
187 b43_lptab_write_bulk(dev, B43_LPTAB16(12, 0), 3, temp);
188 }
189
190 static void lpphy_table_init(struct b43_wldev *dev)
191 {
192 u32 freq = channel2freq_lp(b43_lpphy_op_get_default_chan(dev));
193
194 if (dev->phy.rev < 2)
195 lpphy_rev0_1_table_init(dev);
196 else
197 lpphy_rev2plus_table_init(dev);
198
199 lpphy_init_tx_gain_table(dev);
200
201 if (dev->phy.rev < 2)
202 lpphy_adjust_gain_table(dev, freq);
203 }
204
205 static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
206 {
207 struct ssb_bus *bus = dev->dev->bus;
208 struct b43_phy_lp *lpphy = dev->phy.lp;
209 u16 tmp, tmp2;
210
211 b43_phy_mask(dev, B43_LPPHY_AFE_DAC_CTL, 0xF7FF);
212 b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0);
213 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
214 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
215 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
216 b43_phy_set(dev, B43_LPPHY_AFE_DAC_CTL, 0x0004);
217 b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0x0078);
218 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
219 b43_phy_write(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x0016);
220 b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_0, 0xFFF8, 0x0004);
221 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5400);
222 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2400);
223 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
224 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0x0006);
225 b43_phy_mask(dev, B43_LPPHY_RX_RADIO_CTL, 0xFFFE);
226 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x0005);
227 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC1F, 0x0180);
228 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x3C00);
229 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFFF0, 0x0005);
230 b43_phy_maskset(dev, B43_LPPHY_GAIN_MISMATCH_LIMIT, 0xFFC0, 0x001A);
231 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0x00B3);
232 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
233 b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB,
234 0xFF00, lpphy->rx_pwr_offset);
235 if ((bus->sprom.boardflags_lo & B43_BFL_FEM) &&
236 ((b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
237 (bus->sprom.boardflags_hi & B43_BFH_PAREF))) {
238 ssb_pmu_set_ldo_voltage(&bus->chipco, LDO_PAREF, 0x28);
239 ssb_pmu_set_ldo_paref(&bus->chipco, true);
240 if (dev->phy.rev == 0) {
241 b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT,
242 0xFFCF, 0x0010);
243 }
244 b43_lptab_write(dev, B43_LPTAB16(11, 7), 60);
245 } else {
246 ssb_pmu_set_ldo_paref(&bus->chipco, false);
247 b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT,
248 0xFFCF, 0x0020);
249 b43_lptab_write(dev, B43_LPTAB16(11, 7), 100);
250 }
251 tmp = lpphy->rssi_vf | lpphy->rssi_vc << 4 | 0xA000;
252 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, tmp);
253 if (bus->sprom.boardflags_hi & B43_BFH_RSSIINV)
254 b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x0AAA);
255 else
256 b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x02AA);
257 b43_lptab_write(dev, B43_LPTAB16(11, 1), 24);
258 b43_phy_maskset(dev, B43_LPPHY_RX_RADIO_CTL,
259 0xFFF9, (lpphy->bx_arch << 1));
260 if (dev->phy.rev == 1 &&
261 (bus->sprom.boardflags_hi & B43_BFH_FEM_BT)) {
262 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
263 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0x3F00, 0x0900);
264 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
265 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
266 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x000A);
267 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0400);
268 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x000A);
269 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0B00);
270 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xFFC0, 0x000A);
271 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xC0FF, 0x0900);
272 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xFFC0, 0x000A);
273 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xC0FF, 0x0B00);
274 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xFFC0, 0x000A);
275 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xC0FF, 0x0900);
276 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A);
277 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00);
278 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ ||
279 (bus->boardinfo.type == 0x048A) || ((dev->phy.rev == 0) &&
280 (bus->sprom.boardflags_lo & B43_BFL_FEM))) {
281 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001);
282 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400);
283 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001);
284 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0500);
285 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
286 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0800);
287 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
288 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0A00);
289 } else if (dev->phy.rev == 1 ||
290 (bus->sprom.boardflags_lo & B43_BFL_FEM)) {
291 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0004);
292 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0800);
293 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0004);
294 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0C00);
295 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
296 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0100);
297 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
298 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0300);
299 } else {
300 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
301 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0900);
302 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
303 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
304 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0006);
305 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0500);
306 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0006);
307 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0700);
308 }
309 if (dev->phy.rev == 1 && (bus->sprom.boardflags_hi & B43_BFH_PAREF)) {
310 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_5, B43_LPPHY_TR_LOOKUP_1);
311 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_6, B43_LPPHY_TR_LOOKUP_2);
312 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_7, B43_LPPHY_TR_LOOKUP_3);
313 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_8, B43_LPPHY_TR_LOOKUP_4);
314 }
315 if ((bus->sprom.boardflags_hi & B43_BFH_FEM_BT) &&
316 (bus->chip_id == 0x5354) &&
317 (bus->chip_package == SSB_CHIPPACK_BCM4712S)) {
318 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0006);
319 b43_phy_write(dev, B43_LPPHY_GPIO_SELECT, 0x0005);
320 b43_phy_write(dev, B43_LPPHY_GPIO_OUTEN, 0xFFFF);
321 //FIXME the Broadcom driver caches & delays this HF write!
322 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_PR45960W);
323 }
324 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
325 b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x8000);
326 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0040);
327 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0xA400);
328 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0x0B00);
329 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x0007);
330 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFF8, 0x0003);
331 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFC7, 0x0020);
332 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
333 } else { /* 5GHz */
334 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0x7FFF);
335 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFBF);
336 }
337 if (dev->phy.rev == 1) {
338 tmp = b43_phy_read(dev, B43_LPPHY_CLIPCTRTHRESH);
339 tmp2 = (tmp & 0x03E0) >> 5;
340 tmp2 |= tmp2 << 5;
341 b43_phy_write(dev, B43_LPPHY_4C3, tmp2);
342 tmp = b43_phy_read(dev, B43_LPPHY_GAINDIRECTMISMATCH);
343 tmp2 = (tmp & 0x1F00) >> 8;
344 tmp2 |= tmp2 << 5;
345 b43_phy_write(dev, B43_LPPHY_4C4, tmp2);
346 tmp = b43_phy_read(dev, B43_LPPHY_VERYLOWGAINDB);
347 tmp2 = tmp & 0x00FF;
348 tmp2 |= tmp << 8;
349 b43_phy_write(dev, B43_LPPHY_4C5, tmp2);
350 }
351 }
352
353 static void lpphy_save_dig_flt_state(struct b43_wldev *dev)
354 {
355 static const u16 addr[] = {
356 B43_PHY_OFDM(0xC1),
357 B43_PHY_OFDM(0xC2),
358 B43_PHY_OFDM(0xC3),
359 B43_PHY_OFDM(0xC4),
360 B43_PHY_OFDM(0xC5),
361 B43_PHY_OFDM(0xC6),
362 B43_PHY_OFDM(0xC7),
363 B43_PHY_OFDM(0xC8),
364 B43_PHY_OFDM(0xCF),
365 };
366
367 static const u16 coefs[] = {
368 0xDE5E, 0xE832, 0xE331, 0x4D26,
369 0x0026, 0x1420, 0x0020, 0xFE08,
370 0x0008,
371 };
372
373 struct b43_phy_lp *lpphy = dev->phy.lp;
374 int i;
375
376 for (i = 0; i < ARRAY_SIZE(addr); i++) {
377 lpphy->dig_flt_state[i] = b43_phy_read(dev, addr[i]);
378 b43_phy_write(dev, addr[i], coefs[i]);
379 }
380 }
381
382 /* lpphy_restore_dig_flt_state is unused but kept as a reference */
383 #if 0
384 static void lpphy_restore_dig_flt_state(struct b43_wldev *dev)
385 {
386 static const u16 addr[] = {
387 B43_PHY_OFDM(0xC1),
388 B43_PHY_OFDM(0xC2),
389 B43_PHY_OFDM(0xC3),
390 B43_PHY_OFDM(0xC4),
391 B43_PHY_OFDM(0xC5),
392 B43_PHY_OFDM(0xC6),
393 B43_PHY_OFDM(0xC7),
394 B43_PHY_OFDM(0xC8),
395 B43_PHY_OFDM(0xCF),
396 };
397
398 struct b43_phy_lp *lpphy = dev->phy.lp;
399 int i;
400
401 for (i = 0; i < ARRAY_SIZE(addr); i++)
402 b43_phy_write(dev, addr[i], lpphy->dig_flt_state[i]);
403 }
404 #endif
405
406 static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
407 {
408 struct ssb_bus *bus = dev->dev->bus;
409 struct b43_phy_lp *lpphy = dev->phy.lp;
410
411 b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50);
412 b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0x8800);
413 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
414 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0);
415 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
416 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
417 b43_phy_write(dev, B43_PHY_OFDM(0xF9), 0);
418 b43_phy_write(dev, B43_LPPHY_TR_LOOKUP_1, 0);
419 b43_phy_set(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x10);
420 b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0xB4);
421 b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xF8FF, 0x200);
422 b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xFF00, 0x7F);
423 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFF0F, 0x40);
424 b43_phy_maskset(dev, B43_LPPHY_PREAMBLECONFIRMTO, 0xFF00, 0x2);
425 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000);
426 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000);
427 b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1);
428 if (bus->boardinfo.rev >= 0x18) {
429 b43_lptab_write(dev, B43_LPTAB32(17, 65), 0xEC);
430 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x14);
431 } else {
432 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x10);
433 }
434 b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0xFF00, 0xF4);
435 b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0x00FF, 0xF100);
436 b43_phy_write(dev, B43_LPPHY_CLIPTHRESH, 0x48);
437 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0xFF00, 0x46);
438 b43_phy_maskset(dev, B43_PHY_OFDM(0xE4), 0xFF00, 0x10);
439 b43_phy_maskset(dev, B43_LPPHY_PWR_THRESH1, 0xFFF0, 0x9);
440 b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF);
441 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5500);
442 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC1F, 0xA0);
443 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300);
444 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00);
445 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
446 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
447 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xA);
448 } else {
449 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x1E00);
450 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xD);
451 }
452 b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFFE0, 0x1F);
453 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
454 b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0xFF00, 0x19);
455 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0x03FF, 0x3C00);
456 b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFC1F, 0x3E0);
457 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
458 b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0x00FF, 0x1900);
459 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
460 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12);
461 b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000);
462
463 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
464 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x14), 0);
465 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x12), 0x40);
466 }
467
468 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
469 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x40);
470 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0xB00);
471 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x6);
472 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0x9D00);
473 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0xFF00, 0xA1);
474 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
475 } else /* 5GHz */
476 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40);
477
478 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0xB3);
479 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
480 b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB, 0xFF00, lpphy->rx_pwr_offset);
481 b43_phy_set(dev, B43_LPPHY_RESET_CTL, 0x44);
482 b43_phy_write(dev, B43_LPPHY_RESET_CTL, 0x80);
483 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, 0xA954);
484 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_1,
485 0x2000 | ((u16)lpphy->rssi_gs << 10) |
486 ((u16)lpphy->rssi_vc << 4) | lpphy->rssi_vf);
487
488 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
489 b43_phy_set(dev, B43_LPPHY_AFE_ADC_CTL_0, 0x1C);
490 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL, 0x00FF, 0x8800);
491 b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_1, 0xFC3C, 0x0400);
492 }
493
494 lpphy_save_dig_flt_state(dev);
495 }
496
497 static void lpphy_baseband_init(struct b43_wldev *dev)
498 {
499 lpphy_table_init(dev);
500 if (dev->phy.rev >= 2)
501 lpphy_baseband_rev2plus_init(dev);
502 else
503 lpphy_baseband_rev0_1_init(dev);
504 }
505
506 struct b2062_freqdata {
507 u16 freq;
508 u8 data[6];
509 };
510
511 /* Initialize the 2062 radio. */
512 static void lpphy_2062_init(struct b43_wldev *dev)
513 {
514 struct b43_phy_lp *lpphy = dev->phy.lp;
515 struct ssb_bus *bus = dev->dev->bus;
516 u32 crystalfreq, tmp, ref;
517 unsigned int i;
518 const struct b2062_freqdata *fd = NULL;
519
520 static const struct b2062_freqdata freqdata_tab[] = {
521 { .freq = 12000, .data[0] = 6, .data[1] = 6, .data[2] = 6,
522 .data[3] = 6, .data[4] = 10, .data[5] = 6, },
523 { .freq = 13000, .data[0] = 4, .data[1] = 4, .data[2] = 4,
524 .data[3] = 4, .data[4] = 11, .data[5] = 7, },
525 { .freq = 14400, .data[0] = 3, .data[1] = 3, .data[2] = 3,
526 .data[3] = 3, .data[4] = 12, .data[5] = 7, },
527 { .freq = 16200, .data[0] = 3, .data[1] = 3, .data[2] = 3,
528 .data[3] = 3, .data[4] = 13, .data[5] = 8, },
529 { .freq = 18000, .data[0] = 2, .data[1] = 2, .data[2] = 2,
530 .data[3] = 2, .data[4] = 14, .data[5] = 8, },
531 { .freq = 19200, .data[0] = 1, .data[1] = 1, .data[2] = 1,
532 .data[3] = 1, .data[4] = 14, .data[5] = 9, },
533 };
534
535 b2062_upload_init_table(dev);
536
537 b43_radio_write(dev, B2062_N_TX_CTL3, 0);
538 b43_radio_write(dev, B2062_N_TX_CTL4, 0);
539 b43_radio_write(dev, B2062_N_TX_CTL5, 0);
540 b43_radio_write(dev, B2062_N_TX_CTL6, 0);
541 b43_radio_write(dev, B2062_N_PDN_CTL0, 0x40);
542 b43_radio_write(dev, B2062_N_PDN_CTL0, 0);
543 b43_radio_write(dev, B2062_N_CALIB_TS, 0x10);
544 b43_radio_write(dev, B2062_N_CALIB_TS, 0);
545 if (dev->phy.rev > 0) {
546 b43_radio_write(dev, B2062_S_BG_CTL1,
547 (b43_radio_read(dev, B2062_N_COMM2) >> 1) | 0x80);
548 }
549 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
550 b43_radio_set(dev, B2062_N_TSSI_CTL0, 0x1);
551 else
552 b43_radio_mask(dev, B2062_N_TSSI_CTL0, ~0x1);
553
554 /* Get the crystal freq, in Hz. */
555 crystalfreq = bus->chipco.pmu.crystalfreq * 1000;
556
557 B43_WARN_ON(!(bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU));
558 B43_WARN_ON(crystalfreq == 0);
559
560 if (crystalfreq <= 30000000) {
561 lpphy->pdiv = 1;
562 b43_radio_mask(dev, B2062_S_RFPLL_CTL1, 0xFFFB);
563 } else {
564 lpphy->pdiv = 2;
565 b43_radio_set(dev, B2062_S_RFPLL_CTL1, 0x4);
566 }
567
568 tmp = (((800000000 * lpphy->pdiv + crystalfreq) /
569 (2 * crystalfreq)) - 8) & 0xFF;
570 b43_radio_write(dev, B2062_S_RFPLL_CTL7, tmp);
571
572 tmp = (((100 * crystalfreq + 16000000 * lpphy->pdiv) /
573 (32000000 * lpphy->pdiv)) - 1) & 0xFF;
574 b43_radio_write(dev, B2062_S_RFPLL_CTL18, tmp);
575
576 tmp = (((2 * crystalfreq + 1000000 * lpphy->pdiv) /
577 (2000000 * lpphy->pdiv)) - 1) & 0xFF;
578 b43_radio_write(dev, B2062_S_RFPLL_CTL19, tmp);
579
580 ref = (1000 * lpphy->pdiv + 2 * crystalfreq) / (2000 * lpphy->pdiv);
581 ref &= 0xFFFF;
582 for (i = 0; i < ARRAY_SIZE(freqdata_tab); i++) {
583 if (ref < freqdata_tab[i].freq) {
584 fd = &freqdata_tab[i];
585 break;
586 }
587 }
588 if (!fd)
589 fd = &freqdata_tab[ARRAY_SIZE(freqdata_tab) - 1];
590 b43dbg(dev->wl, "b2062: Using crystal tab entry %u kHz.\n",
591 fd->freq); /* FIXME: Keep this printk until the code is fully debugged. */
592
593 b43_radio_write(dev, B2062_S_RFPLL_CTL8,
594 ((u16)(fd->data[1]) << 4) | fd->data[0]);
595 b43_radio_write(dev, B2062_S_RFPLL_CTL9,
596 ((u16)(fd->data[3]) << 4) | fd->data[2]);
597 b43_radio_write(dev, B2062_S_RFPLL_CTL10, fd->data[4]);
598 b43_radio_write(dev, B2062_S_RFPLL_CTL11, fd->data[5]);
599 }
600
601 /* Initialize the 2063 radio. */
602 static void lpphy_2063_init(struct b43_wldev *dev)
603 {
604 b2063_upload_init_table(dev);
605 b43_radio_write(dev, B2063_LOGEN_SP5, 0);
606 b43_radio_set(dev, B2063_COMM8, 0x38);
607 b43_radio_write(dev, B2063_REG_SP1, 0x56);
608 b43_radio_mask(dev, B2063_RX_BB_CTL2, ~0x2);
609 b43_radio_write(dev, B2063_PA_SP7, 0);
610 b43_radio_write(dev, B2063_TX_RF_SP6, 0x20);
611 b43_radio_write(dev, B2063_TX_RF_SP9, 0x40);
612 if (dev->phy.rev == 2) {
613 b43_radio_write(dev, B2063_PA_SP3, 0xa0);
614 b43_radio_write(dev, B2063_PA_SP4, 0xa0);
615 b43_radio_write(dev, B2063_PA_SP2, 0x18);
616 } else {
617 b43_radio_write(dev, B2063_PA_SP3, 0x20);
618 b43_radio_write(dev, B2063_PA_SP2, 0x20);
619 }
620 }
621
622 struct lpphy_stx_table_entry {
623 u16 phy_offset;
624 u16 phy_shift;
625 u16 rf_addr;
626 u16 rf_shift;
627 u16 mask;
628 };
629
630 static const struct lpphy_stx_table_entry lpphy_stx_table[] = {
631 { .phy_offset = 2, .phy_shift = 6, .rf_addr = 0x3d, .rf_shift = 3, .mask = 0x01, },
632 { .phy_offset = 1, .phy_shift = 12, .rf_addr = 0x4c, .rf_shift = 1, .mask = 0x01, },
633 { .phy_offset = 1, .phy_shift = 8, .rf_addr = 0x50, .rf_shift = 0, .mask = 0x7f, },
634 { .phy_offset = 0, .phy_shift = 8, .rf_addr = 0x44, .rf_shift = 0, .mask = 0xff, },
635 { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4a, .rf_shift = 0, .mask = 0xff, },
636 { .phy_offset = 0, .phy_shift = 4, .rf_addr = 0x4d, .rf_shift = 0, .mask = 0xff, },
637 { .phy_offset = 1, .phy_shift = 4, .rf_addr = 0x4e, .rf_shift = 0, .mask = 0xff, },
638 { .phy_offset = 0, .phy_shift = 12, .rf_addr = 0x4f, .rf_shift = 0, .mask = 0x0f, },
639 { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4f, .rf_shift = 4, .mask = 0x0f, },
640 { .phy_offset = 3, .phy_shift = 0, .rf_addr = 0x49, .rf_shift = 0, .mask = 0x0f, },
641 { .phy_offset = 4, .phy_shift = 3, .rf_addr = 0x46, .rf_shift = 4, .mask = 0x07, },
642 { .phy_offset = 3, .phy_shift = 15, .rf_addr = 0x46, .rf_shift = 0, .mask = 0x01, },
643 { .phy_offset = 4, .phy_shift = 0, .rf_addr = 0x46, .rf_shift = 1, .mask = 0x07, },
644 { .phy_offset = 3, .phy_shift = 8, .rf_addr = 0x48, .rf_shift = 4, .mask = 0x07, },
645 { .phy_offset = 3, .phy_shift = 11, .rf_addr = 0x48, .rf_shift = 0, .mask = 0x0f, },
646 { .phy_offset = 3, .phy_shift = 4, .rf_addr = 0x49, .rf_shift = 4, .mask = 0x0f, },
647 { .phy_offset = 2, .phy_shift = 15, .rf_addr = 0x45, .rf_shift = 0, .mask = 0x01, },
648 { .phy_offset = 5, .phy_shift = 13, .rf_addr = 0x52, .rf_shift = 4, .mask = 0x07, },
649 { .phy_offset = 6, .phy_shift = 0, .rf_addr = 0x52, .rf_shift = 7, .mask = 0x01, },
650 { .phy_offset = 5, .phy_shift = 3, .rf_addr = 0x41, .rf_shift = 5, .mask = 0x07, },
651 { .phy_offset = 5, .phy_shift = 6, .rf_addr = 0x41, .rf_shift = 0, .mask = 0x0f, },
652 { .phy_offset = 5, .phy_shift = 10, .rf_addr = 0x42, .rf_shift = 5, .mask = 0x07, },
653 { .phy_offset = 4, .phy_shift = 15, .rf_addr = 0x42, .rf_shift = 0, .mask = 0x01, },
654 { .phy_offset = 5, .phy_shift = 0, .rf_addr = 0x42, .rf_shift = 1, .mask = 0x07, },
655 { .phy_offset = 4, .phy_shift = 11, .rf_addr = 0x43, .rf_shift = 4, .mask = 0x0f, },
656 { .phy_offset = 4, .phy_shift = 7, .rf_addr = 0x43, .rf_shift = 0, .mask = 0x0f, },
657 { .phy_offset = 4, .phy_shift = 6, .rf_addr = 0x45, .rf_shift = 1, .mask = 0x01, },
658 { .phy_offset = 2, .phy_shift = 7, .rf_addr = 0x40, .rf_shift = 4, .mask = 0x0f, },
659 { .phy_offset = 2, .phy_shift = 11, .rf_addr = 0x40, .rf_shift = 0, .mask = 0x0f, },
660 };
661
662 static void lpphy_sync_stx(struct b43_wldev *dev)
663 {
664 const struct lpphy_stx_table_entry *e;
665 unsigned int i;
666 u16 tmp;
667
668 for (i = 0; i < ARRAY_SIZE(lpphy_stx_table); i++) {
669 e = &lpphy_stx_table[i];
670 tmp = b43_radio_read(dev, e->rf_addr);
671 tmp >>= e->rf_shift;
672 tmp <<= e->phy_shift;
673 b43_phy_maskset(dev, B43_PHY_OFDM(0xF2 + e->phy_offset),
674 ~(e->mask << e->phy_shift), tmp);
675 }
676 }
677
678 static void lpphy_radio_init(struct b43_wldev *dev)
679 {
680 /* The radio is attached through the 4wire bus. */
681 b43_phy_set(dev, B43_LPPHY_FOURWIRE_CTL, 0x2);
682 udelay(1);
683 b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD);
684 udelay(1);
685
686 if (dev->phy.radio_ver == 0x2062) {
687 lpphy_2062_init(dev);
688 } else {
689 lpphy_2063_init(dev);
690 lpphy_sync_stx(dev);
691 b43_phy_write(dev, B43_PHY_OFDM(0xF0), 0x5F80);
692 b43_phy_write(dev, B43_PHY_OFDM(0xF1), 0);
693 if (dev->dev->bus->chip_id == 0x4325) {
694 // TODO SSB PMU recalibration
695 }
696 }
697 }
698
699 struct lpphy_iq_est { u32 iq_prod, i_pwr, q_pwr; };
700
701 static void lpphy_set_rc_cap(struct b43_wldev *dev)
702 {
703 struct b43_phy_lp *lpphy = dev->phy.lp;
704
705 u8 rc_cap = (lpphy->rc_cap & 0x1F) >> 1;
706
707 if (dev->phy.rev == 1) //FIXME check channel 14!
708 rc_cap = min_t(u8, rc_cap + 5, 15);
709
710 b43_radio_write(dev, B2062_N_RXBB_CALIB2,
711 max_t(u8, lpphy->rc_cap - 4, 0x80));
712 b43_radio_write(dev, B2062_N_TX_CTL_A, rc_cap | 0x80);
713 b43_radio_write(dev, B2062_S_RXG_CNT16,
714 ((lpphy->rc_cap & 0x1F) >> 2) | 0x80);
715 }
716
717 static u8 lpphy_get_bb_mult(struct b43_wldev *dev)
718 {
719 return (b43_lptab_read(dev, B43_LPTAB16(0, 87)) & 0xFF00) >> 8;
720 }
721
722 static void lpphy_set_bb_mult(struct b43_wldev *dev, u8 bb_mult)
723 {
724 b43_lptab_write(dev, B43_LPTAB16(0, 87), (u16)bb_mult << 8);
725 }
726
727 static void lpphy_set_deaf(struct b43_wldev *dev, bool user)
728 {
729 struct b43_phy_lp *lpphy = dev->phy.lp;
730
731 if (user)
732 lpphy->crs_usr_disable = 1;
733 else
734 lpphy->crs_sys_disable = 1;
735 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x80);
736 }
737
738 static void lpphy_clear_deaf(struct b43_wldev *dev, bool user)
739 {
740 struct b43_phy_lp *lpphy = dev->phy.lp;
741
742 if (user)
743 lpphy->crs_usr_disable = 0;
744 else
745 lpphy->crs_sys_disable = 0;
746
747 if (!lpphy->crs_usr_disable && !lpphy->crs_sys_disable) {
748 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
749 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL,
750 0xFF1F, 0x60);
751 else
752 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL,
753 0xFF1F, 0x20);
754 }
755 }
756
757 static void lpphy_disable_crs(struct b43_wldev *dev, bool user)
758 {
759 lpphy_set_deaf(dev, user);
760 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x1);
761 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
762 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFB);
763 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x4);
764 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFF7);
765 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
766 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x10);
767 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
768 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFDF);
769 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x20);
770 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFBF);
771 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
772 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x7);
773 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x38);
774 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F);
775 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x100);
776 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFDFF);
777 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL0, 0);
778 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL1, 1);
779 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL2, 0x20);
780 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFBFF);
781 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xF7FF);
782 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL, 0);
783 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, 0x45AF);
784 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0x3FF);
785 }
786
787 static void lpphy_restore_crs(struct b43_wldev *dev, bool user)
788 {
789 lpphy_clear_deaf(dev, user);
790 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFF80);
791 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFC00);
792 }
793
794 struct lpphy_tx_gains { u16 gm, pga, pad, dac; };
795
796 static struct lpphy_tx_gains lpphy_get_tx_gains(struct b43_wldev *dev)
797 {
798 struct lpphy_tx_gains gains;
799 u16 tmp;
800
801 gains.dac = (b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0x380) >> 7;
802 if (dev->phy.rev < 2) {
803 tmp = b43_phy_read(dev,
804 B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL) & 0x7FF;
805 gains.gm = tmp & 0x0007;
806 gains.pga = (tmp & 0x0078) >> 3;
807 gains.pad = (tmp & 0x780) >> 7;
808 } else {
809 tmp = b43_phy_read(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL);
810 gains.pad = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0xFF;
811 gains.gm = tmp & 0xFF;
812 gains.pga = (tmp >> 8) & 0xFF;
813 }
814
815 return gains;
816 }
817
818 static void lpphy_set_dac_gain(struct b43_wldev *dev, u16 dac)
819 {
820 u16 ctl = b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0xC7F;
821 ctl |= dac << 7;
822 b43_phy_maskset(dev, B43_LPPHY_AFE_DAC_CTL, 0xF000, ctl);
823 }
824
825 static void lpphy_set_tx_gains(struct b43_wldev *dev,
826 struct lpphy_tx_gains gains)
827 {
828 u16 rf_gain, pa_gain;
829
830 if (dev->phy.rev < 2) {
831 rf_gain = (gains.pad << 7) | (gains.pga << 3) | gains.gm;
832 b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
833 0xF800, rf_gain);
834 } else {
835 pa_gain = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0x1FC0;
836 pa_gain <<= 2;
837 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
838 (gains.pga << 8) | gains.gm);
839 b43_phy_maskset(dev, B43_PHY_OFDM(0xFB),
840 0x8000, gains.pad | pa_gain);
841 b43_phy_write(dev, B43_PHY_OFDM(0xFC),
842 (gains.pga << 8) | gains.gm);
843 b43_phy_maskset(dev, B43_PHY_OFDM(0xFD),
844 0x8000, gains.pad | pa_gain);
845 }
846 lpphy_set_dac_gain(dev, gains.dac);
847 if (dev->phy.rev < 2) {
848 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF, 1 << 8);
849 } else {
850 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F, 1 << 7);
851 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF, 1 << 14);
852 }
853 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFBF, 1 << 6);
854 }
855
856 static void lpphy_rev0_1_set_rx_gain(struct b43_wldev *dev, u32 gain)
857 {
858 u16 trsw = gain & 0x1;
859 u16 lna = (gain & 0xFFFC) | ((gain & 0xC) >> 2);
860 u16 ext_lna = (gain & 2) >> 1;
861
862 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw);
863 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
864 0xFBFF, ext_lna << 10);
865 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
866 0xF7FF, ext_lna << 11);
867 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, lna);
868 }
869
870 static void lpphy_rev2plus_set_rx_gain(struct b43_wldev *dev, u32 gain)
871 {
872 u16 low_gain = gain & 0xFFFF;
873 u16 high_gain = (gain >> 16) & 0xF;
874 u16 ext_lna = (gain >> 21) & 0x1;
875 u16 trsw = ~(gain >> 20) & 0x1;
876 u16 tmp;
877
878 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw);
879 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
880 0xFDFF, ext_lna << 9);
881 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
882 0xFBFF, ext_lna << 10);
883 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, low_gain);
884 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF0, high_gain);
885 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
886 tmp = (gain >> 2) & 0x3;
887 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
888 0xE7FF, tmp<<11);
889 b43_phy_maskset(dev, B43_PHY_OFDM(0xE6), 0xFFE7, tmp << 3);
890 }
891 }
892
893 /* lpphy_disable_rx_gain_override is unused but kept as a reference */
894 #if 0
895 static void lpphy_disable_rx_gain_override(struct b43_wldev *dev)
896 {
897 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE);
898 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF);
899 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF);
900 if (dev->phy.rev >= 2) {
901 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
902 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
903 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF);
904 b43_phy_mask(dev, B43_PHY_OFDM(0xE5), 0xFFF7);
905 }
906 } else {
907 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF);
908 }
909 }
910 #endif
911
912 static void lpphy_enable_rx_gain_override(struct b43_wldev *dev)
913 {
914 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1);
915 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
916 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
917 if (dev->phy.rev >= 2) {
918 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
919 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
920 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x400);
921 b43_phy_set(dev, B43_PHY_OFDM(0xE5), 0x8);
922 }
923 } else {
924 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x200);
925 }
926 }
927
928 static void lpphy_set_rx_gain(struct b43_wldev *dev, u32 gain)
929 {
930 if (dev->phy.rev < 2)
931 lpphy_rev0_1_set_rx_gain(dev, gain);
932 else
933 lpphy_rev2plus_set_rx_gain(dev, gain);
934 lpphy_enable_rx_gain_override(dev);
935 }
936
937 static void lpphy_set_rx_gain_by_index(struct b43_wldev *dev, u16 idx)
938 {
939 u32 gain = b43_lptab_read(dev, B43_LPTAB16(12, idx));
940 lpphy_set_rx_gain(dev, gain);
941 }
942
943 static void lpphy_stop_ddfs(struct b43_wldev *dev)
944 {
945 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFD);
946 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xFFDF);
947 }
948
949 static void lpphy_run_ddfs(struct b43_wldev *dev, int i_on, int q_on,
950 int incr1, int incr2, int scale_idx)
951 {
952 lpphy_stop_ddfs(dev);
953 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0xFF80);
954 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0x80FF);
955 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0xFF80, incr1);
956 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0x80FF, incr2 << 8);
957 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF7, i_on << 3);
958 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFEF, q_on << 4);
959 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFF9F, scale_idx << 5);
960 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFB);
961 b43_phy_set(dev, B43_LPPHY_AFE_DDFS, 0x2);
962 b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x20);
963 }
964
965 static bool lpphy_rx_iq_est(struct b43_wldev *dev, u16 samples, u8 time,
966 struct lpphy_iq_est *iq_est)
967 {
968 int i;
969
970 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFF7);
971 b43_phy_write(dev, B43_LPPHY_IQ_NUM_SMPLS_ADDR, samples);
972 b43_phy_maskset(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFF00, time);
973 b43_phy_mask(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFEFF);
974 b43_phy_set(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0x200);
975
976 for (i = 0; i < 500; i++) {
977 if (!(b43_phy_read(dev,
978 B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200))
979 break;
980 msleep(1);
981 }
982
983 if ((b43_phy_read(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200)) {
984 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8);
985 return false;
986 }
987
988 iq_est->iq_prod = b43_phy_read(dev, B43_LPPHY_IQ_ACC_HI_ADDR);
989 iq_est->iq_prod <<= 16;
990 iq_est->iq_prod |= b43_phy_read(dev, B43_LPPHY_IQ_ACC_LO_ADDR);
991
992 iq_est->i_pwr = b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_HI_ADDR);
993 iq_est->i_pwr <<= 16;
994 iq_est->i_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_LO_ADDR);
995
996 iq_est->q_pwr = b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_HI_ADDR);
997 iq_est->q_pwr <<= 16;
998 iq_est->q_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_LO_ADDR);
999
1000 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8);
1001 return true;
1002 }
1003
1004 static int lpphy_loopback(struct b43_wldev *dev)
1005 {
1006 struct lpphy_iq_est iq_est;
1007 int i, index = -1;
1008 u32 tmp;
1009
1010 memset(&iq_est, 0, sizeof(iq_est));
1011
1012 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x3);
1013 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
1014 b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 1);
1015 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE);
1016 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800);
1017 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x800);
1018 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
1019 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x8);
1020 b43_radio_write(dev, B2062_N_TX_CTL_A, 0x80);
1021 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x80);
1022 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x80);
1023 for (i = 0; i < 32; i++) {
1024 lpphy_set_rx_gain_by_index(dev, i);
1025 lpphy_run_ddfs(dev, 1, 1, 5, 5, 0);
1026 if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est)))
1027 continue;
1028 tmp = (iq_est.i_pwr + iq_est.q_pwr) / 1000;
1029 if ((tmp > 4000) && (tmp < 10000)) {
1030 index = i;
1031 break;
1032 }
1033 }
1034 lpphy_stop_ddfs(dev);
1035 return index;
1036 }
1037
1038 /* Fixed-point division algorithm using only integer math. */
1039 static u32 lpphy_qdiv_roundup(u32 dividend, u32 divisor, u8 precision)
1040 {
1041 u32 quotient, remainder;
1042
1043 if (divisor == 0)
1044 return 0;
1045
1046 quotient = dividend / divisor;
1047 remainder = dividend % divisor;
1048
1049 while (precision > 0) {
1050 quotient <<= 1;
1051 if (remainder << 1 >= divisor) {
1052 quotient++;
1053 remainder = (remainder << 1) - divisor;
1054 }
1055 precision--;
1056 }
1057
1058 if (remainder << 1 >= divisor)
1059 quotient++;
1060
1061 return quotient;
1062 }
1063
1064 /* Read the TX power control mode from hardware. */
1065 static void lpphy_read_tx_pctl_mode_from_hardware(struct b43_wldev *dev)
1066 {
1067 struct b43_phy_lp *lpphy = dev->phy.lp;
1068 u16 ctl;
1069
1070 ctl = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_CMD);
1071 switch (ctl & B43_LPPHY_TX_PWR_CTL_CMD_MODE) {
1072 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF:
1073 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_OFF;
1074 break;
1075 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW:
1076 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_SW;
1077 break;
1078 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW:
1079 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_HW;
1080 break;
1081 default:
1082 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_UNKNOWN;
1083 B43_WARN_ON(1);
1084 break;
1085 }
1086 }
1087
1088 /* Set the TX power control mode in hardware. */
1089 static void lpphy_write_tx_pctl_mode_to_hardware(struct b43_wldev *dev)
1090 {
1091 struct b43_phy_lp *lpphy = dev->phy.lp;
1092 u16 ctl;
1093
1094 switch (lpphy->txpctl_mode) {
1095 case B43_LPPHY_TXPCTL_OFF:
1096 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF;
1097 break;
1098 case B43_LPPHY_TXPCTL_HW:
1099 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW;
1100 break;
1101 case B43_LPPHY_TXPCTL_SW:
1102 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW;
1103 break;
1104 default:
1105 ctl = 0;
1106 B43_WARN_ON(1);
1107 }
1108 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1109 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE, ctl);
1110 }
1111
1112 static void lpphy_set_tx_power_control(struct b43_wldev *dev,
1113 enum b43_lpphy_txpctl_mode mode)
1114 {
1115 struct b43_phy_lp *lpphy = dev->phy.lp;
1116 enum b43_lpphy_txpctl_mode oldmode;
1117
1118 lpphy_read_tx_pctl_mode_from_hardware(dev);
1119 oldmode = lpphy->txpctl_mode;
1120 if (oldmode == mode)
1121 return;
1122 lpphy->txpctl_mode = mode;
1123
1124 if (oldmode == B43_LPPHY_TXPCTL_HW) {
1125 //TODO Update TX Power NPT
1126 //TODO Clear all TX Power offsets
1127 } else {
1128 if (mode == B43_LPPHY_TXPCTL_HW) {
1129 //TODO Recalculate target TX power
1130 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1131 0xFF80, lpphy->tssi_idx);
1132 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM,
1133 0x8FFF, ((u16)lpphy->tssi_npt << 16));
1134 //TODO Set "TSSI Transmit Count" variable to total transmitted frame count
1135 //TODO Disable TX gain override
1136 lpphy->tx_pwr_idx_over = -1;
1137 }
1138 }
1139 if (dev->phy.rev >= 2) {
1140 if (mode == B43_LPPHY_TXPCTL_HW)
1141 b43_phy_set(dev, B43_PHY_OFDM(0xD0), 0x2);
1142 else
1143 b43_phy_mask(dev, B43_PHY_OFDM(0xD0), 0xFFFD);
1144 }
1145 lpphy_write_tx_pctl_mode_to_hardware(dev);
1146 }
1147
1148 static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
1149 unsigned int new_channel);
1150
1151 static void lpphy_rev0_1_rc_calib(struct b43_wldev *dev)
1152 {
1153 struct b43_phy_lp *lpphy = dev->phy.lp;
1154 struct lpphy_iq_est iq_est;
1155 struct lpphy_tx_gains tx_gains;
1156 static const u32 ideal_pwr_table[21] = {
1157 0x10000, 0x10557, 0x10e2d, 0x113e0, 0x10f22, 0x0ff64,
1158 0x0eda2, 0x0e5d4, 0x0efd1, 0x0fbe8, 0x0b7b8, 0x04b35,
1159 0x01a5e, 0x00a0b, 0x00444, 0x001fd, 0x000ff, 0x00088,
1160 0x0004c, 0x0002c, 0x0001a,
1161 };
1162 bool old_txg_ovr;
1163 u8 old_bbmult;
1164 u16 old_rf_ovr, old_rf_ovrval, old_afe_ovr, old_afe_ovrval,
1165 old_rf2_ovr, old_rf2_ovrval, old_phy_ctl;
1166 enum b43_lpphy_txpctl_mode old_txpctl;
1167 u32 normal_pwr, ideal_pwr, mean_sq_pwr, tmp = 0, mean_sq_pwr_min = 0;
1168 int loopback, i, j, inner_sum, err;
1169
1170 memset(&iq_est, 0, sizeof(iq_est));
1171
1172 err = b43_lpphy_op_switch_channel(dev, 7);
1173 if (err) {
1174 b43dbg(dev->wl,
1175 "RC calib: Failed to switch to channel 7, error = %d\n",
1176 err);
1177 }
1178 old_txg_ovr = !!(b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) & 0x40);
1179 old_bbmult = lpphy_get_bb_mult(dev);
1180 if (old_txg_ovr)
1181 tx_gains = lpphy_get_tx_gains(dev);
1182 old_rf_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_0);
1183 old_rf_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_VAL_0);
1184 old_afe_ovr = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR);
1185 old_afe_ovrval = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVRVAL);
1186 old_rf2_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2);
1187 old_rf2_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2_VAL);
1188 old_phy_ctl = b43_phy_read(dev, B43_LPPHY_LP_PHY_CTL);
1189 lpphy_read_tx_pctl_mode_from_hardware(dev);
1190 old_txpctl = lpphy->txpctl_mode;
1191
1192 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
1193 lpphy_disable_crs(dev, true);
1194 loopback = lpphy_loopback(dev);
1195 if (loopback == -1)
1196 goto finish;
1197 lpphy_set_rx_gain_by_index(dev, loopback);
1198 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFFBF, 0x40);
1199 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFF8, 0x1);
1200 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFC7, 0x8);
1201 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F, 0xC0);
1202 for (i = 128; i <= 159; i++) {
1203 b43_radio_write(dev, B2062_N_RXBB_CALIB2, i);
1204 inner_sum = 0;
1205 for (j = 5; j <= 25; j++) {
1206 lpphy_run_ddfs(dev, 1, 1, j, j, 0);
1207 if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est)))
1208 goto finish;
1209 mean_sq_pwr = iq_est.i_pwr + iq_est.q_pwr;
1210 if (j == 5)
1211 tmp = mean_sq_pwr;
1212 ideal_pwr = ((ideal_pwr_table[j-5] >> 3) + 1) >> 1;
1213 normal_pwr = lpphy_qdiv_roundup(mean_sq_pwr, tmp, 12);
1214 mean_sq_pwr = ideal_pwr - normal_pwr;
1215 mean_sq_pwr *= mean_sq_pwr;
1216 inner_sum += mean_sq_pwr;
1217 if ((i == 128) || (inner_sum < mean_sq_pwr_min)) {
1218 lpphy->rc_cap = i;
1219 mean_sq_pwr_min = inner_sum;
1220 }
1221 }
1222 }
1223 lpphy_stop_ddfs(dev);
1224
1225 finish:
1226 lpphy_restore_crs(dev, true);
1227 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, old_rf_ovrval);
1228 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, old_rf_ovr);
1229 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, old_afe_ovrval);
1230 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, old_afe_ovr);
1231 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, old_rf2_ovrval);
1232 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, old_rf2_ovr);
1233 b43_phy_write(dev, B43_LPPHY_LP_PHY_CTL, old_phy_ctl);
1234
1235 lpphy_set_bb_mult(dev, old_bbmult);
1236 if (old_txg_ovr) {
1237 /*
1238 * SPEC FIXME: The specs say "get_tx_gains" here, which is
1239 * illogical. According to lwfinger, vendor driver v4.150.10.5
1240 * has a Set here, while v4.174.64.19 has a Get - regression in
1241 * the vendor driver? This should be tested this once the code
1242 * is testable.
1243 */
1244 lpphy_set_tx_gains(dev, tx_gains);
1245 }
1246 lpphy_set_tx_power_control(dev, old_txpctl);
1247 if (lpphy->rc_cap)
1248 lpphy_set_rc_cap(dev);
1249 }
1250
1251 static void lpphy_rev2plus_rc_calib(struct b43_wldev *dev)
1252 {
1253 struct ssb_bus *bus = dev->dev->bus;
1254 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
1255 u8 tmp = b43_radio_read(dev, B2063_RX_BB_SP8) & 0xFF;
1256 int i;
1257
1258 b43_radio_write(dev, B2063_RX_BB_SP8, 0x0);
1259 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1260 b43_radio_mask(dev, B2063_PLL_SP1, 0xF7);
1261 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C);
1262 b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x15);
1263 b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x70);
1264 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x52);
1265 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1);
1266 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7D);
1267
1268 for (i = 0; i < 10000; i++) {
1269 if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)
1270 break;
1271 msleep(1);
1272 }
1273
1274 if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2))
1275 b43_radio_write(dev, B2063_RX_BB_SP8, tmp);
1276
1277 tmp = b43_radio_read(dev, B2063_TX_BB_SP3) & 0xFF;
1278
1279 b43_radio_write(dev, B2063_TX_BB_SP3, 0x0);
1280 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1281 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C);
1282 b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x55);
1283 b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x76);
1284
1285 if (crystal_freq == 24000000) {
1286 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0xFC);
1287 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x0);
1288 } else {
1289 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x13);
1290 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1);
1291 }
1292
1293 b43_radio_write(dev, B2063_PA_SP7, 0x7D);
1294
1295 for (i = 0; i < 10000; i++) {
1296 if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)
1297 break;
1298 msleep(1);
1299 }
1300
1301 if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2))
1302 b43_radio_write(dev, B2063_TX_BB_SP3, tmp);
1303
1304 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1305 }
1306
1307 static void lpphy_calibrate_rc(struct b43_wldev *dev)
1308 {
1309 struct b43_phy_lp *lpphy = dev->phy.lp;
1310
1311 if (dev->phy.rev >= 2) {
1312 lpphy_rev2plus_rc_calib(dev);
1313 } else if (!lpphy->rc_cap) {
1314 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1315 lpphy_rev0_1_rc_calib(dev);
1316 } else {
1317 lpphy_set_rc_cap(dev);
1318 }
1319 }
1320
1321 static void lpphy_set_tx_power_by_index(struct b43_wldev *dev, u8 index)
1322 {
1323 struct b43_phy_lp *lpphy = dev->phy.lp;
1324
1325 lpphy->tx_pwr_idx_over = index;
1326 if (lpphy->txpctl_mode != B43_LPPHY_TXPCTL_OFF)
1327 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_SW);
1328
1329 //TODO
1330 }
1331
1332 static void lpphy_btcoex_override(struct b43_wldev *dev)
1333 {
1334 b43_write16(dev, B43_MMIO_BTCOEX_CTL, 0x3);
1335 b43_write16(dev, B43_MMIO_BTCOEX_TXCTL, 0xFF);
1336 }
1337
1338 static void lpphy_pr41573_workaround(struct b43_wldev *dev)
1339 {
1340 struct b43_phy_lp *lpphy = dev->phy.lp;
1341 u32 *saved_tab;
1342 const unsigned int saved_tab_size = 256;
1343 enum b43_lpphy_txpctl_mode txpctl_mode;
1344 s8 tx_pwr_idx_over;
1345 u16 tssi_npt, tssi_idx;
1346
1347 saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL);
1348 if (!saved_tab) {
1349 b43err(dev->wl, "PR41573 failed. Out of memory!\n");
1350 return;
1351 }
1352
1353 lpphy_read_tx_pctl_mode_from_hardware(dev);
1354 txpctl_mode = lpphy->txpctl_mode;
1355 tx_pwr_idx_over = lpphy->tx_pwr_idx_over;
1356 tssi_npt = lpphy->tssi_npt;
1357 tssi_idx = lpphy->tssi_idx;
1358
1359 if (dev->phy.rev < 2) {
1360 b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140),
1361 saved_tab_size, saved_tab);
1362 } else {
1363 b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140),
1364 saved_tab_size, saved_tab);
1365 }
1366 //TODO
1367
1368 kfree(saved_tab);
1369 }
1370
1371 static void lpphy_calibration(struct b43_wldev *dev)
1372 {
1373 struct b43_phy_lp *lpphy = dev->phy.lp;
1374 enum b43_lpphy_txpctl_mode saved_pctl_mode;
1375
1376 b43_mac_suspend(dev);
1377
1378 lpphy_btcoex_override(dev);
1379 lpphy_read_tx_pctl_mode_from_hardware(dev);
1380 saved_pctl_mode = lpphy->txpctl_mode;
1381 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
1382 //TODO Perform transmit power table I/Q LO calibration
1383 if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF))
1384 lpphy_pr41573_workaround(dev);
1385 //TODO If a full calibration has not been performed on this channel yet, perform PAPD TX-power calibration
1386 lpphy_set_tx_power_control(dev, saved_pctl_mode);
1387 //TODO Perform I/Q calibration with a single control value set
1388
1389 b43_mac_enable(dev);
1390 }
1391
1392 static void lpphy_set_tssi_mux(struct b43_wldev *dev, enum tssi_mux_mode mode)
1393 {
1394 if (mode != TSSI_MUX_EXT) {
1395 b43_radio_set(dev, B2063_PA_SP1, 0x2);
1396 b43_phy_set(dev, B43_PHY_OFDM(0xF3), 0x1000);
1397 b43_radio_write(dev, B2063_PA_CTL10, 0x51);
1398 if (mode == TSSI_MUX_POSTPA) {
1399 b43_radio_mask(dev, B2063_PA_SP1, 0xFFFE);
1400 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFC7);
1401 } else {
1402 b43_radio_maskset(dev, B2063_PA_SP1, 0xFFFE, 0x1);
1403 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL_OVRVAL,
1404 0xFFC7, 0x20);
1405 }
1406 } else {
1407 B43_WARN_ON(1);
1408 }
1409 }
1410
1411 static void lpphy_tx_pctl_init_hw(struct b43_wldev *dev)
1412 {
1413 u16 tmp;
1414 int i;
1415
1416 //SPEC TODO Call LP PHY Clear TX Power offsets
1417 for (i = 0; i < 64; i++) {
1418 if (dev->phy.rev >= 2)
1419 b43_lptab_write(dev, B43_LPTAB32(7, i + 1), i);
1420 else
1421 b43_lptab_write(dev, B43_LPTAB32(10, i + 1), i);
1422 }
1423
1424 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xFF00, 0xFF);
1425 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0x8FFF, 0x5000);
1426 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, 0xFFC0, 0x1F);
1427 if (dev->phy.rev < 2) {
1428 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xEFFF);
1429 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xDFFF, 0x2000);
1430 } else {
1431 b43_phy_mask(dev, B43_PHY_OFDM(0x103), 0xFFFE);
1432 b43_phy_maskset(dev, B43_PHY_OFDM(0x103), 0xFFFB, 0x4);
1433 b43_phy_maskset(dev, B43_PHY_OFDM(0x103), 0xFFEF, 0x10);
1434 b43_radio_maskset(dev, B2063_IQ_CALIB_CTL2, 0xF3, 0x1);
1435 lpphy_set_tssi_mux(dev, TSSI_MUX_POSTPA);
1436 }
1437 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, 0x7FFF, 0x8000);
1438 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xFF);
1439 b43_phy_write(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xA);
1440 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1441 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE,
1442 B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF);
1443 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xF8FF);
1444 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1445 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE,
1446 B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW);
1447
1448 if (dev->phy.rev < 2) {
1449 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF, 0x1000);
1450 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xEFFF);
1451 } else {
1452 lpphy_set_tx_power_by_index(dev, 0x7F);
1453 }
1454
1455 b43_dummy_transmission(dev, true, true);
1456
1457 tmp = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_STAT);
1458 if (tmp & 0x8000) {
1459 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI,
1460 0xFFC0, (tmp & 0xFF) - 32);
1461 }
1462
1463 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF);
1464
1465 // (SPEC?) TODO Set "Target TX frequency" variable to 0
1466 // SPEC FIXME "Set BB Multiplier to 0xE000" impossible - bb_mult is u8!
1467 }
1468
1469 static void lpphy_tx_pctl_init_sw(struct b43_wldev *dev)
1470 {
1471 struct lpphy_tx_gains gains;
1472
1473 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1474 gains.gm = 4;
1475 gains.pad = 12;
1476 gains.pga = 12;
1477 gains.dac = 0;
1478 } else {
1479 gains.gm = 7;
1480 gains.pad = 14;
1481 gains.pga = 15;
1482 gains.dac = 0;
1483 }
1484 lpphy_set_tx_gains(dev, gains);
1485 lpphy_set_bb_mult(dev, 150);
1486 }
1487
1488 /* Initialize TX power control */
1489 static void lpphy_tx_pctl_init(struct b43_wldev *dev)
1490 {
1491 if (0/*FIXME HWPCTL capable */) {
1492 lpphy_tx_pctl_init_hw(dev);
1493 } else { /* This device is only software TX power control capable. */
1494 lpphy_tx_pctl_init_sw(dev);
1495 }
1496 }
1497
1498 static u16 b43_lpphy_op_read(struct b43_wldev *dev, u16 reg)
1499 {
1500 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1501 return b43_read16(dev, B43_MMIO_PHY_DATA);
1502 }
1503
1504 static void b43_lpphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
1505 {
1506 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1507 b43_write16(dev, B43_MMIO_PHY_DATA, value);
1508 }
1509
1510 static void b43_lpphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
1511 u16 set)
1512 {
1513 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1514 b43_write16(dev, B43_MMIO_PHY_DATA,
1515 (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
1516 }
1517
1518 static u16 b43_lpphy_op_radio_read(struct b43_wldev *dev, u16 reg)
1519 {
1520 /* Register 1 is a 32-bit register. */
1521 B43_WARN_ON(reg == 1);
1522 /* LP-PHY needs a special bit set for read access */
1523 if (dev->phy.rev < 2) {
1524 if (reg != 0x4001)
1525 reg |= 0x100;
1526 } else
1527 reg |= 0x200;
1528
1529 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1530 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
1531 }
1532
1533 static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
1534 {
1535 /* Register 1 is a 32-bit register. */
1536 B43_WARN_ON(reg == 1);
1537
1538 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1539 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
1540 }
1541
1542 static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
1543 bool blocked)
1544 {
1545 //TODO
1546 }
1547
1548 struct b206x_channel {
1549 u8 channel;
1550 u16 freq;
1551 u8 data[12];
1552 };
1553
1554 static const struct b206x_channel b2062_chantbl[] = {
1555 { .channel = 1, .freq = 2412, .data[0] = 0xFF, .data[1] = 0xFF,
1556 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1557 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1558 { .channel = 2, .freq = 2417, .data[0] = 0xFF, .data[1] = 0xFF,
1559 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1560 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1561 { .channel = 3, .freq = 2422, .data[0] = 0xFF, .data[1] = 0xFF,
1562 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1563 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1564 { .channel = 4, .freq = 2427, .data[0] = 0xFF, .data[1] = 0xFF,
1565 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1566 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1567 { .channel = 5, .freq = 2432, .data[0] = 0xFF, .data[1] = 0xFF,
1568 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1569 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1570 { .channel = 6, .freq = 2437, .data[0] = 0xFF, .data[1] = 0xFF,
1571 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1572 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1573 { .channel = 7, .freq = 2442, .data[0] = 0xFF, .data[1] = 0xFF,
1574 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1575 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1576 { .channel = 8, .freq = 2447, .data[0] = 0xFF, .data[1] = 0xFF,
1577 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1578 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1579 { .channel = 9, .freq = 2452, .data[0] = 0xFF, .data[1] = 0xFF,
1580 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1581 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1582 { .channel = 10, .freq = 2457, .data[0] = 0xFF, .data[1] = 0xFF,
1583 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1584 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1585 { .channel = 11, .freq = 2462, .data[0] = 0xFF, .data[1] = 0xFF,
1586 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1587 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1588 { .channel = 12, .freq = 2467, .data[0] = 0xFF, .data[1] = 0xFF,
1589 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1590 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1591 { .channel = 13, .freq = 2472, .data[0] = 0xFF, .data[1] = 0xFF,
1592 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1593 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1594 { .channel = 14, .freq = 2484, .data[0] = 0xFF, .data[1] = 0xFF,
1595 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1596 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1597 { .channel = 34, .freq = 5170, .data[0] = 0x00, .data[1] = 0x22,
1598 .data[2] = 0x20, .data[3] = 0x84, .data[4] = 0x3C, .data[5] = 0x77,
1599 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1600 { .channel = 38, .freq = 5190, .data[0] = 0x00, .data[1] = 0x11,
1601 .data[2] = 0x10, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1602 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1603 { .channel = 42, .freq = 5210, .data[0] = 0x00, .data[1] = 0x11,
1604 .data[2] = 0x10, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1605 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1606 { .channel = 46, .freq = 5230, .data[0] = 0x00, .data[1] = 0x00,
1607 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1608 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1609 { .channel = 36, .freq = 5180, .data[0] = 0x00, .data[1] = 0x11,
1610 .data[2] = 0x20, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1611 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1612 { .channel = 40, .freq = 5200, .data[0] = 0x00, .data[1] = 0x11,
1613 .data[2] = 0x10, .data[3] = 0x84, .data[4] = 0x3C, .data[5] = 0x77,
1614 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1615 { .channel = 44, .freq = 5220, .data[0] = 0x00, .data[1] = 0x11,
1616 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1617 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1618 { .channel = 48, .freq = 5240, .data[0] = 0x00, .data[1] = 0x00,
1619 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1620 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1621 { .channel = 52, .freq = 5260, .data[0] = 0x00, .data[1] = 0x00,
1622 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1623 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1624 { .channel = 56, .freq = 5280, .data[0] = 0x00, .data[1] = 0x00,
1625 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1626 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1627 { .channel = 60, .freq = 5300, .data[0] = 0x00, .data[1] = 0x00,
1628 .data[2] = 0x00, .data[3] = 0x63, .data[4] = 0x3C, .data[5] = 0x77,
1629 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1630 { .channel = 64, .freq = 5320, .data[0] = 0x00, .data[1] = 0x00,
1631 .data[2] = 0x00, .data[3] = 0x62, .data[4] = 0x3C, .data[5] = 0x77,
1632 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1633 { .channel = 100, .freq = 5500, .data[0] = 0x00, .data[1] = 0x00,
1634 .data[2] = 0x00, .data[3] = 0x30, .data[4] = 0x3C, .data[5] = 0x77,
1635 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1636 { .channel = 104, .freq = 5520, .data[0] = 0x00, .data[1] = 0x00,
1637 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1638 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1639 { .channel = 108, .freq = 5540, .data[0] = 0x00, .data[1] = 0x00,
1640 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1641 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1642 { .channel = 112, .freq = 5560, .data[0] = 0x00, .data[1] = 0x00,
1643 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1644 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1645 { .channel = 116, .freq = 5580, .data[0] = 0x00, .data[1] = 0x00,
1646 .data[2] = 0x00, .data[3] = 0x10, .data[4] = 0x3C, .data[5] = 0x77,
1647 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1648 { .channel = 120, .freq = 5600, .data[0] = 0x00, .data[1] = 0x00,
1649 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1650 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1651 { .channel = 124, .freq = 5620, .data[0] = 0x00, .data[1] = 0x00,
1652 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1653 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1654 { .channel = 128, .freq = 5640, .data[0] = 0x00, .data[1] = 0x00,
1655 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1656 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1657 { .channel = 132, .freq = 5660, .data[0] = 0x00, .data[1] = 0x00,
1658 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1659 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1660 { .channel = 136, .freq = 5680, .data[0] = 0x00, .data[1] = 0x00,
1661 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1662 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1663 { .channel = 140, .freq = 5700, .data[0] = 0x00, .data[1] = 0x00,
1664 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1665 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1666 { .channel = 149, .freq = 5745, .data[0] = 0x00, .data[1] = 0x00,
1667 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1668 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1669 { .channel = 153, .freq = 5765, .data[0] = 0x00, .data[1] = 0x00,
1670 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1671 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1672 { .channel = 157, .freq = 5785, .data[0] = 0x00, .data[1] = 0x00,
1673 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1674 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1675 { .channel = 161, .freq = 5805, .data[0] = 0x00, .data[1] = 0x00,
1676 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1677 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1678 { .channel = 165, .freq = 5825, .data[0] = 0x00, .data[1] = 0x00,
1679 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1680 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1681 { .channel = 184, .freq = 4920, .data[0] = 0x55, .data[1] = 0x77,
1682 .data[2] = 0x90, .data[3] = 0xF7, .data[4] = 0x3C, .data[5] = 0x77,
1683 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1684 { .channel = 188, .freq = 4940, .data[0] = 0x44, .data[1] = 0x77,
1685 .data[2] = 0x80, .data[3] = 0xE7, .data[4] = 0x3C, .data[5] = 0x77,
1686 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1687 { .channel = 192, .freq = 4960, .data[0] = 0x44, .data[1] = 0x66,
1688 .data[2] = 0x80, .data[3] = 0xE7, .data[4] = 0x3C, .data[5] = 0x77,
1689 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1690 { .channel = 196, .freq = 4980, .data[0] = 0x33, .data[1] = 0x66,
1691 .data[2] = 0x70, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1692 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1693 { .channel = 200, .freq = 5000, .data[0] = 0x22, .data[1] = 0x55,
1694 .data[2] = 0x60, .data[3] = 0xD7, .data[4] = 0x3C, .data[5] = 0x77,
1695 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1696 { .channel = 204, .freq = 5020, .data[0] = 0x22, .data[1] = 0x55,
1697 .data[2] = 0x60, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1698 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1699 { .channel = 208, .freq = 5040, .data[0] = 0x22, .data[1] = 0x44,
1700 .data[2] = 0x50, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1701 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1702 { .channel = 212, .freq = 5060, .data[0] = 0x11, .data[1] = 0x44,
1703 .data[2] = 0x50, .data[3] = 0xA5, .data[4] = 0x3C, .data[5] = 0x77,
1704 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1705 { .channel = 216, .freq = 5080, .data[0] = 0x00, .data[1] = 0x44,
1706 .data[2] = 0x40, .data[3] = 0xB6, .data[4] = 0x3C, .data[5] = 0x77,
1707 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1708 };
1709
1710 static const struct b206x_channel b2063_chantbl[] = {
1711 { .channel = 1, .freq = 2412, .data[0] = 0x6F, .data[1] = 0x3C,
1712 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1713 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1714 .data[10] = 0x80, .data[11] = 0x70, },
1715 { .channel = 2, .freq = 2417, .data[0] = 0x6F, .data[1] = 0x3C,
1716 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1717 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1718 .data[10] = 0x80, .data[11] = 0x70, },
1719 { .channel = 3, .freq = 2422, .data[0] = 0x6F, .data[1] = 0x3C,
1720 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1721 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1722 .data[10] = 0x80, .data[11] = 0x70, },
1723 { .channel = 4, .freq = 2427, .data[0] = 0x6F, .data[1] = 0x2C,
1724 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1725 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1726 .data[10] = 0x80, .data[11] = 0x70, },
1727 { .channel = 5, .freq = 2432, .data[0] = 0x6F, .data[1] = 0x2C,
1728 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1729 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1730 .data[10] = 0x80, .data[11] = 0x70, },
1731 { .channel = 6, .freq = 2437, .data[0] = 0x6F, .data[1] = 0x2C,
1732 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1733 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1734 .data[10] = 0x80, .data[11] = 0x70, },
1735 { .channel = 7, .freq = 2442, .data[0] = 0x6F, .data[1] = 0x2C,
1736 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1737 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1738 .data[10] = 0x80, .data[11] = 0x70, },
1739 { .channel = 8, .freq = 2447, .data[0] = 0x6F, .data[1] = 0x2C,
1740 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1741 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1742 .data[10] = 0x80, .data[11] = 0x70, },
1743 { .channel = 9, .freq = 2452, .data[0] = 0x6F, .data[1] = 0x1C,
1744 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1745 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1746 .data[10] = 0x80, .data[11] = 0x70, },
1747 { .channel = 10, .freq = 2457, .data[0] = 0x6F, .data[1] = 0x1C,
1748 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1749 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1750 .data[10] = 0x80, .data[11] = 0x70, },
1751 { .channel = 11, .freq = 2462, .data[0] = 0x6E, .data[1] = 0x1C,
1752 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1753 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1754 .data[10] = 0x80, .data[11] = 0x70, },
1755 { .channel = 12, .freq = 2467, .data[0] = 0x6E, .data[1] = 0x1C,
1756 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1757 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1758 .data[10] = 0x80, .data[11] = 0x70, },
1759 { .channel = 13, .freq = 2472, .data[0] = 0x6E, .data[1] = 0x1C,
1760 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1761 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1762 .data[10] = 0x80, .data[11] = 0x70, },
1763 { .channel = 14, .freq = 2484, .data[0] = 0x6E, .data[1] = 0x0C,
1764 .data[2] = 0x0C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1765 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1766 .data[10] = 0x80, .data[11] = 0x70, },
1767 { .channel = 34, .freq = 5170, .data[0] = 0x6A, .data[1] = 0x0C,
1768 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x02, .data[5] = 0x05,
1769 .data[6] = 0x0D, .data[7] = 0x0D, .data[8] = 0x77, .data[9] = 0x80,
1770 .data[10] = 0x20, .data[11] = 0x00, },
1771 { .channel = 36, .freq = 5180, .data[0] = 0x6A, .data[1] = 0x0C,
1772 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x05,
1773 .data[6] = 0x0D, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x80,
1774 .data[10] = 0x20, .data[11] = 0x00, },
1775 { .channel = 38, .freq = 5190, .data[0] = 0x6A, .data[1] = 0x0C,
1776 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1777 .data[6] = 0x0C, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x80,
1778 .data[10] = 0x20, .data[11] = 0x00, },
1779 { .channel = 40, .freq = 5200, .data[0] = 0x69, .data[1] = 0x0C,
1780 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1781 .data[6] = 0x0C, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x70,
1782 .data[10] = 0x20, .data[11] = 0x00, },
1783 { .channel = 42, .freq = 5210, .data[0] = 0x69, .data[1] = 0x0C,
1784 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1785 .data[6] = 0x0B, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x70,
1786 .data[10] = 0x20, .data[11] = 0x00, },
1787 { .channel = 44, .freq = 5220, .data[0] = 0x69, .data[1] = 0x0C,
1788 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x04,
1789 .data[6] = 0x0B, .data[7] = 0x0B, .data[8] = 0x77, .data[9] = 0x60,
1790 .data[10] = 0x20, .data[11] = 0x00, },
1791 { .channel = 46, .freq = 5230, .data[0] = 0x69, .data[1] = 0x0C,
1792 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x03,
1793 .data[6] = 0x0A, .data[7] = 0x0B, .data[8] = 0x77, .data[9] = 0x60,
1794 .data[10] = 0x20, .data[11] = 0x00, },
1795 { .channel = 48, .freq = 5240, .data[0] = 0x69, .data[1] = 0x0C,
1796 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x03,
1797 .data[6] = 0x0A, .data[7] = 0x0A, .data[8] = 0x77, .data[9] = 0x60,
1798 .data[10] = 0x20, .data[11] = 0x00, },
1799 { .channel = 52, .freq = 5260, .data[0] = 0x68, .data[1] = 0x0C,
1800 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x02,
1801 .data[6] = 0x09, .data[7] = 0x09, .data[8] = 0x77, .data[9] = 0x60,
1802 .data[10] = 0x20, .data[11] = 0x00, },
1803 { .channel = 56, .freq = 5280, .data[0] = 0x68, .data[1] = 0x0C,
1804 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x01,
1805 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1806 .data[10] = 0x10, .data[11] = 0x00, },
1807 { .channel = 60, .freq = 5300, .data[0] = 0x68, .data[1] = 0x0C,
1808 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x01,
1809 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1810 .data[10] = 0x10, .data[11] = 0x00, },
1811 { .channel = 64, .freq = 5320, .data[0] = 0x67, .data[1] = 0x0C,
1812 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1813 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1814 .data[10] = 0x10, .data[11] = 0x00, },
1815 { .channel = 100, .freq = 5500, .data[0] = 0x64, .data[1] = 0x0C,
1816 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1817 .data[6] = 0x02, .data[7] = 0x01, .data[8] = 0x77, .data[9] = 0x20,
1818 .data[10] = 0x00, .data[11] = 0x00, },
1819 { .channel = 104, .freq = 5520, .data[0] = 0x64, .data[1] = 0x0C,
1820 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1821 .data[6] = 0x01, .data[7] = 0x01, .data[8] = 0x77, .data[9] = 0x20,
1822 .data[10] = 0x00, .data[11] = 0x00, },
1823 { .channel = 108, .freq = 5540, .data[0] = 0x63, .data[1] = 0x0C,
1824 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1825 .data[6] = 0x01, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1826 .data[10] = 0x00, .data[11] = 0x00, },
1827 { .channel = 112, .freq = 5560, .data[0] = 0x63, .data[1] = 0x0C,
1828 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1829 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1830 .data[10] = 0x00, .data[11] = 0x00, },
1831 { .channel = 116, .freq = 5580, .data[0] = 0x62, .data[1] = 0x0C,
1832 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1833 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1834 .data[10] = 0x00, .data[11] = 0x00, },
1835 { .channel = 120, .freq = 5600, .data[0] = 0x62, .data[1] = 0x0C,
1836 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1837 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1838 .data[10] = 0x00, .data[11] = 0x00, },
1839 { .channel = 124, .freq = 5620, .data[0] = 0x62, .data[1] = 0x0C,
1840 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1841 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1842 .data[10] = 0x00, .data[11] = 0x00, },
1843 { .channel = 128, .freq = 5640, .data[0] = 0x61, .data[1] = 0x0C,
1844 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1845 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1846 .data[10] = 0x00, .data[11] = 0x00, },
1847 { .channel = 132, .freq = 5660, .data[0] = 0x61, .data[1] = 0x0C,
1848 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1849 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1850 .data[10] = 0x00, .data[11] = 0x00, },
1851 { .channel = 136, .freq = 5680, .data[0] = 0x61, .data[1] = 0x0C,
1852 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1853 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1854 .data[10] = 0x00, .data[11] = 0x00, },
1855 { .channel = 140, .freq = 5700, .data[0] = 0x60, .data[1] = 0x0C,
1856 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1857 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1858 .data[10] = 0x00, .data[11] = 0x00, },
1859 { .channel = 149, .freq = 5745, .data[0] = 0x60, .data[1] = 0x0C,
1860 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1861 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1862 .data[10] = 0x00, .data[11] = 0x00, },
1863 { .channel = 153, .freq = 5765, .data[0] = 0x60, .data[1] = 0x0C,
1864 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1865 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1866 .data[10] = 0x00, .data[11] = 0x00, },
1867 { .channel = 157, .freq = 5785, .data[0] = 0x60, .data[1] = 0x0C,
1868 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1869 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1870 .data[10] = 0x00, .data[11] = 0x00, },
1871 { .channel = 161, .freq = 5805, .data[0] = 0x60, .data[1] = 0x0C,
1872 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1873 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1874 .data[10] = 0x00, .data[11] = 0x00, },
1875 { .channel = 165, .freq = 5825, .data[0] = 0x60, .data[1] = 0x0C,
1876 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1877 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1878 .data[10] = 0x00, .data[11] = 0x00, },
1879 { .channel = 184, .freq = 4920, .data[0] = 0x6E, .data[1] = 0x0C,
1880 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x09, .data[5] = 0x0E,
1881 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xC0,
1882 .data[10] = 0x50, .data[11] = 0x00, },
1883 { .channel = 188, .freq = 4940, .data[0] = 0x6E, .data[1] = 0x0C,
1884 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x09, .data[5] = 0x0D,
1885 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xB0,
1886 .data[10] = 0x50, .data[11] = 0x00, },
1887 { .channel = 192, .freq = 4960, .data[0] = 0x6E, .data[1] = 0x0C,
1888 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0C,
1889 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xB0,
1890 .data[10] = 0x50, .data[11] = 0x00, },
1891 { .channel = 196, .freq = 4980, .data[0] = 0x6D, .data[1] = 0x0C,
1892 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0C,
1893 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1894 .data[10] = 0x40, .data[11] = 0x00, },
1895 { .channel = 200, .freq = 5000, .data[0] = 0x6D, .data[1] = 0x0C,
1896 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0B,
1897 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1898 .data[10] = 0x40, .data[11] = 0x00, },
1899 { .channel = 204, .freq = 5020, .data[0] = 0x6D, .data[1] = 0x0C,
1900 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0A,
1901 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1902 .data[10] = 0x40, .data[11] = 0x00, },
1903 { .channel = 208, .freq = 5040, .data[0] = 0x6C, .data[1] = 0x0C,
1904 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x07, .data[5] = 0x09,
1905 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1906 .data[10] = 0x40, .data[11] = 0x00, },
1907 { .channel = 212, .freq = 5060, .data[0] = 0x6C, .data[1] = 0x0C,
1908 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x06, .data[5] = 0x08,
1909 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1910 .data[10] = 0x40, .data[11] = 0x00, },
1911 { .channel = 216, .freq = 5080, .data[0] = 0x6C, .data[1] = 0x0C,
1912 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x05, .data[5] = 0x08,
1913 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1914 .data[10] = 0x40, .data[11] = 0x00, },
1915 };
1916
1917 static void lpphy_b2062_reset_pll_bias(struct b43_wldev *dev)
1918 {
1919 struct ssb_bus *bus = dev->dev->bus;
1920
1921 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0xFF);
1922 udelay(20);
1923 if (bus->chip_id == 0x5354) {
1924 b43_radio_write(dev, B2062_N_COMM1, 4);
1925 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 4);
1926 } else {
1927 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0);
1928 }
1929 udelay(5);
1930 }
1931
1932 static void lpphy_b2062_vco_calib(struct b43_wldev *dev)
1933 {
1934 b43_radio_write(dev, B2062_S_RFPLL_CTL21, 0x42);
1935 b43_radio_write(dev, B2062_S_RFPLL_CTL21, 0x62);
1936 udelay(200);
1937 }
1938
1939 static int lpphy_b2062_tune(struct b43_wldev *dev,
1940 unsigned int channel)
1941 {
1942 struct b43_phy_lp *lpphy = dev->phy.lp;
1943 struct ssb_bus *bus = dev->dev->bus;
1944 const struct b206x_channel *chandata = NULL;
1945 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
1946 u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8, tmp9;
1947 int i, err = 0;
1948
1949 for (i = 0; i < ARRAY_SIZE(b2062_chantbl); i++) {
1950 if (b2062_chantbl[i].channel == channel) {
1951 chandata = &b2062_chantbl[i];
1952 break;
1953 }
1954 }
1955
1956 if (B43_WARN_ON(!chandata))
1957 return -EINVAL;
1958
1959 b43_radio_set(dev, B2062_S_RFPLL_CTL14, 0x04);
1960 b43_radio_write(dev, B2062_N_LGENA_TUNE0, chandata->data[0]);
1961 b43_radio_write(dev, B2062_N_LGENA_TUNE2, chandata->data[1]);
1962 b43_radio_write(dev, B2062_N_LGENA_TUNE3, chandata->data[2]);
1963 b43_radio_write(dev, B2062_N_TX_TUNE, chandata->data[3]);
1964 b43_radio_write(dev, B2062_S_LGENG_CTL1, chandata->data[4]);
1965 b43_radio_write(dev, B2062_N_LGENA_CTL5, chandata->data[5]);
1966 b43_radio_write(dev, B2062_N_LGENA_CTL6, chandata->data[6]);
1967 b43_radio_write(dev, B2062_N_TX_PGA, chandata->data[7]);
1968 b43_radio_write(dev, B2062_N_TX_PAD, chandata->data[8]);
1969
1970 tmp1 = crystal_freq / 1000;
1971 tmp2 = lpphy->pdiv * 1000;
1972 b43_radio_write(dev, B2062_S_RFPLL_CTL33, 0xCC);
1973 b43_radio_write(dev, B2062_S_RFPLL_CTL34, 0x07);
1974 lpphy_b2062_reset_pll_bias(dev);
1975 tmp3 = tmp2 * channel2freq_lp(channel);
1976 if (channel2freq_lp(channel) < 4000)
1977 tmp3 *= 2;
1978 tmp4 = 48 * tmp1;
1979 tmp6 = tmp3 / tmp4;
1980 tmp7 = tmp3 % tmp4;
1981 b43_radio_write(dev, B2062_S_RFPLL_CTL26, tmp6);
1982 tmp5 = tmp7 * 0x100;
1983 tmp6 = tmp5 / tmp4;
1984 tmp7 = tmp5 % tmp4;
1985 b43_radio_write(dev, B2062_S_RFPLL_CTL27, tmp6);
1986 tmp5 = tmp7 * 0x100;
1987 tmp6 = tmp5 / tmp4;
1988 tmp7 = tmp5 % tmp4;
1989 b43_radio_write(dev, B2062_S_RFPLL_CTL28, tmp6);
1990 tmp5 = tmp7 * 0x100;
1991 tmp6 = tmp5 / tmp4;
1992 tmp7 = tmp5 % tmp4;
1993 b43_radio_write(dev, B2062_S_RFPLL_CTL29, tmp6 + ((2 * tmp7) / tmp4));
1994 tmp8 = b43_radio_read(dev, B2062_S_RFPLL_CTL19);
1995 tmp9 = ((2 * tmp3 * (tmp8 + 1)) + (3 * tmp1)) / (6 * tmp1);
1996 b43_radio_write(dev, B2062_S_RFPLL_CTL23, (tmp9 >> 8) + 16);
1997 b43_radio_write(dev, B2062_S_RFPLL_CTL24, tmp9 & 0xFF);
1998
1999 lpphy_b2062_vco_calib(dev);
2000 if (b43_radio_read(dev, B2062_S_RFPLL_CTL3) & 0x10) {
2001 b43_radio_write(dev, B2062_S_RFPLL_CTL33, 0xFC);
2002 b43_radio_write(dev, B2062_S_RFPLL_CTL34, 0);
2003 lpphy_b2062_reset_pll_bias(dev);
2004 lpphy_b2062_vco_calib(dev);
2005 if (b43_radio_read(dev, B2062_S_RFPLL_CTL3) & 0x10)
2006 err = -EIO;
2007 }
2008
2009 b43_radio_mask(dev, B2062_S_RFPLL_CTL14, ~0x04);
2010 return err;
2011 }
2012
2013
2014 /* This was previously called lpphy_japan_filter */
2015 static void lpphy_set_analog_filter(struct b43_wldev *dev, int channel)
2016 {
2017 struct b43_phy_lp *lpphy = dev->phy.lp;
2018 u16 tmp = (channel == 14); //SPEC FIXME check japanwidefilter!
2019
2020 if (dev->phy.rev < 2) { //SPEC FIXME Isn't this rev0/1-specific?
2021 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFCFF, tmp << 9);
2022 if ((dev->phy.rev == 1) && (lpphy->rc_cap))
2023 lpphy_set_rc_cap(dev);
2024 } else {
2025 b43_radio_write(dev, B2063_TX_BB_SP3, 0x3F);
2026 }
2027 }
2028
2029 static void lpphy_b2063_vco_calib(struct b43_wldev *dev)
2030 {
2031 u16 tmp;
2032
2033 b43_radio_mask(dev, B2063_PLL_SP1, ~0x40);
2034 tmp = b43_radio_read(dev, B2063_PLL_JTAG_CALNRST) & 0xF8;
2035 b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp);
2036 udelay(1);
2037 b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x4);
2038 udelay(1);
2039 b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x6);
2040 udelay(1);
2041 b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x7);
2042 udelay(300);
2043 b43_radio_set(dev, B2063_PLL_SP1, 0x40);
2044 }
2045
2046 static int lpphy_b2063_tune(struct b43_wldev *dev,
2047 unsigned int channel)
2048 {
2049 struct ssb_bus *bus = dev->dev->bus;
2050
2051 static const struct b206x_channel *chandata = NULL;
2052 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
2053 u32 freqref, vco_freq, val1, val2, val3, timeout, timeoutref, count;
2054 u16 old_comm15, scale;
2055 u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
2056 int i, div = (crystal_freq <= 26000000 ? 1 : 2);
2057
2058 for (i = 0; i < ARRAY_SIZE(b2063_chantbl); i++) {
2059 if (b2063_chantbl[i].channel == channel) {
2060 chandata = &b2063_chantbl[i];
2061 break;
2062 }
2063 }
2064
2065 if (B43_WARN_ON(!chandata))
2066 return -EINVAL;
2067
2068 b43_radio_write(dev, B2063_LOGEN_VCOBUF1, chandata->data[0]);
2069 b43_radio_write(dev, B2063_LOGEN_MIXER2, chandata->data[1]);
2070 b43_radio_write(dev, B2063_LOGEN_BUF2, chandata->data[2]);
2071 b43_radio_write(dev, B2063_LOGEN_RCCR1, chandata->data[3]);
2072 b43_radio_write(dev, B2063_A_RX_1ST3, chandata->data[4]);
2073 b43_radio_write(dev, B2063_A_RX_2ND1, chandata->data[5]);
2074 b43_radio_write(dev, B2063_A_RX_2ND4, chandata->data[6]);
2075 b43_radio_write(dev, B2063_A_RX_2ND7, chandata->data[7]);
2076 b43_radio_write(dev, B2063_A_RX_PS6, chandata->data[8]);
2077 b43_radio_write(dev, B2063_TX_RF_CTL2, chandata->data[9]);
2078 b43_radio_write(dev, B2063_TX_RF_CTL5, chandata->data[10]);
2079 b43_radio_write(dev, B2063_PA_CTL11, chandata->data[11]);
2080
2081 old_comm15 = b43_radio_read(dev, B2063_COMM15);
2082 b43_radio_set(dev, B2063_COMM15, 0x1E);
2083
2084 if (chandata->freq > 4000) /* spec says 2484, but 4000 is safer */
2085 vco_freq = chandata->freq << 1;
2086 else
2087 vco_freq = chandata->freq << 2;
2088
2089 freqref = crystal_freq * 3;
2090 val1 = lpphy_qdiv_roundup(crystal_freq, 1000000, 16);
2091 val2 = lpphy_qdiv_roundup(crystal_freq, 1000000 * div, 16);
2092 val3 = lpphy_qdiv_roundup(vco_freq, 3, 16);
2093 timeout = ((((8 * crystal_freq) / (div * 5000000)) + 1) >> 1) - 1;
2094 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB3, 0x2);
2095 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB6,
2096 0xFFF8, timeout >> 2);
2097 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB7,
2098 0xFF9F,timeout << 5);
2099
2100 timeoutref = ((((8 * crystal_freq) / (div * (timeout + 1))) +
2101 999999) / 1000000) + 1;
2102 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB5, timeoutref);
2103
2104 count = lpphy_qdiv_roundup(val3, val2 + 16, 16);
2105 count *= (timeout + 1) * (timeoutref + 1);
2106 count--;
2107 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB7,
2108 0xF0, count >> 8);
2109 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB8, count & 0xFF);
2110
2111 tmp1 = ((val3 * 62500) / freqref) << 4;
2112 tmp2 = ((val3 * 62500) % freqref) << 4;
2113 while (tmp2 >= freqref) {
2114 tmp1++;
2115 tmp2 -= freqref;
2116 }
2117 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG1, 0xFFE0, tmp1 >> 4);
2118 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG2, 0xFE0F, tmp1 << 4);
2119 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG2, 0xFFF0, tmp1 >> 16);
2120 b43_radio_write(dev, B2063_PLL_JTAG_PLL_SG3, (tmp2 >> 8) & 0xFF);
2121 b43_radio_write(dev, B2063_PLL_JTAG_PLL_SG4, tmp2 & 0xFF);
2122
2123 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF1, 0xB9);
2124 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF2, 0x88);
2125 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF3, 0x28);
2126 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF4, 0x63);
2127
2128 tmp3 = ((41 * (val3 - 3000)) /1200) + 27;
2129 tmp4 = lpphy_qdiv_roundup(132000 * tmp1, 8451, 16);
2130
2131 if ((tmp4 + tmp3 - 1) / tmp3 > 60) {
2132 scale = 1;
2133 tmp5 = ((tmp4 + tmp3) / (tmp3 << 1)) - 8;
2134 } else {
2135 scale = 0;
2136 tmp5 = ((tmp4 + (tmp3 >> 1)) / tmp3) - 8;
2137 }
2138 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFC0, tmp5);
2139 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFBF, scale << 6);
2140
2141 tmp6 = lpphy_qdiv_roundup(100 * val1, val3, 16);
2142 tmp6 *= (tmp5 * 8) * (scale + 1);
2143 if (tmp6 > 150)
2144 tmp6 = 0;
2145
2146 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFE0, tmp6);
2147 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFDF, scale << 5);
2148
2149 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFFFB, 0x4);
2150 if (crystal_freq > 26000000)
2151 b43_radio_set(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0x2);
2152 else
2153 b43_radio_mask(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFD);
2154
2155 if (val1 == 45)
2156 b43_radio_set(dev, B2063_PLL_JTAG_PLL_VCO1, 0x2);
2157 else
2158 b43_radio_mask(dev, B2063_PLL_JTAG_PLL_VCO1, 0xFD);
2159
2160 b43_radio_set(dev, B2063_PLL_SP2, 0x3);
2161 udelay(1);
2162 b43_radio_mask(dev, B2063_PLL_SP2, 0xFFFC);
2163 lpphy_b2063_vco_calib(dev);
2164 b43_radio_write(dev, B2063_COMM15, old_comm15);
2165
2166 return 0;
2167 }
2168
2169 static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
2170 unsigned int new_channel)
2171 {
2172 struct b43_phy_lp *lpphy = dev->phy.lp;
2173 int err;
2174
2175 if (dev->phy.radio_ver == 0x2063) {
2176 err = lpphy_b2063_tune(dev, new_channel);
2177 if (err)
2178 return err;
2179 } else {
2180 err = lpphy_b2062_tune(dev, new_channel);
2181 if (err)
2182 return err;
2183 lpphy_set_analog_filter(dev, new_channel);
2184 lpphy_adjust_gain_table(dev, channel2freq_lp(new_channel));
2185 }
2186
2187 lpphy->channel = new_channel;
2188 b43_write16(dev, B43_MMIO_CHANNEL, new_channel);
2189
2190 return 0;
2191 }
2192
2193 static int b43_lpphy_op_init(struct b43_wldev *dev)
2194 {
2195 int err;
2196
2197 lpphy_read_band_sprom(dev); //FIXME should this be in prepare_structs?
2198 lpphy_baseband_init(dev);
2199 lpphy_radio_init(dev);
2200 lpphy_calibrate_rc(dev);
2201 err = b43_lpphy_op_switch_channel(dev, 7);
2202 if (err) {
2203 b43dbg(dev->wl, "Switch to channel 7 failed, error = %d.\n",
2204 err);
2205 }
2206 lpphy_tx_pctl_init(dev);
2207 lpphy_calibration(dev);
2208 //TODO ACI init
2209
2210 return 0;
2211 }
2212
2213 static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
2214 {
2215 if (dev->phy.rev >= 2)
2216 return; // rev2+ doesn't support antenna diversity
2217
2218 if (B43_WARN_ON(antenna > B43_ANTENNA_AUTO1))
2219 return;
2220
2221 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFFD, antenna & 0x2);
2222 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFFE, antenna & 0x1);
2223 }
2224
2225 static void b43_lpphy_op_adjust_txpower(struct b43_wldev *dev)
2226 {
2227 //TODO
2228 }
2229
2230 static enum b43_txpwr_result b43_lpphy_op_recalc_txpower(struct b43_wldev *dev,
2231 bool ignore_tssi)
2232 {
2233 //TODO
2234 return B43_TXPWR_RES_DONE;
2235 }
2236
2237 void b43_lpphy_op_switch_analog(struct b43_wldev *dev, bool on)
2238 {
2239 if (on) {
2240 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xfff8);
2241 } else {
2242 b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0x0007);
2243 b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 0x0007);
2244 }
2245 }
2246
2247 const struct b43_phy_operations b43_phyops_lp = {
2248 .allocate = b43_lpphy_op_allocate,
2249 .free = b43_lpphy_op_free,
2250 .prepare_structs = b43_lpphy_op_prepare_structs,
2251 .init = b43_lpphy_op_init,
2252 .phy_read = b43_lpphy_op_read,
2253 .phy_write = b43_lpphy_op_write,
2254 .phy_maskset = b43_lpphy_op_maskset,
2255 .radio_read = b43_lpphy_op_radio_read,
2256 .radio_write = b43_lpphy_op_radio_write,
2257 .software_rfkill = b43_lpphy_op_software_rfkill,
2258 .switch_analog = b43_lpphy_op_switch_analog,
2259 .switch_channel = b43_lpphy_op_switch_channel,
2260 .get_default_chan = b43_lpphy_op_get_default_chan,
2261 .set_rx_antenna = b43_lpphy_op_set_rx_antenna,
2262 .recalc_txpower = b43_lpphy_op_recalc_txpower,
2263 .adjust_txpower = b43_lpphy_op_adjust_txpower,
2264 };
mm of the moment repository