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On Tue, Nov 06, 2007 at 02:33:53AM -0800, akpm@linux-foundation.org wrote:
[mmotm.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
blobafe19f2bd4f61dc7b9455cdef9d646b03360af71
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/sched.h>
34 #include <linux/skbuff.h>
35 #include <linux/netdevice.h>
36 #include <linux/wireless.h>
37 #include <linux/firmware.h>
38 #include <linux/etherdevice.h>
39 #include <asm/unaligned.h>
40 #include <net/mac80211.h>
41
42 #include "iwl-fh.h"
43 #include "iwl-3945-fh.h"
44 #include "iwl-commands.h"
45 #include "iwl-sta.h"
46 #include "iwl-3945.h"
47 #include "iwl-eeprom.h"
48 #include "iwl-helpers.h"
49 #include "iwl-core.h"
50 #include "iwl-led.h"
51 #include "iwl-3945-led.h"
52
53 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
54 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
55 IWL_RATE_##r##M_IEEE, \
56 IWL_RATE_##ip##M_INDEX, \
57 IWL_RATE_##in##M_INDEX, \
58 IWL_RATE_##rp##M_INDEX, \
59 IWL_RATE_##rn##M_INDEX, \
60 IWL_RATE_##pp##M_INDEX, \
61 IWL_RATE_##np##M_INDEX, \
62 IWL_RATE_##r##M_INDEX_TABLE, \
63 IWL_RATE_##ip##M_INDEX_TABLE }
64
65 /*
66 * Parameter order:
67 * rate, prev rate, next rate, prev tgg rate, next tgg rate
68 *
69 * If there isn't a valid next or previous rate then INV is used which
70 * maps to IWL_RATE_INVALID
71 *
72 */
73 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
74 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
75 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
76 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
77 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
78 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
79 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
80 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
81 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
82 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
83 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
84 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
85 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
86 };
87
88 /* 1 = enable the iwl3945_disable_events() function */
89 #define IWL_EVT_DISABLE (0)
90 #define IWL_EVT_DISABLE_SIZE (1532/32)
91
92 /**
93 * iwl3945_disable_events - Disable selected events in uCode event log
94 *
95 * Disable an event by writing "1"s into "disable"
96 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
97 * Default values of 0 enable uCode events to be logged.
98 * Use for only special debugging. This function is just a placeholder as-is,
99 * you'll need to provide the special bits! ...
100 * ... and set IWL_EVT_DISABLE to 1. */
101 void iwl3945_disable_events(struct iwl_priv *priv)
102 {
103 int i;
104 u32 base; /* SRAM address of event log header */
105 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
106 u32 array_size; /* # of u32 entries in array */
107 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
108 0x00000000, /* 31 - 0 Event id numbers */
109 0x00000000, /* 63 - 32 */
110 0x00000000, /* 95 - 64 */
111 0x00000000, /* 127 - 96 */
112 0x00000000, /* 159 - 128 */
113 0x00000000, /* 191 - 160 */
114 0x00000000, /* 223 - 192 */
115 0x00000000, /* 255 - 224 */
116 0x00000000, /* 287 - 256 */
117 0x00000000, /* 319 - 288 */
118 0x00000000, /* 351 - 320 */
119 0x00000000, /* 383 - 352 */
120 0x00000000, /* 415 - 384 */
121 0x00000000, /* 447 - 416 */
122 0x00000000, /* 479 - 448 */
123 0x00000000, /* 511 - 480 */
124 0x00000000, /* 543 - 512 */
125 0x00000000, /* 575 - 544 */
126 0x00000000, /* 607 - 576 */
127 0x00000000, /* 639 - 608 */
128 0x00000000, /* 671 - 640 */
129 0x00000000, /* 703 - 672 */
130 0x00000000, /* 735 - 704 */
131 0x00000000, /* 767 - 736 */
132 0x00000000, /* 799 - 768 */
133 0x00000000, /* 831 - 800 */
134 0x00000000, /* 863 - 832 */
135 0x00000000, /* 895 - 864 */
136 0x00000000, /* 927 - 896 */
137 0x00000000, /* 959 - 928 */
138 0x00000000, /* 991 - 960 */
139 0x00000000, /* 1023 - 992 */
140 0x00000000, /* 1055 - 1024 */
141 0x00000000, /* 1087 - 1056 */
142 0x00000000, /* 1119 - 1088 */
143 0x00000000, /* 1151 - 1120 */
144 0x00000000, /* 1183 - 1152 */
145 0x00000000, /* 1215 - 1184 */
146 0x00000000, /* 1247 - 1216 */
147 0x00000000, /* 1279 - 1248 */
148 0x00000000, /* 1311 - 1280 */
149 0x00000000, /* 1343 - 1312 */
150 0x00000000, /* 1375 - 1344 */
151 0x00000000, /* 1407 - 1376 */
152 0x00000000, /* 1439 - 1408 */
153 0x00000000, /* 1471 - 1440 */
154 0x00000000, /* 1503 - 1472 */
155 };
156
157 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
158 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
159 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
160 return;
161 }
162
163 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
164 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
165
166 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
167 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
168 disable_ptr);
169 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
170 iwl_write_targ_mem(priv,
171 disable_ptr + (i * sizeof(u32)),
172 evt_disable[i]);
173
174 } else {
175 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
176 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n");
177 IWL_DEBUG_INFO(priv, " in SRAM at 0x%x, size %d u32s\n",
178 disable_ptr, array_size);
179 }
180
181 }
182
183 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
184 {
185 int idx;
186
187 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
188 if (iwl3945_rates[idx].plcp == plcp)
189 return idx;
190 return -1;
191 }
192
193 #ifdef CONFIG_IWLWIFI_DEBUG
194 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
195
196 static const char *iwl3945_get_tx_fail_reason(u32 status)
197 {
198 switch (status & TX_STATUS_MSK) {
199 case TX_STATUS_SUCCESS:
200 return "SUCCESS";
201 TX_STATUS_ENTRY(SHORT_LIMIT);
202 TX_STATUS_ENTRY(LONG_LIMIT);
203 TX_STATUS_ENTRY(FIFO_UNDERRUN);
204 TX_STATUS_ENTRY(MGMNT_ABORT);
205 TX_STATUS_ENTRY(NEXT_FRAG);
206 TX_STATUS_ENTRY(LIFE_EXPIRE);
207 TX_STATUS_ENTRY(DEST_PS);
208 TX_STATUS_ENTRY(ABORTED);
209 TX_STATUS_ENTRY(BT_RETRY);
210 TX_STATUS_ENTRY(STA_INVALID);
211 TX_STATUS_ENTRY(FRAG_DROPPED);
212 TX_STATUS_ENTRY(TID_DISABLE);
213 TX_STATUS_ENTRY(FRAME_FLUSHED);
214 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
215 TX_STATUS_ENTRY(TX_LOCKED);
216 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
217 }
218
219 return "UNKNOWN";
220 }
221 #else
222 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
223 {
224 return "";
225 }
226 #endif
227
228 /*
229 * get ieee prev rate from rate scale table.
230 * for A and B mode we need to overright prev
231 * value
232 */
233 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
234 {
235 int next_rate = iwl3945_get_prev_ieee_rate(rate);
236
237 switch (priv->band) {
238 case IEEE80211_BAND_5GHZ:
239 if (rate == IWL_RATE_12M_INDEX)
240 next_rate = IWL_RATE_9M_INDEX;
241 else if (rate == IWL_RATE_6M_INDEX)
242 next_rate = IWL_RATE_6M_INDEX;
243 break;
244 case IEEE80211_BAND_2GHZ:
245 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
246 iwl_is_associated(priv)) {
247 if (rate == IWL_RATE_11M_INDEX)
248 next_rate = IWL_RATE_5M_INDEX;
249 }
250 break;
251
252 default:
253 break;
254 }
255
256 return next_rate;
257 }
258
259
260 /**
261 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
262 *
263 * When FW advances 'R' index, all entries between old and new 'R' index
264 * need to be reclaimed. As result, some free space forms. If there is
265 * enough free space (> low mark), wake the stack that feeds us.
266 */
267 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
268 int txq_id, int index)
269 {
270 struct iwl_tx_queue *txq = &priv->txq[txq_id];
271 struct iwl_queue *q = &txq->q;
272 struct iwl_tx_info *tx_info;
273
274 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
275
276 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
277 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
278
279 tx_info = &txq->txb[txq->q.read_ptr];
280 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
281 tx_info->skb[0] = NULL;
282 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
283 }
284
285 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
286 (txq_id != IWL_CMD_QUEUE_NUM) &&
287 priv->mac80211_registered)
288 iwl_wake_queue(priv, txq_id);
289 }
290
291 /**
292 * iwl3945_rx_reply_tx - Handle Tx response
293 */
294 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
295 struct iwl_rx_mem_buffer *rxb)
296 {
297 struct iwl_rx_packet *pkt = rxb_addr(rxb);
298 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
299 int txq_id = SEQ_TO_QUEUE(sequence);
300 int index = SEQ_TO_INDEX(sequence);
301 struct iwl_tx_queue *txq = &priv->txq[txq_id];
302 struct ieee80211_tx_info *info;
303 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
304 u32 status = le32_to_cpu(tx_resp->status);
305 int rate_idx;
306 int fail;
307
308 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
309 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
310 "is out of range [0-%d] %d %d\n", txq_id,
311 index, txq->q.n_bd, txq->q.write_ptr,
312 txq->q.read_ptr);
313 return;
314 }
315
316 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
317 ieee80211_tx_info_clear_status(info);
318
319 /* Fill the MRR chain with some info about on-chip retransmissions */
320 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
321 if (info->band == IEEE80211_BAND_5GHZ)
322 rate_idx -= IWL_FIRST_OFDM_RATE;
323
324 fail = tx_resp->failure_frame;
325
326 info->status.rates[0].idx = rate_idx;
327 info->status.rates[0].count = fail + 1; /* add final attempt */
328
329 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
330 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
331 IEEE80211_TX_STAT_ACK : 0;
332
333 IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
334 txq_id, iwl3945_get_tx_fail_reason(status), status,
335 tx_resp->rate, tx_resp->failure_frame);
336
337 IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
338 iwl3945_tx_queue_reclaim(priv, txq_id, index);
339
340 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
341 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
342 }
343
344
345
346 /*****************************************************************************
347 *
348 * Intel PRO/Wireless 3945ABG/BG Network Connection
349 *
350 * RX handler implementations
351 *
352 *****************************************************************************/
353
354 void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
355 struct iwl_rx_mem_buffer *rxb)
356 {
357 struct iwl_rx_packet *pkt = rxb_addr(rxb);
358 IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
359 (int)sizeof(struct iwl3945_notif_statistics),
360 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
361
362 memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
363
364 iwl_leds_background(priv);
365 }
366
367 /******************************************************************************
368 *
369 * Misc. internal state and helper functions
370 *
371 ******************************************************************************/
372 #ifdef CONFIG_IWLWIFI_DEBUG
373
374 /**
375 * iwl3945_report_frame - dump frame to syslog during debug sessions
376 *
377 * You may hack this function to show different aspects of received frames,
378 * including selective frame dumps.
379 * group100 parameter selects whether to show 1 out of 100 good frames.
380 */
381 static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
382 struct iwl_rx_packet *pkt,
383 struct ieee80211_hdr *header, int group100)
384 {
385 u32 to_us;
386 u32 print_summary = 0;
387 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
388 u32 hundred = 0;
389 u32 dataframe = 0;
390 __le16 fc;
391 u16 seq_ctl;
392 u16 channel;
393 u16 phy_flags;
394 u16 length;
395 u16 status;
396 u16 bcn_tmr;
397 u32 tsf_low;
398 u64 tsf;
399 u8 rssi;
400 u8 agc;
401 u16 sig_avg;
402 u16 noise_diff;
403 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
404 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
405 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
406 u8 *data = IWL_RX_DATA(pkt);
407
408 /* MAC header */
409 fc = header->frame_control;
410 seq_ctl = le16_to_cpu(header->seq_ctrl);
411
412 /* metadata */
413 channel = le16_to_cpu(rx_hdr->channel);
414 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
415 length = le16_to_cpu(rx_hdr->len);
416
417 /* end-of-frame status and timestamp */
418 status = le32_to_cpu(rx_end->status);
419 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
420 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
421 tsf = le64_to_cpu(rx_end->timestamp);
422
423 /* signal statistics */
424 rssi = rx_stats->rssi;
425 agc = rx_stats->agc;
426 sig_avg = le16_to_cpu(rx_stats->sig_avg);
427 noise_diff = le16_to_cpu(rx_stats->noise_diff);
428
429 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
430
431 /* if data frame is to us and all is good,
432 * (optionally) print summary for only 1 out of every 100 */
433 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
434 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
435 dataframe = 1;
436 if (!group100)
437 print_summary = 1; /* print each frame */
438 else if (priv->framecnt_to_us < 100) {
439 priv->framecnt_to_us++;
440 print_summary = 0;
441 } else {
442 priv->framecnt_to_us = 0;
443 print_summary = 1;
444 hundred = 1;
445 }
446 } else {
447 /* print summary for all other frames */
448 print_summary = 1;
449 }
450
451 if (print_summary) {
452 char *title;
453 int rate;
454
455 if (hundred)
456 title = "100Frames";
457 else if (ieee80211_has_retry(fc))
458 title = "Retry";
459 else if (ieee80211_is_assoc_resp(fc))
460 title = "AscRsp";
461 else if (ieee80211_is_reassoc_resp(fc))
462 title = "RasRsp";
463 else if (ieee80211_is_probe_resp(fc)) {
464 title = "PrbRsp";
465 print_dump = 1; /* dump frame contents */
466 } else if (ieee80211_is_beacon(fc)) {
467 title = "Beacon";
468 print_dump = 1; /* dump frame contents */
469 } else if (ieee80211_is_atim(fc))
470 title = "ATIM";
471 else if (ieee80211_is_auth(fc))
472 title = "Auth";
473 else if (ieee80211_is_deauth(fc))
474 title = "DeAuth";
475 else if (ieee80211_is_disassoc(fc))
476 title = "DisAssoc";
477 else
478 title = "Frame";
479
480 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
481 if (rate == -1)
482 rate = 0;
483 else
484 rate = iwl3945_rates[rate].ieee / 2;
485
486 /* print frame summary.
487 * MAC addresses show just the last byte (for brevity),
488 * but you can hack it to show more, if you'd like to. */
489 if (dataframe)
490 IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
491 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
492 title, le16_to_cpu(fc), header->addr1[5],
493 length, rssi, channel, rate);
494 else {
495 /* src/dst addresses assume managed mode */
496 IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
497 "src=0x%02x, rssi=%u, tim=%lu usec, "
498 "phy=0x%02x, chnl=%d\n",
499 title, le16_to_cpu(fc), header->addr1[5],
500 header->addr3[5], rssi,
501 tsf_low - priv->scan_start_tsf,
502 phy_flags, channel);
503 }
504 }
505 if (print_dump)
506 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
507 }
508
509 static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
510 struct iwl_rx_packet *pkt,
511 struct ieee80211_hdr *header, int group100)
512 {
513 if (iwl_get_debug_level(priv) & IWL_DL_RX)
514 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
515 }
516
517 #else
518 static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
519 struct iwl_rx_packet *pkt,
520 struct ieee80211_hdr *header, int group100)
521 {
522 }
523 #endif
524
525 /* This is necessary only for a number of statistics, see the caller. */
526 static int iwl3945_is_network_packet(struct iwl_priv *priv,
527 struct ieee80211_hdr *header)
528 {
529 /* Filter incoming packets to determine if they are targeted toward
530 * this network, discarding packets coming from ourselves */
531 switch (priv->iw_mode) {
532 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
533 /* packets to our IBSS update information */
534 return !compare_ether_addr(header->addr3, priv->bssid);
535 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
536 /* packets to our IBSS update information */
537 return !compare_ether_addr(header->addr2, priv->bssid);
538 default:
539 return 1;
540 }
541 }
542
543 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
544 struct iwl_rx_mem_buffer *rxb,
545 struct ieee80211_rx_status *stats)
546 {
547 struct iwl_rx_packet *pkt = rxb_addr(rxb);
548 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
549 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
550 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
551 u16 len = le16_to_cpu(rx_hdr->len);
552 struct sk_buff *skb;
553 int ret;
554
555 /* We received data from the HW, so stop the watchdog */
556 if (unlikely(len + IWL39_RX_FRAME_SIZE >
557 PAGE_SIZE << priv->hw_params.rx_page_order)) {
558 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
559 return;
560 }
561
562 /* We only process data packets if the interface is open */
563 if (unlikely(!priv->is_open)) {
564 IWL_DEBUG_DROP_LIMIT(priv,
565 "Dropping packet while interface is not open.\n");
566 return;
567 }
568
569 skb = alloc_skb(IWL_LINK_HDR_MAX, GFP_ATOMIC);
570 if (!skb) {
571 IWL_ERR(priv, "alloc_skb failed\n");
572 return;
573 }
574
575 if (!iwl3945_mod_params.sw_crypto)
576 iwl_set_decrypted_flag(priv,
577 (struct ieee80211_hdr *)rxb_addr(rxb),
578 le32_to_cpu(rx_end->status), stats);
579
580 skb_add_rx_frag(skb, 0, rxb->page,
581 (void *)rx_hdr->payload - (void *)pkt, len);
582
583 /* mac80211 currently doesn't support paged SKB. Convert it to
584 * linear SKB for management frame and data frame requires
585 * software decryption or software defragementation. */
586 if (ieee80211_is_mgmt(hdr->frame_control) ||
587 ieee80211_has_protected(hdr->frame_control) ||
588 ieee80211_has_morefrags(hdr->frame_control) ||
589 le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)
590 ret = skb_linearize(skb);
591 else
592 ret = __pskb_pull_tail(skb, min_t(u16, IWL_LINK_HDR_MAX, len)) ?
593 0 : -ENOMEM;
594
595 if (ret) {
596 kfree_skb(skb);
597 goto out;
598 }
599
600 iwl_update_stats(priv, false, hdr->frame_control, len);
601
602 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
603 ieee80211_rx(priv->hw, skb);
604
605 out:
606 priv->alloc_rxb_page--;
607 rxb->page = NULL;
608 }
609
610 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
611
612 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
613 struct iwl_rx_mem_buffer *rxb)
614 {
615 struct ieee80211_hdr *header;
616 struct ieee80211_rx_status rx_status;
617 struct iwl_rx_packet *pkt = rxb_addr(rxb);
618 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
619 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
620 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
621 int snr;
622 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
623 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
624 u8 network_packet;
625
626 rx_status.flag = 0;
627 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
628 rx_status.freq =
629 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
630 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
631 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
632
633 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
634 if (rx_status.band == IEEE80211_BAND_5GHZ)
635 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
636
637 rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
638 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
639
640 /* set the preamble flag if appropriate */
641 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
642 rx_status.flag |= RX_FLAG_SHORTPRE;
643
644 if ((unlikely(rx_stats->phy_count > 20))) {
645 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
646 rx_stats->phy_count);
647 return;
648 }
649
650 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
651 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
652 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
653 return;
654 }
655
656
657
658 /* Convert 3945's rssi indicator to dBm */
659 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
660
661 /* Set default noise value to -127 */
662 if (priv->last_rx_noise == 0)
663 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
664
665 /* 3945 provides noise info for OFDM frames only.
666 * sig_avg and noise_diff are measured by the 3945's digital signal
667 * processor (DSP), and indicate linear levels of signal level and
668 * distortion/noise within the packet preamble after
669 * automatic gain control (AGC). sig_avg should stay fairly
670 * constant if the radio's AGC is working well.
671 * Since these values are linear (not dB or dBm), linear
672 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
673 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
674 * to obtain noise level in dBm.
675 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
676 if (rx_stats_noise_diff) {
677 snr = rx_stats_sig_avg / rx_stats_noise_diff;
678 rx_status.noise = rx_status.signal -
679 iwl3945_calc_db_from_ratio(snr);
680 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
681 rx_status.noise);
682
683 /* If noise info not available, calculate signal quality indicator (%)
684 * using just the dBm signal level. */
685 } else {
686 rx_status.noise = priv->last_rx_noise;
687 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
688 }
689
690
691 IWL_DEBUG_STATS(priv, "Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
692 rx_status.signal, rx_status.noise, rx_status.qual,
693 rx_stats_sig_avg, rx_stats_noise_diff);
694
695 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
696
697 network_packet = iwl3945_is_network_packet(priv, header);
698
699 IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
700 network_packet ? '*' : ' ',
701 le16_to_cpu(rx_hdr->channel),
702 rx_status.signal, rx_status.signal,
703 rx_status.noise, rx_status.rate_idx);
704
705 /* Set "1" to report good data frames in groups of 100 */
706 iwl3945_dbg_report_frame(priv, pkt, header, 1);
707 iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
708
709 if (network_packet) {
710 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
711 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
712 priv->last_rx_rssi = rx_status.signal;
713 priv->last_rx_noise = rx_status.noise;
714 }
715
716 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
717 }
718
719 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
720 struct iwl_tx_queue *txq,
721 dma_addr_t addr, u16 len, u8 reset, u8 pad)
722 {
723 int count;
724 struct iwl_queue *q;
725 struct iwl3945_tfd *tfd, *tfd_tmp;
726
727 q = &txq->q;
728 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
729 tfd = &tfd_tmp[q->write_ptr];
730
731 if (reset)
732 memset(tfd, 0, sizeof(*tfd));
733
734 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
735
736 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
737 IWL_ERR(priv, "Error can not send more than %d chunks\n",
738 NUM_TFD_CHUNKS);
739 return -EINVAL;
740 }
741
742 tfd->tbs[count].addr = cpu_to_le32(addr);
743 tfd->tbs[count].len = cpu_to_le32(len);
744
745 count++;
746
747 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
748 TFD_CTL_PAD_SET(pad));
749
750 return 0;
751 }
752
753 /**
754 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
755 *
756 * Does NOT advance any indexes
757 */
758 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
759 {
760 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
761 int index = txq->q.read_ptr;
762 struct iwl3945_tfd *tfd = &tfd_tmp[index];
763 struct pci_dev *dev = priv->pci_dev;
764 int i;
765 int counter;
766
767 /* sanity check */
768 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
769 if (counter > NUM_TFD_CHUNKS) {
770 IWL_ERR(priv, "Too many chunks: %i\n", counter);
771 /* @todo issue fatal error, it is quite serious situation */
772 return;
773 }
774
775 /* Unmap tx_cmd */
776 if (counter)
777 pci_unmap_single(dev,
778 pci_unmap_addr(&txq->meta[index], mapping),
779 pci_unmap_len(&txq->meta[index], len),
780 PCI_DMA_TODEVICE);
781
782 /* unmap chunks if any */
783
784 for (i = 1; i < counter; i++) {
785 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
786 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
787 if (txq->txb[txq->q.read_ptr].skb[0]) {
788 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
789 if (txq->txb[txq->q.read_ptr].skb[0]) {
790 /* Can be called from interrupt context */
791 dev_kfree_skb_any(skb);
792 txq->txb[txq->q.read_ptr].skb[0] = NULL;
793 }
794 }
795 }
796 return ;
797 }
798
799 /**
800 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
801 *
802 */
803 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
804 struct iwl_device_cmd *cmd,
805 struct ieee80211_tx_info *info,
806 struct ieee80211_hdr *hdr,
807 int sta_id, int tx_id)
808 {
809 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
810 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
811 u16 rate_mask;
812 int rate;
813 u8 rts_retry_limit;
814 u8 data_retry_limit;
815 __le32 tx_flags;
816 __le16 fc = hdr->frame_control;
817 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
818
819 rate = iwl3945_rates[rate_index].plcp;
820 tx_flags = tx_cmd->tx_flags;
821
822 /* We need to figure out how to get the sta->supp_rates while
823 * in this running context */
824 rate_mask = IWL_RATES_MASK;
825
826
827 /* Set retry limit on DATA packets and Probe Responses*/
828 if (ieee80211_is_probe_resp(fc))
829 data_retry_limit = 3;
830 else
831 data_retry_limit = IWL_DEFAULT_TX_RETRY;
832 tx_cmd->data_retry_limit = data_retry_limit;
833
834 if (tx_id >= IWL_CMD_QUEUE_NUM)
835 rts_retry_limit = 3;
836 else
837 rts_retry_limit = 7;
838
839 if (data_retry_limit < rts_retry_limit)
840 rts_retry_limit = data_retry_limit;
841 tx_cmd->rts_retry_limit = rts_retry_limit;
842
843 if (ieee80211_is_mgmt(fc)) {
844 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
845 case cpu_to_le16(IEEE80211_STYPE_AUTH):
846 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
847 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
848 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
849 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
850 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
851 tx_flags |= TX_CMD_FLG_CTS_MSK;
852 }
853 break;
854 default:
855 break;
856 }
857 }
858
859 tx_cmd->rate = rate;
860 tx_cmd->tx_flags = tx_flags;
861
862 /* OFDM */
863 tx_cmd->supp_rates[0] =
864 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
865
866 /* CCK */
867 tx_cmd->supp_rates[1] = (rate_mask & 0xF);
868
869 IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
870 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
871 tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
872 tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
873 }
874
875 u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
876 {
877 unsigned long flags_spin;
878 struct iwl_station_entry *station;
879
880 if (sta_id == IWL_INVALID_STATION)
881 return IWL_INVALID_STATION;
882
883 spin_lock_irqsave(&priv->sta_lock, flags_spin);
884 station = &priv->stations[sta_id];
885
886 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
887 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
888 station->sta.mode = STA_CONTROL_MODIFY_MSK;
889
890 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
891
892 iwl_send_add_sta(priv, &station->sta, flags);
893 IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
894 sta_id, tx_rate);
895 return sta_id;
896 }
897
898 static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
899 {
900 if (src == IWL_PWR_SRC_VAUX) {
901 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
902 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
903 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
904 ~APMG_PS_CTRL_MSK_PWR_SRC);
905
906 iwl_poll_bit(priv, CSR_GPIO_IN,
907 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
908 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
909 }
910 } else {
911 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
912 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
913 ~APMG_PS_CTRL_MSK_PWR_SRC);
914
915 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
916 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
917 }
918
919 return 0;
920 }
921
922 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
923 {
924 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
925 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
926 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
927 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
928 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
929 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
930 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
931 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
932 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
933 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
934 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
935 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
936
937 /* fake read to flush all prev I/O */
938 iwl_read_direct32(priv, FH39_RSSR_CTRL);
939
940 return 0;
941 }
942
943 static int iwl3945_tx_reset(struct iwl_priv *priv)
944 {
945
946 /* bypass mode */
947 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
948
949 /* RA 0 is active */
950 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
951
952 /* all 6 fifo are active */
953 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
954
955 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
956 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
957 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
958 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
959
960 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
961 priv->shared_phys);
962
963 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
964 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
965 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
966 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
967 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
968 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
969 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
970 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
971
972
973 return 0;
974 }
975
976 /**
977 * iwl3945_txq_ctx_reset - Reset TX queue context
978 *
979 * Destroys all DMA structures and initialize them again
980 */
981 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
982 {
983 int rc;
984 int txq_id, slots_num;
985
986 iwl3945_hw_txq_ctx_free(priv);
987
988 /* allocate tx queue structure */
989 rc = iwl_alloc_txq_mem(priv);
990 if (rc)
991 return rc;
992
993 /* Tx CMD queue */
994 rc = iwl3945_tx_reset(priv);
995 if (rc)
996 goto error;
997
998 /* Tx queue(s) */
999 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1000 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1001 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1002 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1003 txq_id);
1004 if (rc) {
1005 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
1006 goto error;
1007 }
1008 }
1009
1010 return rc;
1011
1012 error:
1013 iwl3945_hw_txq_ctx_free(priv);
1014 return rc;
1015 }
1016
1017 /*
1018 * Start up NIC's basic functionality after it has been reset
1019 * (e.g. after platform boot, or shutdown via iwl3945_apm_stop())
1020 * NOTE: This does not load uCode nor start the embedded processor
1021 */
1022 static int iwl3945_apm_init(struct iwl_priv *priv)
1023 {
1024 int ret;
1025
1026 /* Configure chip clock phase-lock-loop */
1027 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR39_ANA_PLL_CFG_VAL);
1028
1029 /*
1030 * Disable L0S exit timer (platform NMI Work/Around)
1031 * (does this do anything on 3945, or just 4965 and beyond?)
1032 */
1033 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1034 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1035
1036 /* Disable L0s without affecting L1; don't wait for ICH (L0s bug W/A) */
1037 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1038 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1039
1040 /* Set FH wait threshold to maximum (HW error during stress W/A) */
1041 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
1042
1043 /*
1044 * Set "initialization complete" bit to move adapter from
1045 * D0U* --> D0A* (powered-up active) state.
1046 */
1047 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1048
1049 /*
1050 * Wait for clock stabilization; once stabilized, access to
1051 * device-internal resources is supported, e.g. iwl_write_prph()
1052 * and accesses to uCode SRAM.
1053 */
1054 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
1055 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1056 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1057 if (ret < 0) {
1058 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
1059 goto out;
1060 }
1061
1062 /* Enable DMA and BSM clocks, wait for them to stabilize */
1063 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1064 APMG_CLK_VAL_BSM_CLK_RQT);
1065 udelay(20);
1066
1067 /* Clear APMG (NIC's internal power management) interrupts */
1068 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1069 iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
1070
1071 /* Reset radio chip */
1072 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1073 udelay(5);
1074 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1075
1076 /* Disable L1-Active */
1077 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1078 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1079
1080 out:
1081 return ret;
1082 }
1083
1084 static void iwl3945_nic_config(struct iwl_priv *priv)
1085 {
1086 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1087 unsigned long flags;
1088 u8 rev_id = 0;
1089
1090 spin_lock_irqsave(&priv->lock, flags);
1091
1092 /* Determine HW type */
1093 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1094
1095 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1096
1097 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1098 IWL_DEBUG_INFO(priv, "RTP type \n");
1099 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1100 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
1101 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1102 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1103 } else {
1104 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
1105 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1106 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1107 }
1108
1109 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
1110 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
1111 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1112 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1113 } else
1114 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
1115
1116 if ((eeprom->board_revision & 0xF0) == 0xD0) {
1117 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1118 eeprom->board_revision);
1119 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1120 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1121 } else {
1122 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1123 eeprom->board_revision);
1124 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1125 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1126 }
1127
1128 if (eeprom->almgor_m_version <= 1) {
1129 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1130 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1131 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
1132 eeprom->almgor_m_version);
1133 } else {
1134 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
1135 eeprom->almgor_m_version);
1136 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1137 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1138 }
1139 spin_unlock_irqrestore(&priv->lock, flags);
1140
1141 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1142 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
1143
1144 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1145 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
1146 }
1147
1148 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1149 {
1150 int rc;
1151 unsigned long flags;
1152 struct iwl_rx_queue *rxq = &priv->rxq;
1153
1154 spin_lock_irqsave(&priv->lock, flags);
1155 priv->cfg->ops->lib->apm_ops.init(priv);
1156 spin_unlock_irqrestore(&priv->lock, flags);
1157
1158 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1159 if (rc)
1160 return rc;
1161
1162 priv->cfg->ops->lib->apm_ops.config(priv);
1163
1164 /* Allocate the RX queue, or reset if it is already allocated */
1165 if (!rxq->bd) {
1166 rc = iwl_rx_queue_alloc(priv);
1167 if (rc) {
1168 IWL_ERR(priv, "Unable to initialize Rx queue\n");
1169 return -ENOMEM;
1170 }
1171 } else
1172 iwl3945_rx_queue_reset(priv, rxq);
1173
1174 iwl3945_rx_replenish(priv);
1175
1176 iwl3945_rx_init(priv, rxq);
1177
1178
1179 /* Look at using this instead:
1180 rxq->need_update = 1;
1181 iwl_rx_queue_update_write_ptr(priv, rxq);
1182 */
1183
1184 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1185
1186 rc = iwl3945_txq_ctx_reset(priv);
1187 if (rc)
1188 return rc;
1189
1190 set_bit(STATUS_INIT, &priv->status);
1191
1192 return 0;
1193 }
1194
1195 /**
1196 * iwl3945_hw_txq_ctx_free - Free TXQ Context
1197 *
1198 * Destroy all TX DMA queues and structures
1199 */
1200 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1201 {
1202 int txq_id;
1203
1204 /* Tx queues */
1205 if (priv->txq)
1206 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1207 txq_id++)
1208 if (txq_id == IWL_CMD_QUEUE_NUM)
1209 iwl_cmd_queue_free(priv);
1210 else
1211 iwl_tx_queue_free(priv, txq_id);
1212
1213 /* free tx queue structure */
1214 iwl_free_txq_mem(priv);
1215 }
1216
1217 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1218 {
1219 int txq_id;
1220
1221 /* stop SCD */
1222 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1223
1224 /* reset TFD queues */
1225 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1226 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1227 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1228 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1229 1000);
1230 }
1231
1232 iwl3945_hw_txq_ctx_free(priv);
1233 }
1234
1235 /**
1236 * iwl3945_hw_reg_adjust_power_by_temp
1237 * return index delta into power gain settings table
1238 */
1239 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1240 {
1241 return (new_reading - old_reading) * (-11) / 100;
1242 }
1243
1244 /**
1245 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1246 */
1247 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1248 {
1249 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1250 }
1251
1252 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1253 {
1254 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1255 }
1256
1257 /**
1258 * iwl3945_hw_reg_txpower_get_temperature
1259 * get the current temperature by reading from NIC
1260 */
1261 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1262 {
1263 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1264 int temperature;
1265
1266 temperature = iwl3945_hw_get_temperature(priv);
1267
1268 /* driver's okay range is -260 to +25.
1269 * human readable okay range is 0 to +285 */
1270 IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1271
1272 /* handle insane temp reading */
1273 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1274 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
1275
1276 /* if really really hot(?),
1277 * substitute the 3rd band/group's temp measured at factory */
1278 if (priv->last_temperature > 100)
1279 temperature = eeprom->groups[2].temperature;
1280 else /* else use most recent "sane" value from driver */
1281 temperature = priv->last_temperature;
1282 }
1283
1284 return temperature; /* raw, not "human readable" */
1285 }
1286
1287 /* Adjust Txpower only if temperature variance is greater than threshold.
1288 *
1289 * Both are lower than older versions' 9 degrees */
1290 #define IWL_TEMPERATURE_LIMIT_TIMER 6
1291
1292 /**
1293 * is_temp_calib_needed - determines if new calibration is needed
1294 *
1295 * records new temperature in tx_mgr->temperature.
1296 * replaces tx_mgr->last_temperature *only* if calib needed
1297 * (assumes caller will actually do the calibration!). */
1298 static int is_temp_calib_needed(struct iwl_priv *priv)
1299 {
1300 int temp_diff;
1301
1302 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1303 temp_diff = priv->temperature - priv->last_temperature;
1304
1305 /* get absolute value */
1306 if (temp_diff < 0) {
1307 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1308 temp_diff = -temp_diff;
1309 } else if (temp_diff == 0)
1310 IWL_DEBUG_POWER(priv, "Same temp,\n");
1311 else
1312 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1313
1314 /* if we don't need calibration, *don't* update last_temperature */
1315 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1316 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1317 return 0;
1318 }
1319
1320 IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1321
1322 /* assume that caller will actually do calib ...
1323 * update the "last temperature" value */
1324 priv->last_temperature = priv->temperature;
1325 return 1;
1326 }
1327
1328 #define IWL_MAX_GAIN_ENTRIES 78
1329 #define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1330 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1331
1332 /* radio and DSP power table, each step is 1/2 dB.
1333 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1334 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1335 {
1336 {251, 127}, /* 2.4 GHz, highest power */
1337 {251, 127},
1338 {251, 127},
1339 {251, 127},
1340 {251, 125},
1341 {251, 110},
1342 {251, 105},
1343 {251, 98},
1344 {187, 125},
1345 {187, 115},
1346 {187, 108},
1347 {187, 99},
1348 {243, 119},
1349 {243, 111},
1350 {243, 105},
1351 {243, 97},
1352 {243, 92},
1353 {211, 106},
1354 {211, 100},
1355 {179, 120},
1356 {179, 113},
1357 {179, 107},
1358 {147, 125},
1359 {147, 119},
1360 {147, 112},
1361 {147, 106},
1362 {147, 101},
1363 {147, 97},
1364 {147, 91},
1365 {115, 107},
1366 {235, 121},
1367 {235, 115},
1368 {235, 109},
1369 {203, 127},
1370 {203, 121},
1371 {203, 115},
1372 {203, 108},
1373 {203, 102},
1374 {203, 96},
1375 {203, 92},
1376 {171, 110},
1377 {171, 104},
1378 {171, 98},
1379 {139, 116},
1380 {227, 125},
1381 {227, 119},
1382 {227, 113},
1383 {227, 107},
1384 {227, 101},
1385 {227, 96},
1386 {195, 113},
1387 {195, 106},
1388 {195, 102},
1389 {195, 95},
1390 {163, 113},
1391 {163, 106},
1392 {163, 102},
1393 {163, 95},
1394 {131, 113},
1395 {131, 106},
1396 {131, 102},
1397 {131, 95},
1398 {99, 113},
1399 {99, 106},
1400 {99, 102},
1401 {99, 95},
1402 {67, 113},
1403 {67, 106},
1404 {67, 102},
1405 {67, 95},
1406 {35, 113},
1407 {35, 106},
1408 {35, 102},
1409 {35, 95},
1410 {3, 113},
1411 {3, 106},
1412 {3, 102},
1413 {3, 95} }, /* 2.4 GHz, lowest power */
1414 {
1415 {251, 127}, /* 5.x GHz, highest power */
1416 {251, 120},
1417 {251, 114},
1418 {219, 119},
1419 {219, 101},
1420 {187, 113},
1421 {187, 102},
1422 {155, 114},
1423 {155, 103},
1424 {123, 117},
1425 {123, 107},
1426 {123, 99},
1427 {123, 92},
1428 {91, 108},
1429 {59, 125},
1430 {59, 118},
1431 {59, 109},
1432 {59, 102},
1433 {59, 96},
1434 {59, 90},
1435 {27, 104},
1436 {27, 98},
1437 {27, 92},
1438 {115, 118},
1439 {115, 111},
1440 {115, 104},
1441 {83, 126},
1442 {83, 121},
1443 {83, 113},
1444 {83, 105},
1445 {83, 99},
1446 {51, 118},
1447 {51, 111},
1448 {51, 104},
1449 {51, 98},
1450 {19, 116},
1451 {19, 109},
1452 {19, 102},
1453 {19, 98},
1454 {19, 93},
1455 {171, 113},
1456 {171, 107},
1457 {171, 99},
1458 {139, 120},
1459 {139, 113},
1460 {139, 107},
1461 {139, 99},
1462 {107, 120},
1463 {107, 113},
1464 {107, 107},
1465 {107, 99},
1466 {75, 120},
1467 {75, 113},
1468 {75, 107},
1469 {75, 99},
1470 {43, 120},
1471 {43, 113},
1472 {43, 107},
1473 {43, 99},
1474 {11, 120},
1475 {11, 113},
1476 {11, 107},
1477 {11, 99},
1478 {131, 107},
1479 {131, 99},
1480 {99, 120},
1481 {99, 113},
1482 {99, 107},
1483 {99, 99},
1484 {67, 120},
1485 {67, 113},
1486 {67, 107},
1487 {67, 99},
1488 {35, 120},
1489 {35, 113},
1490 {35, 107},
1491 {35, 99},
1492 {3, 120} } /* 5.x GHz, lowest power */
1493 };
1494
1495 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1496 {
1497 if (index < 0)
1498 return 0;
1499 if (index >= IWL_MAX_GAIN_ENTRIES)
1500 return IWL_MAX_GAIN_ENTRIES - 1;
1501 return (u8) index;
1502 }
1503
1504 /* Kick off thermal recalibration check every 60 seconds */
1505 #define REG_RECALIB_PERIOD (60)
1506
1507 /**
1508 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1509 *
1510 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1511 * or 6 Mbit (OFDM) rates.
1512 */
1513 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1514 s32 rate_index, const s8 *clip_pwrs,
1515 struct iwl_channel_info *ch_info,
1516 int band_index)
1517 {
1518 struct iwl3945_scan_power_info *scan_power_info;
1519 s8 power;
1520 u8 power_index;
1521
1522 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1523
1524 /* use this channel group's 6Mbit clipping/saturation pwr,
1525 * but cap at regulatory scan power restriction (set during init
1526 * based on eeprom channel data) for this channel. */
1527 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1528
1529 /* further limit to user's max power preference.
1530 * FIXME: Other spectrum management power limitations do not
1531 * seem to apply?? */
1532 power = min(power, priv->tx_power_user_lmt);
1533 scan_power_info->requested_power = power;
1534
1535 /* find difference between new scan *power* and current "normal"
1536 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1537 * current "normal" temperature-compensated Tx power *index* for
1538 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1539 * *index*. */
1540 power_index = ch_info->power_info[rate_index].power_table_index
1541 - (power - ch_info->power_info
1542 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1543
1544 /* store reference index that we use when adjusting *all* scan
1545 * powers. So we can accommodate user (all channel) or spectrum
1546 * management (single channel) power changes "between" temperature
1547 * feedback compensation procedures.
1548 * don't force fit this reference index into gain table; it may be a
1549 * negative number. This will help avoid errors when we're at
1550 * the lower bounds (highest gains, for warmest temperatures)
1551 * of the table. */
1552
1553 /* don't exceed table bounds for "real" setting */
1554 power_index = iwl3945_hw_reg_fix_power_index(power_index);
1555
1556 scan_power_info->power_table_index = power_index;
1557 scan_power_info->tpc.tx_gain =
1558 power_gain_table[band_index][power_index].tx_gain;
1559 scan_power_info->tpc.dsp_atten =
1560 power_gain_table[band_index][power_index].dsp_atten;
1561 }
1562
1563 /**
1564 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1565 *
1566 * Configures power settings for all rates for the current channel,
1567 * using values from channel info struct, and send to NIC
1568 */
1569 static int iwl3945_send_tx_power(struct iwl_priv *priv)
1570 {
1571 int rate_idx, i;
1572 const struct iwl_channel_info *ch_info = NULL;
1573 struct iwl3945_txpowertable_cmd txpower = {
1574 .channel = priv->active_rxon.channel,
1575 };
1576
1577 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1578 ch_info = iwl_get_channel_info(priv,
1579 priv->band,
1580 le16_to_cpu(priv->active_rxon.channel));
1581 if (!ch_info) {
1582 IWL_ERR(priv,
1583 "Failed to get channel info for channel %d [%d]\n",
1584 le16_to_cpu(priv->active_rxon.channel), priv->band);
1585 return -EINVAL;
1586 }
1587
1588 if (!is_channel_valid(ch_info)) {
1589 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1590 "non-Tx channel.\n");
1591 return 0;
1592 }
1593
1594 /* fill cmd with power settings for all rates for current channel */
1595 /* Fill OFDM rate */
1596 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1597 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1598
1599 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1600 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1601
1602 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1603 le16_to_cpu(txpower.channel),
1604 txpower.band,
1605 txpower.power[i].tpc.tx_gain,
1606 txpower.power[i].tpc.dsp_atten,
1607 txpower.power[i].rate);
1608 }
1609 /* Fill CCK rates */
1610 for (rate_idx = IWL_FIRST_CCK_RATE;
1611 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1612 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1613 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1614
1615 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1616 le16_to_cpu(txpower.channel),
1617 txpower.band,
1618 txpower.power[i].tpc.tx_gain,
1619 txpower.power[i].tpc.dsp_atten,
1620 txpower.power[i].rate);
1621 }
1622
1623 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1624 sizeof(struct iwl3945_txpowertable_cmd),
1625 &txpower);
1626
1627 }
1628
1629 /**
1630 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1631 * @ch_info: Channel to update. Uses power_info.requested_power.
1632 *
1633 * Replace requested_power and base_power_index ch_info fields for
1634 * one channel.
1635 *
1636 * Called if user or spectrum management changes power preferences.
1637 * Takes into account h/w and modulation limitations (clip power).
1638 *
1639 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1640 *
1641 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1642 * properly fill out the scan powers, and actual h/w gain settings,
1643 * and send changes to NIC
1644 */
1645 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1646 struct iwl_channel_info *ch_info)
1647 {
1648 struct iwl3945_channel_power_info *power_info;
1649 int power_changed = 0;
1650 int i;
1651 const s8 *clip_pwrs;
1652 int power;
1653
1654 /* Get this chnlgrp's rate-to-max/clip-powers table */
1655 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1656
1657 /* Get this channel's rate-to-current-power settings table */
1658 power_info = ch_info->power_info;
1659
1660 /* update OFDM Txpower settings */
1661 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1662 i++, ++power_info) {
1663 int delta_idx;
1664
1665 /* limit new power to be no more than h/w capability */
1666 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1667 if (power == power_info->requested_power)
1668 continue;
1669
1670 /* find difference between old and new requested powers,
1671 * update base (non-temp-compensated) power index */
1672 delta_idx = (power - power_info->requested_power) * 2;
1673 power_info->base_power_index -= delta_idx;
1674
1675 /* save new requested power value */
1676 power_info->requested_power = power;
1677
1678 power_changed = 1;
1679 }
1680
1681 /* update CCK Txpower settings, based on OFDM 12M setting ...
1682 * ... all CCK power settings for a given channel are the *same*. */
1683 if (power_changed) {
1684 power =
1685 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1686 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1687
1688 /* do all CCK rates' iwl3945_channel_power_info structures */
1689 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1690 power_info->requested_power = power;
1691 power_info->base_power_index =
1692 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1693 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1694 ++power_info;
1695 }
1696 }
1697
1698 return 0;
1699 }
1700
1701 /**
1702 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1703 *
1704 * NOTE: Returned power limit may be less (but not more) than requested,
1705 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1706 * (no consideration for h/w clipping limitations).
1707 */
1708 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1709 {
1710 s8 max_power;
1711
1712 #if 0
1713 /* if we're using TGd limits, use lower of TGd or EEPROM */
1714 if (ch_info->tgd_data.max_power != 0)
1715 max_power = min(ch_info->tgd_data.max_power,
1716 ch_info->eeprom.max_power_avg);
1717
1718 /* else just use EEPROM limits */
1719 else
1720 #endif
1721 max_power = ch_info->eeprom.max_power_avg;
1722
1723 return min(max_power, ch_info->max_power_avg);
1724 }
1725
1726 /**
1727 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1728 *
1729 * Compensate txpower settings of *all* channels for temperature.
1730 * This only accounts for the difference between current temperature
1731 * and the factory calibration temperatures, and bases the new settings
1732 * on the channel's base_power_index.
1733 *
1734 * If RxOn is "associated", this sends the new Txpower to NIC!
1735 */
1736 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1737 {
1738 struct iwl_channel_info *ch_info = NULL;
1739 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1740 int delta_index;
1741 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1742 u8 a_band;
1743 u8 rate_index;
1744 u8 scan_tbl_index;
1745 u8 i;
1746 int ref_temp;
1747 int temperature = priv->temperature;
1748
1749 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1750 for (i = 0; i < priv->channel_count; i++) {
1751 ch_info = &priv->channel_info[i];
1752 a_band = is_channel_a_band(ch_info);
1753
1754 /* Get this chnlgrp's factory calibration temperature */
1755 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1756 temperature;
1757
1758 /* get power index adjustment based on current and factory
1759 * temps */
1760 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1761 ref_temp);
1762
1763 /* set tx power value for all rates, OFDM and CCK */
1764 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1765 rate_index++) {
1766 int power_idx =
1767 ch_info->power_info[rate_index].base_power_index;
1768
1769 /* temperature compensate */
1770 power_idx += delta_index;
1771
1772 /* stay within table range */
1773 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1774 ch_info->power_info[rate_index].
1775 power_table_index = (u8) power_idx;
1776 ch_info->power_info[rate_index].tpc =
1777 power_gain_table[a_band][power_idx];
1778 }
1779
1780 /* Get this chnlgrp's rate-to-max/clip-powers table */
1781 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1782
1783 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1784 for (scan_tbl_index = 0;
1785 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1786 s32 actual_index = (scan_tbl_index == 0) ?
1787 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1788 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1789 actual_index, clip_pwrs,
1790 ch_info, a_band);
1791 }
1792 }
1793
1794 /* send Txpower command for current channel to ucode */
1795 return priv->cfg->ops->lib->send_tx_power(priv);
1796 }
1797
1798 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1799 {
1800 struct iwl_channel_info *ch_info;
1801 s8 max_power;
1802 u8 a_band;
1803 u8 i;
1804
1805 if (priv->tx_power_user_lmt == power) {
1806 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1807 "limit: %ddBm.\n", power);
1808 return 0;
1809 }
1810
1811 IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1812 priv->tx_power_user_lmt = power;
1813
1814 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1815
1816 for (i = 0; i < priv->channel_count; i++) {
1817 ch_info = &priv->channel_info[i];
1818 a_band = is_channel_a_band(ch_info);
1819
1820 /* find minimum power of all user and regulatory constraints
1821 * (does not consider h/w clipping limitations) */
1822 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1823 max_power = min(power, max_power);
1824 if (max_power != ch_info->curr_txpow) {
1825 ch_info->curr_txpow = max_power;
1826
1827 /* this considers the h/w clipping limitations */
1828 iwl3945_hw_reg_set_new_power(priv, ch_info);
1829 }
1830 }
1831
1832 /* update txpower settings for all channels,
1833 * send to NIC if associated. */
1834 is_temp_calib_needed(priv);
1835 iwl3945_hw_reg_comp_txpower_temp(priv);
1836
1837 return 0;
1838 }
1839
1840 static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1841 {
1842 int rc = 0;
1843 struct iwl_rx_packet *pkt;
1844 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1845 struct iwl_host_cmd cmd = {
1846 .id = REPLY_RXON_ASSOC,
1847 .len = sizeof(rxon_assoc),
1848 .flags = CMD_WANT_SKB,
1849 .data = &rxon_assoc,
1850 };
1851 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1852 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1853
1854 if ((rxon1->flags == rxon2->flags) &&
1855 (rxon1->filter_flags == rxon2->filter_flags) &&
1856 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1857 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1858 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1859 return 0;
1860 }
1861
1862 rxon_assoc.flags = priv->staging_rxon.flags;
1863 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1864 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1865 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1866 rxon_assoc.reserved = 0;
1867
1868 rc = iwl_send_cmd_sync(priv, &cmd);
1869 if (rc)
1870 return rc;
1871
1872 pkt = (struct iwl_rx_packet *)cmd.reply_page;
1873 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
1874 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1875 rc = -EIO;
1876 }
1877
1878 priv->alloc_rxb_page--;
1879 free_pages(cmd.reply_page, priv->hw_params.rx_page_order);
1880
1881 return rc;
1882 }
1883
1884 /**
1885 * iwl3945_commit_rxon - commit staging_rxon to hardware
1886 *
1887 * The RXON command in staging_rxon is committed to the hardware and
1888 * the active_rxon structure is updated with the new data. This
1889 * function correctly transitions out of the RXON_ASSOC_MSK state if
1890 * a HW tune is required based on the RXON structure changes.
1891 */
1892 static int iwl3945_commit_rxon(struct iwl_priv *priv)
1893 {
1894 /* cast away the const for active_rxon in this function */
1895 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1896 struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1897 int rc = 0;
1898 bool new_assoc =
1899 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1900
1901 if (!iwl_is_alive(priv))
1902 return -1;
1903
1904 /* always get timestamp with Rx frame */
1905 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1906
1907 /* select antenna */
1908 staging_rxon->flags &=
1909 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1910 staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1911
1912 rc = iwl_check_rxon_cmd(priv);
1913 if (rc) {
1914 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
1915 return -EINVAL;
1916 }
1917
1918 /* If we don't need to send a full RXON, we can use
1919 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1920 * and other flags for the current radio configuration. */
1921 if (!iwl_full_rxon_required(priv)) {
1922 rc = iwl_send_rxon_assoc(priv);
1923 if (rc) {
1924 IWL_ERR(priv, "Error setting RXON_ASSOC "
1925 "configuration (%d).\n", rc);
1926 return rc;
1927 }
1928
1929 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1930
1931 return 0;
1932 }
1933
1934 /* If we are currently associated and the new config requires
1935 * an RXON_ASSOC and the new config wants the associated mask enabled,
1936 * we must clear the associated from the active configuration
1937 * before we apply the new config */
1938 if (iwl_is_associated(priv) && new_assoc) {
1939 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1940 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1941
1942 /*
1943 * reserved4 and 5 could have been filled by the iwlcore code.
1944 * Let's clear them before pushing to the 3945.
1945 */
1946 active_rxon->reserved4 = 0;
1947 active_rxon->reserved5 = 0;
1948 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1949 sizeof(struct iwl3945_rxon_cmd),
1950 &priv->active_rxon);
1951
1952 /* If the mask clearing failed then we set
1953 * active_rxon back to what it was previously */
1954 if (rc) {
1955 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1956 IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1957 "configuration (%d).\n", rc);
1958 return rc;
1959 }
1960 }
1961
1962 IWL_DEBUG_INFO(priv, "Sending RXON\n"
1963 "* with%s RXON_FILTER_ASSOC_MSK\n"
1964 "* channel = %d\n"
1965 "* bssid = %pM\n",
1966 (new_assoc ? "" : "out"),
1967 le16_to_cpu(staging_rxon->channel),
1968 staging_rxon->bssid_addr);
1969
1970 /*
1971 * reserved4 and 5 could have been filled by the iwlcore code.
1972 * Let's clear them before pushing to the 3945.
1973 */
1974 staging_rxon->reserved4 = 0;
1975 staging_rxon->reserved5 = 0;
1976
1977 iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
1978
1979 /* Apply the new configuration */
1980 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1981 sizeof(struct iwl3945_rxon_cmd),
1982 staging_rxon);
1983 if (rc) {
1984 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1985 return rc;
1986 }
1987
1988 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1989
1990 iwl_clear_stations_table(priv);
1991
1992 /* If we issue a new RXON command which required a tune then we must
1993 * send a new TXPOWER command or we won't be able to Tx any frames */
1994 rc = priv->cfg->ops->lib->send_tx_power(priv);
1995 if (rc) {
1996 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1997 return rc;
1998 }
1999
2000 /* Add the broadcast address so we can send broadcast frames */
2001 if (iwl_add_station(priv, iwl_bcast_addr, false, CMD_SYNC, NULL) ==
2002 IWL_INVALID_STATION) {
2003 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
2004 return -EIO;
2005 }
2006
2007 /* If we have set the ASSOC_MSK and we are in BSS mode then
2008 * add the IWL_AP_ID to the station rate table */
2009 if (iwl_is_associated(priv) &&
2010 (priv->iw_mode == NL80211_IFTYPE_STATION))
2011 if (iwl_add_station(priv, priv->active_rxon.bssid_addr,
2012 true, CMD_SYNC, NULL) == IWL_INVALID_STATION) {
2013 IWL_ERR(priv, "Error adding AP address for transmit\n");
2014 return -EIO;
2015 }
2016
2017 /* Init the hardware's rate fallback order based on the band */
2018 rc = iwl3945_init_hw_rate_table(priv);
2019 if (rc) {
2020 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
2021 return -EIO;
2022 }
2023
2024 return 0;
2025 }
2026
2027 /* will add 3945 channel switch cmd handling later */
2028 int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
2029 {
2030 return 0;
2031 }
2032
2033 /**
2034 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
2035 *
2036 * -- reset periodic timer
2037 * -- see if temp has changed enough to warrant re-calibration ... if so:
2038 * -- correct coeffs for temp (can reset temp timer)
2039 * -- save this temp as "last",
2040 * -- send new set of gain settings to NIC
2041 * NOTE: This should continue working, even when we're not associated,
2042 * so we can keep our internal table of scan powers current. */
2043 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
2044 {
2045 /* This will kick in the "brute force"
2046 * iwl3945_hw_reg_comp_txpower_temp() below */
2047 if (!is_temp_calib_needed(priv))
2048 goto reschedule;
2049
2050 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2051 * This is based *only* on current temperature,
2052 * ignoring any previous power measurements */
2053 iwl3945_hw_reg_comp_txpower_temp(priv);
2054
2055 reschedule:
2056 queue_delayed_work(priv->workqueue,
2057 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2058 }
2059
2060 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
2061 {
2062 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2063 thermal_periodic.work);
2064
2065 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2066 return;
2067
2068 mutex_lock(&priv->mutex);
2069 iwl3945_reg_txpower_periodic(priv);
2070 mutex_unlock(&priv->mutex);
2071 }
2072
2073 /**
2074 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
2075 * for the channel.
2076 *
2077 * This function is used when initializing channel-info structs.
2078 *
2079 * NOTE: These channel groups do *NOT* match the bands above!
2080 * These channel groups are based on factory-tested channels;
2081 * on A-band, EEPROM's "group frequency" entries represent the top
2082 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2083 */
2084 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
2085 const struct iwl_channel_info *ch_info)
2086 {
2087 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2088 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
2089 u8 group;
2090 u16 group_index = 0; /* based on factory calib frequencies */
2091 u8 grp_channel;
2092
2093 /* Find the group index for the channel ... don't use index 1(?) */
2094 if (is_channel_a_band(ch_info)) {
2095 for (group = 1; group < 5; group++) {
2096 grp_channel = ch_grp[group].group_channel;
2097 if (ch_info->channel <= grp_channel) {
2098 group_index = group;
2099 break;
2100 }
2101 }
2102 /* group 4 has a few channels *above* its factory cal freq */
2103 if (group == 5)
2104 group_index = 4;
2105 } else
2106 group_index = 0; /* 2.4 GHz, group 0 */
2107
2108 IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
2109 group_index);
2110 return group_index;
2111 }
2112
2113 /**
2114 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2115 *
2116 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2117 * into radio/DSP gain settings table for requested power.
2118 */
2119 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
2120 s8 requested_power,
2121 s32 setting_index, s32 *new_index)
2122 {
2123 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2124 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2125 s32 index0, index1;
2126 s32 power = 2 * requested_power;
2127 s32 i;
2128 const struct iwl3945_eeprom_txpower_sample *samples;
2129 s32 gains0, gains1;
2130 s32 res;
2131 s32 denominator;
2132
2133 chnl_grp = &eeprom->groups[setting_index];
2134 samples = chnl_grp->samples;
2135 for (i = 0; i < 5; i++) {
2136 if (power == samples[i].power) {
2137 *new_index = samples[i].gain_index;
2138 return 0;
2139 }
2140 }
2141
2142 if (power > samples[1].power) {
2143 index0 = 0;
2144 index1 = 1;
2145 } else if (power > samples[2].power) {
2146 index0 = 1;
2147 index1 = 2;
2148 } else if (power > samples[3].power) {
2149 index0 = 2;
2150 index1 = 3;
2151 } else {
2152 index0 = 3;
2153 index1 = 4;
2154 }
2155
2156 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2157 if (denominator == 0)
2158 return -EINVAL;
2159 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2160 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2161 res = gains0 + (gains1 - gains0) *
2162 ((s32) power - (s32) samples[index0].power) / denominator +
2163 (1 << 18);
2164 *new_index = res >> 19;
2165 return 0;
2166 }
2167
2168 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2169 {
2170 u32 i;
2171 s32 rate_index;
2172 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2173 const struct iwl3945_eeprom_txpower_group *group;
2174
2175 IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
2176
2177 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2178 s8 *clip_pwrs; /* table of power levels for each rate */
2179 s8 satur_pwr; /* saturation power for each chnl group */
2180 group = &eeprom->groups[i];
2181
2182 /* sanity check on factory saturation power value */
2183 if (group->saturation_power < 40) {
2184 IWL_WARN(priv, "Error: saturation power is %d, "
2185 "less than minimum expected 40\n",
2186 group->saturation_power);
2187 return;
2188 }
2189
2190 /*
2191 * Derive requested power levels for each rate, based on
2192 * hardware capabilities (saturation power for band).
2193 * Basic value is 3dB down from saturation, with further
2194 * power reductions for highest 3 data rates. These
2195 * backoffs provide headroom for high rate modulation
2196 * power peaks, without too much distortion (clipping).
2197 */
2198 /* we'll fill in this array with h/w max power levels */
2199 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
2200
2201 /* divide factory saturation power by 2 to find -3dB level */
2202 satur_pwr = (s8) (group->saturation_power >> 1);
2203
2204 /* fill in channel group's nominal powers for each rate */
2205 for (rate_index = 0;
2206 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2207 switch (rate_index) {
2208 case IWL_RATE_36M_INDEX_TABLE:
2209 if (i == 0) /* B/G */
2210 *clip_pwrs = satur_pwr;
2211 else /* A */
2212 *clip_pwrs = satur_pwr - 5;
2213 break;
2214 case IWL_RATE_48M_INDEX_TABLE:
2215 if (i == 0)
2216 *clip_pwrs = satur_pwr - 7;
2217 else
2218 *clip_pwrs = satur_pwr - 10;
2219 break;
2220 case IWL_RATE_54M_INDEX_TABLE:
2221 if (i == 0)
2222 *clip_pwrs = satur_pwr - 9;
2223 else
2224 *clip_pwrs = satur_pwr - 12;
2225 break;
2226 default:
2227 *clip_pwrs = satur_pwr;
2228 break;
2229 }
2230 }
2231 }
2232 }
2233
2234 /**
2235 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2236 *
2237 * Second pass (during init) to set up priv->channel_info
2238 *
2239 * Set up Tx-power settings in our channel info database for each VALID
2240 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2241 * and current temperature.
2242 *
2243 * Since this is based on current temperature (at init time), these values may
2244 * not be valid for very long, but it gives us a starting/default point,
2245 * and allows us to active (i.e. using Tx) scan.
2246 *
2247 * This does *not* write values to NIC, just sets up our internal table.
2248 */
2249 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2250 {
2251 struct iwl_channel_info *ch_info = NULL;
2252 struct iwl3945_channel_power_info *pwr_info;
2253 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2254 int delta_index;
2255 u8 rate_index;
2256 u8 scan_tbl_index;
2257 const s8 *clip_pwrs; /* array of power levels for each rate */
2258 u8 gain, dsp_atten;
2259 s8 power;
2260 u8 pwr_index, base_pwr_index, a_band;
2261 u8 i;
2262 int temperature;
2263
2264 /* save temperature reference,
2265 * so we can determine next time to calibrate */
2266 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2267 priv->last_temperature = temperature;
2268
2269 iwl3945_hw_reg_init_channel_groups(priv);
2270
2271 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2272 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2273 i++, ch_info++) {
2274 a_band = is_channel_a_band(ch_info);
2275 if (!is_channel_valid(ch_info))
2276 continue;
2277
2278 /* find this channel's channel group (*not* "band") index */
2279 ch_info->group_index =
2280 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2281
2282 /* Get this chnlgrp's rate->max/clip-powers table */
2283 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
2284
2285 /* calculate power index *adjustment* value according to
2286 * diff between current temperature and factory temperature */
2287 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2288 eeprom->groups[ch_info->group_index].
2289 temperature);
2290
2291 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2292 ch_info->channel, delta_index, temperature +
2293 IWL_TEMP_CONVERT);
2294
2295 /* set tx power value for all OFDM rates */
2296 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2297 rate_index++) {
2298 s32 uninitialized_var(power_idx);
2299 int rc;
2300
2301 /* use channel group's clip-power table,
2302 * but don't exceed channel's max power */
2303 s8 pwr = min(ch_info->max_power_avg,
2304 clip_pwrs[rate_index]);
2305
2306 pwr_info = &ch_info->power_info[rate_index];
2307
2308 /* get base (i.e. at factory-measured temperature)
2309 * power table index for this rate's power */
2310 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2311 ch_info->group_index,
2312 &power_idx);
2313 if (rc) {
2314 IWL_ERR(priv, "Invalid power index\n");
2315 return rc;
2316 }
2317 pwr_info->base_power_index = (u8) power_idx;
2318
2319 /* temperature compensate */
2320 power_idx += delta_index;
2321
2322 /* stay within range of gain table */
2323 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2324
2325 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2326 pwr_info->requested_power = pwr;
2327 pwr_info->power_table_index = (u8) power_idx;
2328 pwr_info->tpc.tx_gain =
2329 power_gain_table[a_band][power_idx].tx_gain;
2330 pwr_info->tpc.dsp_atten =
2331 power_gain_table[a_band][power_idx].dsp_atten;
2332 }
2333
2334 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2335 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2336 power = pwr_info->requested_power +
2337 IWL_CCK_FROM_OFDM_POWER_DIFF;
2338 pwr_index = pwr_info->power_table_index +
2339 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2340 base_pwr_index = pwr_info->base_power_index +
2341 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2342
2343 /* stay within table range */
2344 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2345 gain = power_gain_table[a_band][pwr_index].tx_gain;
2346 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2347
2348 /* fill each CCK rate's iwl3945_channel_power_info structure
2349 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2350 * NOTE: CCK rates start at end of OFDM rates! */
2351 for (rate_index = 0;
2352 rate_index < IWL_CCK_RATES; rate_index++) {
2353 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2354 pwr_info->requested_power = power;
2355 pwr_info->power_table_index = pwr_index;
2356 pwr_info->base_power_index = base_pwr_index;
2357 pwr_info->tpc.tx_gain = gain;
2358 pwr_info->tpc.dsp_atten = dsp_atten;
2359 }
2360
2361 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2362 for (scan_tbl_index = 0;
2363 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2364 s32 actual_index = (scan_tbl_index == 0) ?
2365 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2366 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2367 actual_index, clip_pwrs, ch_info, a_band);
2368 }
2369 }
2370
2371 return 0;
2372 }
2373
2374 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2375 {
2376 int rc;
2377
2378 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2379 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2380 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2381 if (rc < 0)
2382 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2383
2384 return 0;
2385 }
2386
2387 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2388 {
2389 int txq_id = txq->q.id;
2390
2391 struct iwl3945_shared *shared_data = priv->shared_virt;
2392
2393 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2394
2395 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2396 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2397
2398 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2399 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2400 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2401 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2402 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2403 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2404
2405 /* fake read to flush all prev. writes */
2406 iwl_read32(priv, FH39_TSSR_CBB_BASE);
2407
2408 return 0;
2409 }
2410
2411 /*
2412 * HCMD utils
2413 */
2414 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2415 {
2416 switch (cmd_id) {
2417 case REPLY_RXON:
2418 return sizeof(struct iwl3945_rxon_cmd);
2419 case POWER_TABLE_CMD:
2420 return sizeof(struct iwl3945_powertable_cmd);
2421 default:
2422 return len;
2423 }
2424 }
2425
2426
2427 static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2428 {
2429 struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2430 addsta->mode = cmd->mode;
2431 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2432 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2433 addsta->station_flags = cmd->station_flags;
2434 addsta->station_flags_msk = cmd->station_flags_msk;
2435 addsta->tid_disable_tx = cpu_to_le16(0);
2436 addsta->rate_n_flags = cmd->rate_n_flags;
2437 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2438 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2439 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2440
2441 return (u16)sizeof(struct iwl3945_addsta_cmd);
2442 }
2443
2444
2445 /**
2446 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2447 */
2448 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2449 {
2450 int rc, i, index, prev_index;
2451 struct iwl3945_rate_scaling_cmd rate_cmd = {
2452 .reserved = {0, 0, 0},
2453 };
2454 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2455
2456 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2457 index = iwl3945_rates[i].table_rs_index;
2458
2459 table[index].rate_n_flags =
2460 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2461 table[index].try_cnt = priv->retry_rate;
2462 prev_index = iwl3945_get_prev_ieee_rate(i);
2463 table[index].next_rate_index =
2464 iwl3945_rates[prev_index].table_rs_index;
2465 }
2466
2467 switch (priv->band) {
2468 case IEEE80211_BAND_5GHZ:
2469 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2470 /* If one of the following CCK rates is used,
2471 * have it fall back to the 6M OFDM rate */
2472 for (i = IWL_RATE_1M_INDEX_TABLE;
2473 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2474 table[i].next_rate_index =
2475 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2476
2477 /* Don't fall back to CCK rates */
2478 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2479 IWL_RATE_9M_INDEX_TABLE;
2480
2481 /* Don't drop out of OFDM rates */
2482 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2483 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2484 break;
2485
2486 case IEEE80211_BAND_2GHZ:
2487 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2488 /* If an OFDM rate is used, have it fall back to the
2489 * 1M CCK rates */
2490
2491 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2492 iwl_is_associated(priv)) {
2493
2494 index = IWL_FIRST_CCK_RATE;
2495 for (i = IWL_RATE_6M_INDEX_TABLE;
2496 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2497 table[i].next_rate_index =
2498 iwl3945_rates[index].table_rs_index;
2499
2500 index = IWL_RATE_11M_INDEX_TABLE;
2501 /* CCK shouldn't fall back to OFDM... */
2502 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2503 }
2504 break;
2505
2506 default:
2507 WARN_ON(1);
2508 break;
2509 }
2510
2511 /* Update the rate scaling for control frame Tx */
2512 rate_cmd.table_id = 0;
2513 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2514 &rate_cmd);
2515 if (rc)
2516 return rc;
2517
2518 /* Update the rate scaling for data frame Tx */
2519 rate_cmd.table_id = 1;
2520 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2521 &rate_cmd);
2522 }
2523
2524 /* Called when initializing driver */
2525 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2526 {
2527 memset((void *)&priv->hw_params, 0,
2528 sizeof(struct iwl_hw_params));
2529
2530 priv->shared_virt =
2531 pci_alloc_consistent(priv->pci_dev,
2532 sizeof(struct iwl3945_shared),
2533 &priv->shared_phys);
2534
2535 if (!priv->shared_virt) {
2536 IWL_ERR(priv, "failed to allocate pci memory\n");
2537 mutex_unlock(&priv->mutex);
2538 return -ENOMEM;
2539 }
2540
2541 /* Assign number of Usable TX queues */
2542 priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
2543
2544 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2545 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
2546 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2547 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2548 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2549 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
2550
2551 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2552 priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
2553
2554 return 0;
2555 }
2556
2557 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2558 struct iwl3945_frame *frame, u8 rate)
2559 {
2560 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2561 unsigned int frame_size;
2562
2563 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2564 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2565
2566 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2567 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2568
2569 frame_size = iwl3945_fill_beacon_frame(priv,
2570 tx_beacon_cmd->frame,
2571 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2572
2573 BUG_ON(frame_size > MAX_MPDU_SIZE);
2574 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2575
2576 tx_beacon_cmd->tx.rate = rate;
2577 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2578 TX_CMD_FLG_TSF_MSK);
2579
2580 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2581 tx_beacon_cmd->tx.supp_rates[0] =
2582 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2583
2584 tx_beacon_cmd->tx.supp_rates[1] =
2585 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2586
2587 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2588 }
2589
2590 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2591 {
2592 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2593 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2594 }
2595
2596 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2597 {
2598 INIT_DELAYED_WORK(&priv->thermal_periodic,
2599 iwl3945_bg_reg_txpower_periodic);
2600 }
2601
2602 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2603 {
2604 cancel_delayed_work(&priv->thermal_periodic);
2605 }
2606
2607 /* check contents of special bootstrap uCode SRAM */
2608 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2609 {
2610 __le32 *image = priv->ucode_boot.v_addr;
2611 u32 len = priv->ucode_boot.len;
2612 u32 reg;
2613 u32 val;
2614
2615 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2616
2617 /* verify BSM SRAM contents */
2618 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2619 for (reg = BSM_SRAM_LOWER_BOUND;
2620 reg < BSM_SRAM_LOWER_BOUND + len;
2621 reg += sizeof(u32), image++) {
2622 val = iwl_read_prph(priv, reg);
2623 if (val != le32_to_cpu(*image)) {
2624 IWL_ERR(priv, "BSM uCode verification failed at "
2625 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2626 BSM_SRAM_LOWER_BOUND,
2627 reg - BSM_SRAM_LOWER_BOUND, len,
2628 val, le32_to_cpu(*image));
2629 return -EIO;
2630 }
2631 }
2632
2633 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2634
2635 return 0;
2636 }
2637
2638
2639 /******************************************************************************
2640 *
2641 * EEPROM related functions
2642 *
2643 ******************************************************************************/
2644
2645 /*
2646 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2647 * embedded controller) as EEPROM reader; each read is a series of pulses
2648 * to/from the EEPROM chip, not a single event, so even reads could conflict
2649 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2650 * simply claims ownership, which should be safe when this function is called
2651 * (i.e. before loading uCode!).
2652 */
2653 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2654 {
2655 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2656 return 0;
2657 }
2658
2659
2660 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2661 {
2662 return;
2663 }
2664
2665 /**
2666 * iwl3945_load_bsm - Load bootstrap instructions
2667 *
2668 * BSM operation:
2669 *
2670 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2671 * in special SRAM that does not power down during RFKILL. When powering back
2672 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2673 * the bootstrap program into the on-board processor, and starts it.
2674 *
2675 * The bootstrap program loads (via DMA) instructions and data for a new
2676 * program from host DRAM locations indicated by the host driver in the
2677 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2678 * automatically.
2679 *
2680 * When initializing the NIC, the host driver points the BSM to the
2681 * "initialize" uCode image. This uCode sets up some internal data, then
2682 * notifies host via "initialize alive" that it is complete.
2683 *
2684 * The host then replaces the BSM_DRAM_* pointer values to point to the
2685 * normal runtime uCode instructions and a backup uCode data cache buffer
2686 * (filled initially with starting data values for the on-board processor),
2687 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2688 * which begins normal operation.
2689 *
2690 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2691 * the backup data cache in DRAM before SRAM is powered down.
2692 *
2693 * When powering back up, the BSM loads the bootstrap program. This reloads
2694 * the runtime uCode instructions and the backup data cache into SRAM,
2695 * and re-launches the runtime uCode from where it left off.
2696 */
2697 static int iwl3945_load_bsm(struct iwl_priv *priv)
2698 {
2699 __le32 *image = priv->ucode_boot.v_addr;
2700 u32 len = priv->ucode_boot.len;
2701 dma_addr_t pinst;
2702 dma_addr_t pdata;
2703 u32 inst_len;
2704 u32 data_len;
2705 int rc;
2706 int i;
2707 u32 done;
2708 u32 reg_offset;
2709
2710 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2711
2712 /* make sure bootstrap program is no larger than BSM's SRAM size */
2713 if (len > IWL39_MAX_BSM_SIZE)
2714 return -EINVAL;
2715
2716 /* Tell bootstrap uCode where to find the "Initialize" uCode
2717 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2718 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2719 * after the "initialize" uCode has run, to point to
2720 * runtime/protocol instructions and backup data cache. */
2721 pinst = priv->ucode_init.p_addr;
2722 pdata = priv->ucode_init_data.p_addr;
2723 inst_len = priv->ucode_init.len;
2724 data_len = priv->ucode_init_data.len;
2725
2726 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2727 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2728 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2729 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2730
2731 /* Fill BSM memory with bootstrap instructions */
2732 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2733 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2734 reg_offset += sizeof(u32), image++)
2735 _iwl_write_prph(priv, reg_offset,
2736 le32_to_cpu(*image));
2737
2738 rc = iwl3945_verify_bsm(priv);
2739 if (rc)
2740 return rc;
2741
2742 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2743 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2744 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2745 IWL39_RTC_INST_LOWER_BOUND);
2746 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2747
2748 /* Load bootstrap code into instruction SRAM now,
2749 * to prepare to load "initialize" uCode */
2750 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2751 BSM_WR_CTRL_REG_BIT_START);
2752
2753 /* Wait for load of bootstrap uCode to finish */
2754 for (i = 0; i < 100; i++) {
2755 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2756 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2757 break;
2758 udelay(10);
2759 }
2760 if (i < 100)
2761 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2762 else {
2763 IWL_ERR(priv, "BSM write did not complete!\n");
2764 return -EIO;
2765 }
2766
2767 /* Enable future boot loads whenever power management unit triggers it
2768 * (e.g. when powering back up after power-save shutdown) */
2769 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2770 BSM_WR_CTRL_REG_BIT_START_EN);
2771
2772 return 0;
2773 }
2774
2775 #define IWL3945_UCODE_GET(item) \
2776 static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2777 u32 api_ver) \
2778 { \
2779 return le32_to_cpu(ucode->u.v1.item); \
2780 }
2781
2782 static u32 iwl3945_ucode_get_header_size(u32 api_ver)
2783 {
2784 return UCODE_HEADER_SIZE(1);
2785 }
2786 static u32 iwl3945_ucode_get_build(const struct iwl_ucode_header *ucode,
2787 u32 api_ver)
2788 {
2789 return 0;
2790 }
2791 static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode,
2792 u32 api_ver)
2793 {
2794 return (u8 *) ucode->u.v1.data;
2795 }
2796
2797 IWL3945_UCODE_GET(inst_size);
2798 IWL3945_UCODE_GET(data_size);
2799 IWL3945_UCODE_GET(init_size);
2800 IWL3945_UCODE_GET(init_data_size);
2801 IWL3945_UCODE_GET(boot_size);
2802
2803 static struct iwl_hcmd_ops iwl3945_hcmd = {
2804 .rxon_assoc = iwl3945_send_rxon_assoc,
2805 .commit_rxon = iwl3945_commit_rxon,
2806 };
2807
2808 static struct iwl_ucode_ops iwl3945_ucode = {
2809 .get_header_size = iwl3945_ucode_get_header_size,
2810 .get_build = iwl3945_ucode_get_build,
2811 .get_inst_size = iwl3945_ucode_get_inst_size,
2812 .get_data_size = iwl3945_ucode_get_data_size,
2813 .get_init_size = iwl3945_ucode_get_init_size,
2814 .get_init_data_size = iwl3945_ucode_get_init_data_size,
2815 .get_boot_size = iwl3945_ucode_get_boot_size,
2816 .get_data = iwl3945_ucode_get_data,
2817 };
2818
2819 static struct iwl_lib_ops iwl3945_lib = {
2820 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2821 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2822 .txq_init = iwl3945_hw_tx_queue_init,
2823 .load_ucode = iwl3945_load_bsm,
2824 .dump_nic_event_log = iwl3945_dump_nic_event_log,
2825 .dump_nic_error_log = iwl3945_dump_nic_error_log,
2826 .apm_ops = {
2827 .init = iwl3945_apm_init,
2828 .stop = iwl_apm_stop,
2829 .config = iwl3945_nic_config,
2830 .set_pwr_src = iwl3945_set_pwr_src,
2831 },
2832 .eeprom_ops = {
2833 .regulatory_bands = {
2834 EEPROM_REGULATORY_BAND_1_CHANNELS,
2835 EEPROM_REGULATORY_BAND_2_CHANNELS,
2836 EEPROM_REGULATORY_BAND_3_CHANNELS,
2837 EEPROM_REGULATORY_BAND_4_CHANNELS,
2838 EEPROM_REGULATORY_BAND_5_CHANNELS,
2839 EEPROM_REGULATORY_BAND_NO_HT40,
2840 EEPROM_REGULATORY_BAND_NO_HT40,
2841 },
2842 .verify_signature = iwlcore_eeprom_verify_signature,
2843 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2844 .release_semaphore = iwl3945_eeprom_release_semaphore,
2845 .query_addr = iwlcore_eeprom_query_addr,
2846 },
2847 .send_tx_power = iwl3945_send_tx_power,
2848 .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
2849 .post_associate = iwl3945_post_associate,
2850 .isr = iwl_isr_legacy,
2851 .config_ap = iwl3945_config_ap,
2852 };
2853
2854 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2855 .get_hcmd_size = iwl3945_get_hcmd_size,
2856 .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2857 .rts_tx_cmd_flag = iwlcore_rts_tx_cmd_flag,
2858 };
2859
2860 static struct iwl_ops iwl3945_ops = {
2861 .ucode = &iwl3945_ucode,
2862 .lib = &iwl3945_lib,
2863 .hcmd = &iwl3945_hcmd,
2864 .utils = &iwl3945_hcmd_utils,
2865 .led = &iwl3945_led_ops,
2866 };
2867
2868 static struct iwl_cfg iwl3945_bg_cfg = {
2869 .name = "3945BG",
2870 .fw_name_pre = IWL3945_FW_PRE,
2871 .ucode_api_max = IWL3945_UCODE_API_MAX,
2872 .ucode_api_min = IWL3945_UCODE_API_MIN,
2873 .sku = IWL_SKU_G,
2874 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2875 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2876 .ops = &iwl3945_ops,
2877 .num_of_queues = IWL39_NUM_QUEUES,
2878 .mod_params = &iwl3945_mod_params,
2879 .use_isr_legacy = true,
2880 .ht_greenfield_support = false,
2881 .led_compensation = 64,
2882 };
2883
2884 static struct iwl_cfg iwl3945_abg_cfg = {
2885 .name = "3945ABG",
2886 .fw_name_pre = IWL3945_FW_PRE,
2887 .ucode_api_max = IWL3945_UCODE_API_MAX,
2888 .ucode_api_min = IWL3945_UCODE_API_MIN,
2889 .sku = IWL_SKU_A|IWL_SKU_G,
2890 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2891 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2892 .ops = &iwl3945_ops,
2893 .num_of_queues = IWL39_NUM_QUEUES,
2894 .mod_params = &iwl3945_mod_params,
2895 .use_isr_legacy = true,
2896 .ht_greenfield_support = false,
2897 .led_compensation = 64,
2898 };
2899
2900 struct pci_device_id iwl3945_hw_card_ids[] = {
2901 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2902 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2903 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2904 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2905 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2906 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2907 {0}
2908 };
2909
2910 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
mm of the moment repository