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On Tue, Nov 06, 2007 at 02:33:53AM -0800, akpm@linux-foundation.org wrote:
[mmotm.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
blob7e836e846d00ef3c6999f9d1e89d499cb6ed8f58
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/sched.h>
34 #include <linux/skbuff.h>
35 #include <linux/netdevice.h>
36 #include <linux/wireless.h>
37 #include <net/mac80211.h>
38 #include <linux/etherdevice.h>
39 #include <asm/unaligned.h>
40
41 #include "iwl-eeprom.h"
42 #include "iwl-dev.h"
43 #include "iwl-core.h"
44 #include "iwl-io.h"
45 #include "iwl-helpers.h"
46 #include "iwl-calib.h"
47 #include "iwl-sta.h"
48 #include "iwl-agn-led.h"
49
50 static int iwl4965_send_tx_power(struct iwl_priv *priv);
51 static int iwl4965_hw_get_temperature(struct iwl_priv *priv);
52
53 /* Highest firmware API version supported */
54 #define IWL4965_UCODE_API_MAX 2
55
56 /* Lowest firmware API version supported */
57 #define IWL4965_UCODE_API_MIN 2
58
59 #define IWL4965_FW_PRE "iwlwifi-4965-"
60 #define _IWL4965_MODULE_FIRMWARE(api) IWL4965_FW_PRE #api ".ucode"
61 #define IWL4965_MODULE_FIRMWARE(api) _IWL4965_MODULE_FIRMWARE(api)
62
63
64 /* module parameters */
65 static struct iwl_mod_params iwl4965_mod_params = {
66 .amsdu_size_8K = 1,
67 .restart_fw = 1,
68 /* the rest are 0 by default */
69 };
70
71 /* check contents of special bootstrap uCode SRAM */
72 static int iwl4965_verify_bsm(struct iwl_priv *priv)
73 {
74 __le32 *image = priv->ucode_boot.v_addr;
75 u32 len = priv->ucode_boot.len;
76 u32 reg;
77 u32 val;
78
79 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
80
81 /* verify BSM SRAM contents */
82 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
83 for (reg = BSM_SRAM_LOWER_BOUND;
84 reg < BSM_SRAM_LOWER_BOUND + len;
85 reg += sizeof(u32), image++) {
86 val = iwl_read_prph(priv, reg);
87 if (val != le32_to_cpu(*image)) {
88 IWL_ERR(priv, "BSM uCode verification failed at "
89 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
90 BSM_SRAM_LOWER_BOUND,
91 reg - BSM_SRAM_LOWER_BOUND, len,
92 val, le32_to_cpu(*image));
93 return -EIO;
94 }
95 }
96
97 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
98
99 return 0;
100 }
101
102 /**
103 * iwl4965_load_bsm - Load bootstrap instructions
104 *
105 * BSM operation:
106 *
107 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
108 * in special SRAM that does not power down during RFKILL. When powering back
109 * up after power-saving sleeps (or during initial uCode load), the BSM loads
110 * the bootstrap program into the on-board processor, and starts it.
111 *
112 * The bootstrap program loads (via DMA) instructions and data for a new
113 * program from host DRAM locations indicated by the host driver in the
114 * BSM_DRAM_* registers. Once the new program is loaded, it starts
115 * automatically.
116 *
117 * When initializing the NIC, the host driver points the BSM to the
118 * "initialize" uCode image. This uCode sets up some internal data, then
119 * notifies host via "initialize alive" that it is complete.
120 *
121 * The host then replaces the BSM_DRAM_* pointer values to point to the
122 * normal runtime uCode instructions and a backup uCode data cache buffer
123 * (filled initially with starting data values for the on-board processor),
124 * then triggers the "initialize" uCode to load and launch the runtime uCode,
125 * which begins normal operation.
126 *
127 * When doing a power-save shutdown, runtime uCode saves data SRAM into
128 * the backup data cache in DRAM before SRAM is powered down.
129 *
130 * When powering back up, the BSM loads the bootstrap program. This reloads
131 * the runtime uCode instructions and the backup data cache into SRAM,
132 * and re-launches the runtime uCode from where it left off.
133 */
134 static int iwl4965_load_bsm(struct iwl_priv *priv)
135 {
136 __le32 *image = priv->ucode_boot.v_addr;
137 u32 len = priv->ucode_boot.len;
138 dma_addr_t pinst;
139 dma_addr_t pdata;
140 u32 inst_len;
141 u32 data_len;
142 int i;
143 u32 done;
144 u32 reg_offset;
145 int ret;
146
147 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
148
149 priv->ucode_type = UCODE_RT;
150
151 /* make sure bootstrap program is no larger than BSM's SRAM size */
152 if (len > IWL49_MAX_BSM_SIZE)
153 return -EINVAL;
154
155 /* Tell bootstrap uCode where to find the "Initialize" uCode
156 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
157 * NOTE: iwl_init_alive_start() will replace these values,
158 * after the "initialize" uCode has run, to point to
159 * runtime/protocol instructions and backup data cache.
160 */
161 pinst = priv->ucode_init.p_addr >> 4;
162 pdata = priv->ucode_init_data.p_addr >> 4;
163 inst_len = priv->ucode_init.len;
164 data_len = priv->ucode_init_data.len;
165
166 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
167 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
168 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
169 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
170
171 /* Fill BSM memory with bootstrap instructions */
172 for (reg_offset = BSM_SRAM_LOWER_BOUND;
173 reg_offset < BSM_SRAM_LOWER_BOUND + len;
174 reg_offset += sizeof(u32), image++)
175 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
176
177 ret = iwl4965_verify_bsm(priv);
178 if (ret)
179 return ret;
180
181 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
182 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
183 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, IWL49_RTC_INST_LOWER_BOUND);
184 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
185
186 /* Load bootstrap code into instruction SRAM now,
187 * to prepare to load "initialize" uCode */
188 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
189
190 /* Wait for load of bootstrap uCode to finish */
191 for (i = 0; i < 100; i++) {
192 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
193 if (!(done & BSM_WR_CTRL_REG_BIT_START))
194 break;
195 udelay(10);
196 }
197 if (i < 100)
198 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
199 else {
200 IWL_ERR(priv, "BSM write did not complete!\n");
201 return -EIO;
202 }
203
204 /* Enable future boot loads whenever power management unit triggers it
205 * (e.g. when powering back up after power-save shutdown) */
206 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
207
208
209 return 0;
210 }
211
212 /**
213 * iwl4965_set_ucode_ptrs - Set uCode address location
214 *
215 * Tell initialization uCode where to find runtime uCode.
216 *
217 * BSM registers initially contain pointers to initialization uCode.
218 * We need to replace them to load runtime uCode inst and data,
219 * and to save runtime data when powering down.
220 */
221 static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
222 {
223 dma_addr_t pinst;
224 dma_addr_t pdata;
225 int ret = 0;
226
227 /* bits 35:4 for 4965 */
228 pinst = priv->ucode_code.p_addr >> 4;
229 pdata = priv->ucode_data_backup.p_addr >> 4;
230
231 /* Tell bootstrap uCode where to find image to load */
232 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
233 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
234 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
235 priv->ucode_data.len);
236
237 /* Inst byte count must be last to set up, bit 31 signals uCode
238 * that all new ptr/size info is in place */
239 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
240 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
241 IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
242
243 return ret;
244 }
245
246 /**
247 * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
248 *
249 * Called after REPLY_ALIVE notification received from "initialize" uCode.
250 *
251 * The 4965 "initialize" ALIVE reply contains calibration data for:
252 * Voltage, temperature, and MIMO tx gain correction, now stored in priv
253 * (3945 does not contain this data).
254 *
255 * Tell "initialize" uCode to go ahead and load the runtime uCode.
256 */
257 static void iwl4965_init_alive_start(struct iwl_priv *priv)
258 {
259 /* Check alive response for "valid" sign from uCode */
260 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
261 /* We had an error bringing up the hardware, so take it
262 * all the way back down so we can try again */
263 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
264 goto restart;
265 }
266
267 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
268 * This is a paranoid check, because we would not have gotten the
269 * "initialize" alive if code weren't properly loaded. */
270 if (iwl_verify_ucode(priv)) {
271 /* Runtime instruction load was bad;
272 * take it all the way back down so we can try again */
273 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
274 goto restart;
275 }
276
277 /* Calculate temperature */
278 priv->temperature = iwl4965_hw_get_temperature(priv);
279
280 /* Send pointers to protocol/runtime uCode image ... init code will
281 * load and launch runtime uCode, which will send us another "Alive"
282 * notification. */
283 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
284 if (iwl4965_set_ucode_ptrs(priv)) {
285 /* Runtime instruction load won't happen;
286 * take it all the way back down so we can try again */
287 IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
288 goto restart;
289 }
290 return;
291
292 restart:
293 queue_work(priv->workqueue, &priv->restart);
294 }
295
296 static bool is_ht40_channel(__le32 rxon_flags)
297 {
298 int chan_mod = le32_to_cpu(rxon_flags & RXON_FLG_CHANNEL_MODE_MSK)
299 >> RXON_FLG_CHANNEL_MODE_POS;
300 return ((chan_mod == CHANNEL_MODE_PURE_40) ||
301 (chan_mod == CHANNEL_MODE_MIXED));
302 }
303
304 /*
305 * EEPROM handlers
306 */
307 static u16 iwl4965_eeprom_calib_version(struct iwl_priv *priv)
308 {
309 return iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
310 }
311
312 /*
313 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
314 * must be called under priv->lock and mac access
315 */
316 static void iwl4965_txq_set_sched(struct iwl_priv *priv, u32 mask)
317 {
318 iwl_write_prph(priv, IWL49_SCD_TXFACT, mask);
319 }
320
321 static int iwl4965_apm_init(struct iwl_priv *priv)
322 {
323 int ret = 0;
324
325 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
326 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
327
328 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
329 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
330 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
331
332 /* set "initialization complete" bit to move adapter
333 * D0U* --> D0A* state */
334 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
335
336 /* wait for clock stabilization */
337 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
338 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
339 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
340 if (ret < 0) {
341 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
342 goto out;
343 }
344
345 /* enable DMA */
346 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
347 APMG_CLK_VAL_BSM_CLK_RQT);
348
349 udelay(20);
350
351 /* disable L1-Active */
352 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
353 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
354
355 out:
356 return ret;
357 }
358
359
360 static void iwl4965_nic_config(struct iwl_priv *priv)
361 {
362 unsigned long flags;
363 u16 radio_cfg;
364 u16 lctl;
365
366 spin_lock_irqsave(&priv->lock, flags);
367
368 lctl = iwl_pcie_link_ctl(priv);
369
370 /* HW bug W/A - negligible power consumption */
371 /* L1-ASPM is enabled by BIOS */
372 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
373 /* L1-ASPM enabled: disable L0S */
374 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
375 else
376 /* L1-ASPM disabled: enable L0S */
377 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
378
379 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
380
381 /* write radio config values to register */
382 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
383 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
384 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
385 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
386 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
387
388 /* set CSR_HW_CONFIG_REG for uCode use */
389 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
390 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
391 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
392
393 priv->calib_info = (struct iwl_eeprom_calib_info *)
394 iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
395
396 spin_unlock_irqrestore(&priv->lock, flags);
397 }
398
399 /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
400 * Called after every association, but this runs only once!
401 * ... once chain noise is calibrated the first time, it's good forever. */
402 static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
403 {
404 struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
405
406 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
407 struct iwl_calib_diff_gain_cmd cmd;
408
409 memset(&cmd, 0, sizeof(cmd));
410 cmd.hdr.op_code = IWL_PHY_CALIBRATE_DIFF_GAIN_CMD;
411 cmd.diff_gain_a = 0;
412 cmd.diff_gain_b = 0;
413 cmd.diff_gain_c = 0;
414 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
415 sizeof(cmd), &cmd))
416 IWL_ERR(priv,
417 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
418 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
419 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
420 }
421 }
422
423 static void iwl4965_gain_computation(struct iwl_priv *priv,
424 u32 *average_noise,
425 u16 min_average_noise_antenna_i,
426 u32 min_average_noise,
427 u8 default_chain)
428 {
429 int i, ret;
430 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
431
432 data->delta_gain_code[min_average_noise_antenna_i] = 0;
433
434 for (i = default_chain; i < NUM_RX_CHAINS; i++) {
435 s32 delta_g = 0;
436
437 if (!(data->disconn_array[i]) &&
438 (data->delta_gain_code[i] ==
439 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
440 delta_g = average_noise[i] - min_average_noise;
441 data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
442 data->delta_gain_code[i] =
443 min(data->delta_gain_code[i],
444 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
445
446 data->delta_gain_code[i] =
447 (data->delta_gain_code[i] | (1 << 2));
448 } else {
449 data->delta_gain_code[i] = 0;
450 }
451 }
452 IWL_DEBUG_CALIB(priv, "delta_gain_codes: a %d b %d c %d\n",
453 data->delta_gain_code[0],
454 data->delta_gain_code[1],
455 data->delta_gain_code[2]);
456
457 /* Differential gain gets sent to uCode only once */
458 if (!data->radio_write) {
459 struct iwl_calib_diff_gain_cmd cmd;
460 data->radio_write = 1;
461
462 memset(&cmd, 0, sizeof(cmd));
463 cmd.hdr.op_code = IWL_PHY_CALIBRATE_DIFF_GAIN_CMD;
464 cmd.diff_gain_a = data->delta_gain_code[0];
465 cmd.diff_gain_b = data->delta_gain_code[1];
466 cmd.diff_gain_c = data->delta_gain_code[2];
467 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
468 sizeof(cmd), &cmd);
469 if (ret)
470 IWL_DEBUG_CALIB(priv, "fail sending cmd "
471 "REPLY_PHY_CALIBRATION_CMD \n");
472
473 /* TODO we might want recalculate
474 * rx_chain in rxon cmd */
475
476 /* Mark so we run this algo only once! */
477 data->state = IWL_CHAIN_NOISE_CALIBRATED;
478 }
479 data->chain_noise_a = 0;
480 data->chain_noise_b = 0;
481 data->chain_noise_c = 0;
482 data->chain_signal_a = 0;
483 data->chain_signal_b = 0;
484 data->chain_signal_c = 0;
485 data->beacon_count = 0;
486 }
487
488 static void iwl4965_bg_txpower_work(struct work_struct *work)
489 {
490 struct iwl_priv *priv = container_of(work, struct iwl_priv,
491 txpower_work);
492
493 /* If a scan happened to start before we got here
494 * then just return; the statistics notification will
495 * kick off another scheduled work to compensate for
496 * any temperature delta we missed here. */
497 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
498 test_bit(STATUS_SCANNING, &priv->status))
499 return;
500
501 mutex_lock(&priv->mutex);
502
503 /* Regardless of if we are associated, we must reconfigure the
504 * TX power since frames can be sent on non-radar channels while
505 * not associated */
506 iwl4965_send_tx_power(priv);
507
508 /* Update last_temperature to keep is_calib_needed from running
509 * when it isn't needed... */
510 priv->last_temperature = priv->temperature;
511
512 mutex_unlock(&priv->mutex);
513 }
514
515 /*
516 * Acquire priv->lock before calling this function !
517 */
518 static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
519 {
520 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
521 (index & 0xff) | (txq_id << 8));
522 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
523 }
524
525 /**
526 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
527 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
528 * @scd_retry: (1) Indicates queue will be used in aggregation mode
529 *
530 * NOTE: Acquire priv->lock before calling this function !
531 */
532 static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
533 struct iwl_tx_queue *txq,
534 int tx_fifo_id, int scd_retry)
535 {
536 int txq_id = txq->q.id;
537
538 /* Find out whether to activate Tx queue */
539 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
540
541 /* Set up and activate */
542 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
543 (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
544 (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
545 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
546 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
547 IWL49_SCD_QUEUE_STTS_REG_MSK);
548
549 txq->sched_retry = scd_retry;
550
551 IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
552 active ? "Activate" : "Deactivate",
553 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
554 }
555
556 static const u16 default_queue_to_tx_fifo[] = {
557 IWL_TX_FIFO_AC3,
558 IWL_TX_FIFO_AC2,
559 IWL_TX_FIFO_AC1,
560 IWL_TX_FIFO_AC0,
561 IWL49_CMD_FIFO_NUM,
562 IWL_TX_FIFO_HCCA_1,
563 IWL_TX_FIFO_HCCA_2
564 };
565
566 static int iwl4965_alive_notify(struct iwl_priv *priv)
567 {
568 u32 a;
569 unsigned long flags;
570 int i, chan;
571 u32 reg_val;
572
573 spin_lock_irqsave(&priv->lock, flags);
574
575 /* Clear 4965's internal Tx Scheduler data base */
576 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
577 a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
578 for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
579 iwl_write_targ_mem(priv, a, 0);
580 for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
581 iwl_write_targ_mem(priv, a, 0);
582 for (; a < priv->scd_base_addr +
583 IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
584 iwl_write_targ_mem(priv, a, 0);
585
586 /* Tel 4965 where to find Tx byte count tables */
587 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
588 priv->scd_bc_tbls.dma >> 10);
589
590 /* Enable DMA channel */
591 for (chan = 0; chan < FH49_TCSR_CHNL_NUM ; chan++)
592 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
593 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
594 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
595
596 /* Update FH chicken bits */
597 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
598 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
599 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
600
601 /* Disable chain mode for all queues */
602 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
603
604 /* Initialize each Tx queue (including the command queue) */
605 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
606
607 /* TFD circular buffer read/write indexes */
608 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
609 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
610
611 /* Max Tx Window size for Scheduler-ACK mode */
612 iwl_write_targ_mem(priv, priv->scd_base_addr +
613 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
614 (SCD_WIN_SIZE <<
615 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
616 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
617
618 /* Frame limit */
619 iwl_write_targ_mem(priv, priv->scd_base_addr +
620 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
621 sizeof(u32),
622 (SCD_FRAME_LIMIT <<
623 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
624 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
625
626 }
627 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
628 (1 << priv->hw_params.max_txq_num) - 1);
629
630 /* Activate all Tx DMA/FIFO channels */
631 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 6));
632
633 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
634
635 /* Map each Tx/cmd queue to its corresponding fifo */
636 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
637 int ac = default_queue_to_tx_fifo[i];
638 iwl_txq_ctx_activate(priv, i);
639 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
640 }
641
642 spin_unlock_irqrestore(&priv->lock, flags);
643
644 return 0;
645 }
646
647 static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
648 .min_nrg_cck = 97,
649 .max_nrg_cck = 0, /* not used, set to 0 */
650
651 .auto_corr_min_ofdm = 85,
652 .auto_corr_min_ofdm_mrc = 170,
653 .auto_corr_min_ofdm_x1 = 105,
654 .auto_corr_min_ofdm_mrc_x1 = 220,
655
656 .auto_corr_max_ofdm = 120,
657 .auto_corr_max_ofdm_mrc = 210,
658 .auto_corr_max_ofdm_x1 = 140,
659 .auto_corr_max_ofdm_mrc_x1 = 270,
660
661 .auto_corr_min_cck = 125,
662 .auto_corr_max_cck = 200,
663 .auto_corr_min_cck_mrc = 200,
664 .auto_corr_max_cck_mrc = 400,
665
666 .nrg_th_cck = 100,
667 .nrg_th_ofdm = 100,
668
669 .barker_corr_th_min = 190,
670 .barker_corr_th_min_mrc = 390,
671 .nrg_th_cca = 62,
672 };
673
674 static void iwl4965_set_ct_threshold(struct iwl_priv *priv)
675 {
676 /* want Kelvin */
677 priv->hw_params.ct_kill_threshold =
678 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY);
679 }
680
681 /**
682 * iwl4965_hw_set_hw_params
683 *
684 * Called when initializing driver
685 */
686 static int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
687 {
688 if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES &&
689 priv->cfg->mod_params->num_of_queues <= IWL49_NUM_QUEUES)
690 priv->cfg->num_of_queues =
691 priv->cfg->mod_params->num_of_queues;
692
693 priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
694 priv->hw_params.dma_chnl_num = FH49_TCSR_CHNL_NUM;
695 priv->hw_params.scd_bc_tbls_size =
696 priv->cfg->num_of_queues *
697 sizeof(struct iwl4965_scd_bc_tbl);
698 priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
699 priv->hw_params.max_stations = IWL4965_STATION_COUNT;
700 priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
701 priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
702 priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
703 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
704 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_5GHZ);
705
706 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
707
708 priv->hw_params.tx_chains_num = 2;
709 priv->hw_params.rx_chains_num = 2;
710 priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
711 priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
712 if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
713 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
714
715 priv->hw_params.sens = &iwl4965_sensitivity;
716
717 return 0;
718 }
719
720 static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
721 {
722 s32 sign = 1;
723
724 if (num < 0) {
725 sign = -sign;
726 num = -num;
727 }
728 if (denom < 0) {
729 sign = -sign;
730 denom = -denom;
731 }
732 *res = 1;
733 *res = ((num * 2 + denom) / (denom * 2)) * sign;
734
735 return 1;
736 }
737
738 /**
739 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
740 *
741 * Determines power supply voltage compensation for txpower calculations.
742 * Returns number of 1/2-dB steps to subtract from gain table index,
743 * to compensate for difference between power supply voltage during
744 * factory measurements, vs. current power supply voltage.
745 *
746 * Voltage indication is higher for lower voltage.
747 * Lower voltage requires more gain (lower gain table index).
748 */
749 static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
750 s32 current_voltage)
751 {
752 s32 comp = 0;
753
754 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
755 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
756 return 0;
757
758 iwl4965_math_div_round(current_voltage - eeprom_voltage,
759 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
760
761 if (current_voltage > eeprom_voltage)
762 comp *= 2;
763 if ((comp < -2) || (comp > 2))
764 comp = 0;
765
766 return comp;
767 }
768
769 static s32 iwl4965_get_tx_atten_grp(u16 channel)
770 {
771 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
772 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
773 return CALIB_CH_GROUP_5;
774
775 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
776 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
777 return CALIB_CH_GROUP_1;
778
779 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
780 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
781 return CALIB_CH_GROUP_2;
782
783 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
784 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
785 return CALIB_CH_GROUP_3;
786
787 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
788 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
789 return CALIB_CH_GROUP_4;
790
791 return -1;
792 }
793
794 static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
795 {
796 s32 b = -1;
797
798 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
799 if (priv->calib_info->band_info[b].ch_from == 0)
800 continue;
801
802 if ((channel >= priv->calib_info->band_info[b].ch_from)
803 && (channel <= priv->calib_info->band_info[b].ch_to))
804 break;
805 }
806
807 return b;
808 }
809
810 static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
811 {
812 s32 val;
813
814 if (x2 == x1)
815 return y1;
816 else {
817 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
818 return val + y2;
819 }
820 }
821
822 /**
823 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
824 *
825 * Interpolates factory measurements from the two sample channels within a
826 * sub-band, to apply to channel of interest. Interpolation is proportional to
827 * differences in channel frequencies, which is proportional to differences
828 * in channel number.
829 */
830 static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
831 struct iwl_eeprom_calib_ch_info *chan_info)
832 {
833 s32 s = -1;
834 u32 c;
835 u32 m;
836 const struct iwl_eeprom_calib_measure *m1;
837 const struct iwl_eeprom_calib_measure *m2;
838 struct iwl_eeprom_calib_measure *omeas;
839 u32 ch_i1;
840 u32 ch_i2;
841
842 s = iwl4965_get_sub_band(priv, channel);
843 if (s >= EEPROM_TX_POWER_BANDS) {
844 IWL_ERR(priv, "Tx Power can not find channel %d\n", channel);
845 return -1;
846 }
847
848 ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
849 ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
850 chan_info->ch_num = (u8) channel;
851
852 IWL_DEBUG_TXPOWER(priv, "channel %d subband %d factory cal ch %d & %d\n",
853 channel, s, ch_i1, ch_i2);
854
855 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
856 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
857 m1 = &(priv->calib_info->band_info[s].ch1.
858 measurements[c][m]);
859 m2 = &(priv->calib_info->band_info[s].ch2.
860 measurements[c][m]);
861 omeas = &(chan_info->measurements[c][m]);
862
863 omeas->actual_pow =
864 (u8) iwl4965_interpolate_value(channel, ch_i1,
865 m1->actual_pow,
866 ch_i2,
867 m2->actual_pow);
868 omeas->gain_idx =
869 (u8) iwl4965_interpolate_value(channel, ch_i1,
870 m1->gain_idx, ch_i2,
871 m2->gain_idx);
872 omeas->temperature =
873 (u8) iwl4965_interpolate_value(channel, ch_i1,
874 m1->temperature,
875 ch_i2,
876 m2->temperature);
877 omeas->pa_det =
878 (s8) iwl4965_interpolate_value(channel, ch_i1,
879 m1->pa_det, ch_i2,
880 m2->pa_det);
881
882 IWL_DEBUG_TXPOWER(priv,
883 "chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
884 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
885 IWL_DEBUG_TXPOWER(priv,
886 "chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
887 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
888 IWL_DEBUG_TXPOWER(priv,
889 "chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
890 m1->pa_det, m2->pa_det, omeas->pa_det);
891 IWL_DEBUG_TXPOWER(priv,
892 "chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
893 m1->temperature, m2->temperature,
894 omeas->temperature);
895 }
896 }
897
898 return 0;
899 }
900
901 /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
902 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
903 static s32 back_off_table[] = {
904 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
905 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
906 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
907 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
908 10 /* CCK */
909 };
910
911 /* Thermal compensation values for txpower for various frequency ranges ...
912 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
913 static struct iwl4965_txpower_comp_entry {
914 s32 degrees_per_05db_a;
915 s32 degrees_per_05db_a_denom;
916 } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
917 {9, 2}, /* group 0 5.2, ch 34-43 */
918 {4, 1}, /* group 1 5.2, ch 44-70 */
919 {4, 1}, /* group 2 5.2, ch 71-124 */
920 {4, 1}, /* group 3 5.2, ch 125-200 */
921 {3, 1} /* group 4 2.4, ch all */
922 };
923
924 static s32 get_min_power_index(s32 rate_power_index, u32 band)
925 {
926 if (!band) {
927 if ((rate_power_index & 7) <= 4)
928 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
929 }
930 return MIN_TX_GAIN_INDEX;
931 }
932
933 struct gain_entry {
934 u8 dsp;
935 u8 radio;
936 };
937
938 static const struct gain_entry gain_table[2][108] = {
939 /* 5.2GHz power gain index table */
940 {
941 {123, 0x3F}, /* highest txpower */
942 {117, 0x3F},
943 {110, 0x3F},
944 {104, 0x3F},
945 {98, 0x3F},
946 {110, 0x3E},
947 {104, 0x3E},
948 {98, 0x3E},
949 {110, 0x3D},
950 {104, 0x3D},
951 {98, 0x3D},
952 {110, 0x3C},
953 {104, 0x3C},
954 {98, 0x3C},
955 {110, 0x3B},
956 {104, 0x3B},
957 {98, 0x3B},
958 {110, 0x3A},
959 {104, 0x3A},
960 {98, 0x3A},
961 {110, 0x39},
962 {104, 0x39},
963 {98, 0x39},
964 {110, 0x38},
965 {104, 0x38},
966 {98, 0x38},
967 {110, 0x37},
968 {104, 0x37},
969 {98, 0x37},
970 {110, 0x36},
971 {104, 0x36},
972 {98, 0x36},
973 {110, 0x35},
974 {104, 0x35},
975 {98, 0x35},
976 {110, 0x34},
977 {104, 0x34},
978 {98, 0x34},
979 {110, 0x33},
980 {104, 0x33},
981 {98, 0x33},
982 {110, 0x32},
983 {104, 0x32},
984 {98, 0x32},
985 {110, 0x31},
986 {104, 0x31},
987 {98, 0x31},
988 {110, 0x30},
989 {104, 0x30},
990 {98, 0x30},
991 {110, 0x25},
992 {104, 0x25},
993 {98, 0x25},
994 {110, 0x24},
995 {104, 0x24},
996 {98, 0x24},
997 {110, 0x23},
998 {104, 0x23},
999 {98, 0x23},
1000 {110, 0x22},
1001 {104, 0x18},
1002 {98, 0x18},
1003 {110, 0x17},
1004 {104, 0x17},
1005 {98, 0x17},
1006 {110, 0x16},
1007 {104, 0x16},
1008 {98, 0x16},
1009 {110, 0x15},
1010 {104, 0x15},
1011 {98, 0x15},
1012 {110, 0x14},
1013 {104, 0x14},
1014 {98, 0x14},
1015 {110, 0x13},
1016 {104, 0x13},
1017 {98, 0x13},
1018 {110, 0x12},
1019 {104, 0x08},
1020 {98, 0x08},
1021 {110, 0x07},
1022 {104, 0x07},
1023 {98, 0x07},
1024 {110, 0x06},
1025 {104, 0x06},
1026 {98, 0x06},
1027 {110, 0x05},
1028 {104, 0x05},
1029 {98, 0x05},
1030 {110, 0x04},
1031 {104, 0x04},
1032 {98, 0x04},
1033 {110, 0x03},
1034 {104, 0x03},
1035 {98, 0x03},
1036 {110, 0x02},
1037 {104, 0x02},
1038 {98, 0x02},
1039 {110, 0x01},
1040 {104, 0x01},
1041 {98, 0x01},
1042 {110, 0x00},
1043 {104, 0x00},
1044 {98, 0x00},
1045 {93, 0x00},
1046 {88, 0x00},
1047 {83, 0x00},
1048 {78, 0x00},
1049 },
1050 /* 2.4GHz power gain index table */
1051 {
1052 {110, 0x3f}, /* highest txpower */
1053 {104, 0x3f},
1054 {98, 0x3f},
1055 {110, 0x3e},
1056 {104, 0x3e},
1057 {98, 0x3e},
1058 {110, 0x3d},
1059 {104, 0x3d},
1060 {98, 0x3d},
1061 {110, 0x3c},
1062 {104, 0x3c},
1063 {98, 0x3c},
1064 {110, 0x3b},
1065 {104, 0x3b},
1066 {98, 0x3b},
1067 {110, 0x3a},
1068 {104, 0x3a},
1069 {98, 0x3a},
1070 {110, 0x39},
1071 {104, 0x39},
1072 {98, 0x39},
1073 {110, 0x38},
1074 {104, 0x38},
1075 {98, 0x38},
1076 {110, 0x37},
1077 {104, 0x37},
1078 {98, 0x37},
1079 {110, 0x36},
1080 {104, 0x36},
1081 {98, 0x36},
1082 {110, 0x35},
1083 {104, 0x35},
1084 {98, 0x35},
1085 {110, 0x34},
1086 {104, 0x34},
1087 {98, 0x34},
1088 {110, 0x33},
1089 {104, 0x33},
1090 {98, 0x33},
1091 {110, 0x32},
1092 {104, 0x32},
1093 {98, 0x32},
1094 {110, 0x31},
1095 {104, 0x31},
1096 {98, 0x31},
1097 {110, 0x30},
1098 {104, 0x30},
1099 {98, 0x30},
1100 {110, 0x6},
1101 {104, 0x6},
1102 {98, 0x6},
1103 {110, 0x5},
1104 {104, 0x5},
1105 {98, 0x5},
1106 {110, 0x4},
1107 {104, 0x4},
1108 {98, 0x4},
1109 {110, 0x3},
1110 {104, 0x3},
1111 {98, 0x3},
1112 {110, 0x2},
1113 {104, 0x2},
1114 {98, 0x2},
1115 {110, 0x1},
1116 {104, 0x1},
1117 {98, 0x1},
1118 {110, 0x0},
1119 {104, 0x0},
1120 {98, 0x0},
1121 {97, 0},
1122 {96, 0},
1123 {95, 0},
1124 {94, 0},
1125 {93, 0},
1126 {92, 0},
1127 {91, 0},
1128 {90, 0},
1129 {89, 0},
1130 {88, 0},
1131 {87, 0},
1132 {86, 0},
1133 {85, 0},
1134 {84, 0},
1135 {83, 0},
1136 {82, 0},
1137 {81, 0},
1138 {80, 0},
1139 {79, 0},
1140 {78, 0},
1141 {77, 0},
1142 {76, 0},
1143 {75, 0},
1144 {74, 0},
1145 {73, 0},
1146 {72, 0},
1147 {71, 0},
1148 {70, 0},
1149 {69, 0},
1150 {68, 0},
1151 {67, 0},
1152 {66, 0},
1153 {65, 0},
1154 {64, 0},
1155 {63, 0},
1156 {62, 0},
1157 {61, 0},
1158 {60, 0},
1159 {59, 0},
1160 }
1161 };
1162
1163 static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
1164 u8 is_ht40, u8 ctrl_chan_high,
1165 struct iwl4965_tx_power_db *tx_power_tbl)
1166 {
1167 u8 saturation_power;
1168 s32 target_power;
1169 s32 user_target_power;
1170 s32 power_limit;
1171 s32 current_temp;
1172 s32 reg_limit;
1173 s32 current_regulatory;
1174 s32 txatten_grp = CALIB_CH_GROUP_MAX;
1175 int i;
1176 int c;
1177 const struct iwl_channel_info *ch_info = NULL;
1178 struct iwl_eeprom_calib_ch_info ch_eeprom_info;
1179 const struct iwl_eeprom_calib_measure *measurement;
1180 s16 voltage;
1181 s32 init_voltage;
1182 s32 voltage_compensation;
1183 s32 degrees_per_05db_num;
1184 s32 degrees_per_05db_denom;
1185 s32 factory_temp;
1186 s32 temperature_comp[2];
1187 s32 factory_gain_index[2];
1188 s32 factory_actual_pwr[2];
1189 s32 power_index;
1190
1191 /* tx_power_user_lmt is in dBm, convert to half-dBm (half-dB units
1192 * are used for indexing into txpower table) */
1193 user_target_power = 2 * priv->tx_power_user_lmt;
1194
1195 /* Get current (RXON) channel, band, width */
1196 IWL_DEBUG_TXPOWER(priv, "chan %d band %d is_ht40 %d\n", channel, band,
1197 is_ht40);
1198
1199 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1200
1201 if (!is_channel_valid(ch_info))
1202 return -EINVAL;
1203
1204 /* get txatten group, used to select 1) thermal txpower adjustment
1205 * and 2) mimo txpower balance between Tx chains. */
1206 txatten_grp = iwl4965_get_tx_atten_grp(channel);
1207 if (txatten_grp < 0) {
1208 IWL_ERR(priv, "Can't find txatten group for channel %d.\n",
1209 channel);
1210 return -EINVAL;
1211 }
1212
1213 IWL_DEBUG_TXPOWER(priv, "channel %d belongs to txatten group %d\n",
1214 channel, txatten_grp);
1215
1216 if (is_ht40) {
1217 if (ctrl_chan_high)
1218 channel -= 2;
1219 else
1220 channel += 2;
1221 }
1222
1223 /* hardware txpower limits ...
1224 * saturation (clipping distortion) txpowers are in half-dBm */
1225 if (band)
1226 saturation_power = priv->calib_info->saturation_power24;
1227 else
1228 saturation_power = priv->calib_info->saturation_power52;
1229
1230 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
1231 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
1232 if (band)
1233 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
1234 else
1235 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
1236 }
1237
1238 /* regulatory txpower limits ... reg_limit values are in half-dBm,
1239 * max_power_avg values are in dBm, convert * 2 */
1240 if (is_ht40)
1241 reg_limit = ch_info->ht40_max_power_avg * 2;
1242 else
1243 reg_limit = ch_info->max_power_avg * 2;
1244
1245 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
1246 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
1247 if (band)
1248 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
1249 else
1250 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
1251 }
1252
1253 /* Interpolate txpower calibration values for this channel,
1254 * based on factory calibration tests on spaced channels. */
1255 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
1256
1257 /* calculate tx gain adjustment based on power supply voltage */
1258 voltage = priv->calib_info->voltage;
1259 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
1260 voltage_compensation =
1261 iwl4965_get_voltage_compensation(voltage, init_voltage);
1262
1263 IWL_DEBUG_TXPOWER(priv, "curr volt %d eeprom volt %d volt comp %d\n",
1264 init_voltage,
1265 voltage, voltage_compensation);
1266
1267 /* get current temperature (Celsius) */
1268 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
1269 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
1270 current_temp = KELVIN_TO_CELSIUS(current_temp);
1271
1272 /* select thermal txpower adjustment params, based on channel group
1273 * (same frequency group used for mimo txatten adjustment) */
1274 degrees_per_05db_num =
1275 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
1276 degrees_per_05db_denom =
1277 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
1278
1279 /* get per-chain txpower values from factory measurements */
1280 for (c = 0; c < 2; c++) {
1281 measurement = &ch_eeprom_info.measurements[c][1];
1282
1283 /* txgain adjustment (in half-dB steps) based on difference
1284 * between factory and current temperature */
1285 factory_temp = measurement->temperature;
1286 iwl4965_math_div_round((current_temp - factory_temp) *
1287 degrees_per_05db_denom,
1288 degrees_per_05db_num,
1289 &temperature_comp[c]);
1290
1291 factory_gain_index[c] = measurement->gain_idx;
1292 factory_actual_pwr[c] = measurement->actual_pow;
1293
1294 IWL_DEBUG_TXPOWER(priv, "chain = %d\n", c);
1295 IWL_DEBUG_TXPOWER(priv, "fctry tmp %d, "
1296 "curr tmp %d, comp %d steps\n",
1297 factory_temp, current_temp,
1298 temperature_comp[c]);
1299
1300 IWL_DEBUG_TXPOWER(priv, "fctry idx %d, fctry pwr %d\n",
1301 factory_gain_index[c],
1302 factory_actual_pwr[c]);
1303 }
1304
1305 /* for each of 33 bit-rates (including 1 for CCK) */
1306 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
1307 u8 is_mimo_rate;
1308 union iwl4965_tx_power_dual_stream tx_power;
1309
1310 /* for mimo, reduce each chain's txpower by half
1311 * (3dB, 6 steps), so total output power is regulatory
1312 * compliant. */
1313 if (i & 0x8) {
1314 current_regulatory = reg_limit -
1315 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
1316 is_mimo_rate = 1;
1317 } else {
1318 current_regulatory = reg_limit;
1319 is_mimo_rate = 0;
1320 }
1321
1322 /* find txpower limit, either hardware or regulatory */
1323 power_limit = saturation_power - back_off_table[i];
1324 if (power_limit > current_regulatory)
1325 power_limit = current_regulatory;
1326
1327 /* reduce user's txpower request if necessary
1328 * for this rate on this channel */
1329 target_power = user_target_power;
1330 if (target_power > power_limit)
1331 target_power = power_limit;
1332
1333 IWL_DEBUG_TXPOWER(priv, "rate %d sat %d reg %d usr %d tgt %d\n",
1334 i, saturation_power - back_off_table[i],
1335 current_regulatory, user_target_power,
1336 target_power);
1337
1338 /* for each of 2 Tx chains (radio transmitters) */
1339 for (c = 0; c < 2; c++) {
1340 s32 atten_value;
1341
1342 if (is_mimo_rate)
1343 atten_value =
1344 (s32)le32_to_cpu(priv->card_alive_init.
1345 tx_atten[txatten_grp][c]);
1346 else
1347 atten_value = 0;
1348
1349 /* calculate index; higher index means lower txpower */
1350 power_index = (u8) (factory_gain_index[c] -
1351 (target_power -
1352 factory_actual_pwr[c]) -
1353 temperature_comp[c] -
1354 voltage_compensation +
1355 atten_value);
1356
1357 /* IWL_DEBUG_TXPOWER(priv, "calculated txpower index %d\n",
1358 power_index); */
1359
1360 if (power_index < get_min_power_index(i, band))
1361 power_index = get_min_power_index(i, band);
1362
1363 /* adjust 5 GHz index to support negative indexes */
1364 if (!band)
1365 power_index += 9;
1366
1367 /* CCK, rate 32, reduce txpower for CCK */
1368 if (i == POWER_TABLE_CCK_ENTRY)
1369 power_index +=
1370 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
1371
1372 /* stay within the table! */
1373 if (power_index > 107) {
1374 IWL_WARN(priv, "txpower index %d > 107\n",
1375 power_index);
1376 power_index = 107;
1377 }
1378 if (power_index < 0) {
1379 IWL_WARN(priv, "txpower index %d < 0\n",
1380 power_index);
1381 power_index = 0;
1382 }
1383
1384 /* fill txpower command for this rate/chain */
1385 tx_power.s.radio_tx_gain[c] =
1386 gain_table[band][power_index].radio;
1387 tx_power.s.dsp_predis_atten[c] =
1388 gain_table[band][power_index].dsp;
1389
1390 IWL_DEBUG_TXPOWER(priv, "chain %d mimo %d index %d "
1391 "gain 0x%02x dsp %d\n",
1392 c, atten_value, power_index,
1393 tx_power.s.radio_tx_gain[c],
1394 tx_power.s.dsp_predis_atten[c]);
1395 } /* for each chain */
1396
1397 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
1398
1399 } /* for each rate */
1400
1401 return 0;
1402 }
1403
1404 /**
1405 * iwl4965_send_tx_power - Configure the TXPOWER level user limit
1406 *
1407 * Uses the active RXON for channel, band, and characteristics (ht40, high)
1408 * The power limit is taken from priv->tx_power_user_lmt.
1409 */
1410 static int iwl4965_send_tx_power(struct iwl_priv *priv)
1411 {
1412 struct iwl4965_txpowertable_cmd cmd = { 0 };
1413 int ret;
1414 u8 band = 0;
1415 bool is_ht40 = false;
1416 u8 ctrl_chan_high = 0;
1417
1418 if (test_bit(STATUS_SCANNING, &priv->status)) {
1419 /* If this gets hit a lot, switch it to a BUG() and catch
1420 * the stack trace to find out who is calling this during
1421 * a scan. */
1422 IWL_WARN(priv, "TX Power requested while scanning!\n");
1423 return -EAGAIN;
1424 }
1425
1426 band = priv->band == IEEE80211_BAND_2GHZ;
1427
1428 is_ht40 = is_ht40_channel(priv->active_rxon.flags);
1429
1430 if (is_ht40 &&
1431 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1432 ctrl_chan_high = 1;
1433
1434 cmd.band = band;
1435 cmd.channel = priv->active_rxon.channel;
1436
1437 ret = iwl4965_fill_txpower_tbl(priv, band,
1438 le16_to_cpu(priv->active_rxon.channel),
1439 is_ht40, ctrl_chan_high, &cmd.tx_power);
1440 if (ret)
1441 goto out;
1442
1443 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
1444
1445 out:
1446 return ret;
1447 }
1448
1449 static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
1450 {
1451 int ret = 0;
1452 struct iwl4965_rxon_assoc_cmd rxon_assoc;
1453 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1454 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1455
1456 if ((rxon1->flags == rxon2->flags) &&
1457 (rxon1->filter_flags == rxon2->filter_flags) &&
1458 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1459 (rxon1->ofdm_ht_single_stream_basic_rates ==
1460 rxon2->ofdm_ht_single_stream_basic_rates) &&
1461 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1462 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1463 (rxon1->rx_chain == rxon2->rx_chain) &&
1464 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1465 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1466 return 0;
1467 }
1468
1469 rxon_assoc.flags = priv->staging_rxon.flags;
1470 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1471 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1472 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1473 rxon_assoc.reserved = 0;
1474 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1475 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1476 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1477 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1478 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1479
1480 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1481 sizeof(rxon_assoc), &rxon_assoc, NULL);
1482 if (ret)
1483 return ret;
1484
1485 return ret;
1486 }
1487
1488 #ifdef IEEE80211_CONF_CHANNEL_SWITCH
1489 static int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1490 {
1491 int rc;
1492 u8 band = 0;
1493 bool is_ht40 = false;
1494 u8 ctrl_chan_high = 0;
1495 struct iwl4965_channel_switch_cmd cmd = { 0 };
1496 const struct iwl_channel_info *ch_info;
1497
1498 band = priv->band == IEEE80211_BAND_2GHZ;
1499
1500 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1501
1502 is_ht40 = is_ht40_channel(priv->staging_rxon.flags);
1503
1504 if (is_ht40 &&
1505 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1506 ctrl_chan_high = 1;
1507
1508 cmd.band = band;
1509 cmd.expect_beacon = 0;
1510 cmd.channel = cpu_to_le16(channel);
1511 cmd.rxon_flags = priv->active_rxon.flags;
1512 cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
1513 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1514 if (ch_info)
1515 cmd.expect_beacon = is_channel_radar(ch_info);
1516 else
1517 cmd.expect_beacon = 1;
1518
1519 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_ht40,
1520 ctrl_chan_high, &cmd.tx_power);
1521 if (rc) {
1522 IWL_DEBUG_11H(priv, "error:%d fill txpower_tbl\n", rc);
1523 return rc;
1524 }
1525
1526 rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
1527 return rc;
1528 }
1529 #endif
1530
1531 /**
1532 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
1533 */
1534 static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
1535 struct iwl_tx_queue *txq,
1536 u16 byte_cnt)
1537 {
1538 struct iwl4965_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
1539 int txq_id = txq->q.id;
1540 int write_ptr = txq->q.write_ptr;
1541 int len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
1542 __le16 bc_ent;
1543
1544 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
1545
1546 bc_ent = cpu_to_le16(len & 0xFFF);
1547 /* Set up byte count within first 256 entries */
1548 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
1549
1550 /* If within first 64 entries, duplicate at end */
1551 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
1552 scd_bc_tbl[txq_id].
1553 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
1554 }
1555
1556 /**
1557 * sign_extend - Sign extend a value using specified bit as sign-bit
1558 *
1559 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
1560 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
1561 *
1562 * @param oper value to sign extend
1563 * @param index 0 based bit index (0<=index<32) to sign bit
1564 */
1565 static s32 sign_extend(u32 oper, int index)
1566 {
1567 u8 shift = 31 - index;
1568
1569 return (s32)(oper << shift) >> shift;
1570 }
1571
1572 /**
1573 * iwl4965_hw_get_temperature - return the calibrated temperature (in Kelvin)
1574 * @statistics: Provides the temperature reading from the uCode
1575 *
1576 * A return of <0 indicates bogus data in the statistics
1577 */
1578 static int iwl4965_hw_get_temperature(struct iwl_priv *priv)
1579 {
1580 s32 temperature;
1581 s32 vt;
1582 s32 R1, R2, R3;
1583 u32 R4;
1584
1585 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
1586 (priv->statistics.flag & STATISTICS_REPLY_FLG_HT40_MODE_MSK)) {
1587 IWL_DEBUG_TEMP(priv, "Running HT40 temperature calibration\n");
1588 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
1589 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
1590 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
1591 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
1592 } else {
1593 IWL_DEBUG_TEMP(priv, "Running temperature calibration\n");
1594 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
1595 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
1596 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
1597 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
1598 }
1599
1600 /*
1601 * Temperature is only 23 bits, so sign extend out to 32.
1602 *
1603 * NOTE If we haven't received a statistics notification yet
1604 * with an updated temperature, use R4 provided to us in the
1605 * "initialize" ALIVE response.
1606 */
1607 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
1608 vt = sign_extend(R4, 23);
1609 else
1610 vt = sign_extend(
1611 le32_to_cpu(priv->statistics.general.temperature), 23);
1612
1613 IWL_DEBUG_TEMP(priv, "Calib values R[1-3]: %d %d %d R4: %d\n", R1, R2, R3, vt);
1614
1615 if (R3 == R1) {
1616 IWL_ERR(priv, "Calibration conflict R1 == R3\n");
1617 return -1;
1618 }
1619
1620 /* Calculate temperature in degrees Kelvin, adjust by 97%.
1621 * Add offset to center the adjustment around 0 degrees Centigrade. */
1622 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
1623 temperature /= (R3 - R1);
1624 temperature = (temperature * 97) / 100 + TEMPERATURE_CALIB_KELVIN_OFFSET;
1625
1626 IWL_DEBUG_TEMP(priv, "Calibrated temperature: %dK, %dC\n",
1627 temperature, KELVIN_TO_CELSIUS(temperature));
1628
1629 return temperature;
1630 }
1631
1632 /* Adjust Txpower only if temperature variance is greater than threshold. */
1633 #define IWL_TEMPERATURE_THRESHOLD 3
1634
1635 /**
1636 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
1637 *
1638 * If the temperature changed has changed sufficiently, then a recalibration
1639 * is needed.
1640 *
1641 * Assumes caller will replace priv->last_temperature once calibration
1642 * executed.
1643 */
1644 static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
1645 {
1646 int temp_diff;
1647
1648 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
1649 IWL_DEBUG_TEMP(priv, "Temperature not updated -- no statistics.\n");
1650 return 0;
1651 }
1652
1653 temp_diff = priv->temperature - priv->last_temperature;
1654
1655 /* get absolute value */
1656 if (temp_diff < 0) {
1657 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d, \n", temp_diff);
1658 temp_diff = -temp_diff;
1659 } else if (temp_diff == 0)
1660 IWL_DEBUG_POWER(priv, "Same temp, \n");
1661 else
1662 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d, \n", temp_diff);
1663
1664 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
1665 IWL_DEBUG_POWER(priv, "Thermal txpower calib not needed\n");
1666 return 0;
1667 }
1668
1669 IWL_DEBUG_POWER(priv, "Thermal txpower calib needed\n");
1670
1671 return 1;
1672 }
1673
1674 static void iwl4965_temperature_calib(struct iwl_priv *priv)
1675 {
1676 s32 temp;
1677
1678 temp = iwl4965_hw_get_temperature(priv);
1679 if (temp < 0)
1680 return;
1681
1682 if (priv->temperature != temp) {
1683 if (priv->temperature)
1684 IWL_DEBUG_TEMP(priv, "Temperature changed "
1685 "from %dC to %dC\n",
1686 KELVIN_TO_CELSIUS(priv->temperature),
1687 KELVIN_TO_CELSIUS(temp));
1688 else
1689 IWL_DEBUG_TEMP(priv, "Temperature "
1690 "initialized to %dC\n",
1691 KELVIN_TO_CELSIUS(temp));
1692 }
1693
1694 priv->temperature = temp;
1695 iwl_tt_handler(priv);
1696 set_bit(STATUS_TEMPERATURE, &priv->status);
1697
1698 if (!priv->disable_tx_power_cal &&
1699 unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
1700 iwl4965_is_temp_calib_needed(priv))
1701 queue_work(priv->workqueue, &priv->txpower_work);
1702 }
1703
1704 /**
1705 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
1706 */
1707 static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
1708 u16 txq_id)
1709 {
1710 /* Simply stop the queue, but don't change any configuration;
1711 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1712 iwl_write_prph(priv,
1713 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
1714 (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1715 (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1716 }
1717
1718 /**
1719 * txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE
1720 * priv->lock must be held by the caller
1721 */
1722 static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1723 u16 ssn_idx, u8 tx_fifo)
1724 {
1725 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1726 (IWL49_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
1727 <= txq_id)) {
1728 IWL_WARN(priv,
1729 "queue number out of range: %d, must be %d to %d\n",
1730 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1731 IWL49_FIRST_AMPDU_QUEUE +
1732 priv->cfg->num_of_ampdu_queues - 1);
1733 return -EINVAL;
1734 }
1735
1736 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1737
1738 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
1739
1740 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1741 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1742 /* supposes that ssn_idx is valid (!= 0xFFF) */
1743 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1744
1745 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
1746 iwl_txq_ctx_deactivate(priv, txq_id);
1747 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1748
1749 return 0;
1750 }
1751
1752 /**
1753 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
1754 */
1755 static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
1756 u16 txq_id)
1757 {
1758 u32 tbl_dw_addr;
1759 u32 tbl_dw;
1760 u16 scd_q2ratid;
1761
1762 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1763
1764 tbl_dw_addr = priv->scd_base_addr +
1765 IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
1766
1767 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
1768
1769 if (txq_id & 0x1)
1770 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1771 else
1772 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1773
1774 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
1775
1776 return 0;
1777 }
1778
1779
1780 /**
1781 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
1782 *
1783 * NOTE: txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE,
1784 * i.e. it must be one of the higher queues used for aggregation
1785 */
1786 static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1787 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
1788 {
1789 unsigned long flags;
1790 u16 ra_tid;
1791
1792 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1793 (IWL49_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
1794 <= txq_id)) {
1795 IWL_WARN(priv,
1796 "queue number out of range: %d, must be %d to %d\n",
1797 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1798 IWL49_FIRST_AMPDU_QUEUE +
1799 priv->cfg->num_of_ampdu_queues - 1);
1800 return -EINVAL;
1801 }
1802
1803 ra_tid = BUILD_RAxTID(sta_id, tid);
1804
1805 /* Modify device's station table to Tx this TID */
1806 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
1807
1808 spin_lock_irqsave(&priv->lock, flags);
1809
1810 /* Stop this Tx queue before configuring it */
1811 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1812
1813 /* Map receiver-address / traffic-ID to this queue */
1814 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1815
1816 /* Set this queue as a chain-building queue */
1817 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
1818
1819 /* Place first TFD at index corresponding to start sequence number.
1820 * Assumes that ssn_idx is valid (!= 0xFFF) */
1821 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1822 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1823 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1824
1825 /* Set up Tx window size and frame limit for this queue */
1826 iwl_write_targ_mem(priv,
1827 priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
1828 (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1829 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
1830
1831 iwl_write_targ_mem(priv, priv->scd_base_addr +
1832 IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1833 (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
1834 & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1835
1836 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
1837
1838 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1839 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1840
1841 spin_unlock_irqrestore(&priv->lock, flags);
1842
1843 return 0;
1844 }
1845
1846
1847 static u16 iwl4965_get_hcmd_size(u8 cmd_id, u16 len)
1848 {
1849 switch (cmd_id) {
1850 case REPLY_RXON:
1851 return (u16) sizeof(struct iwl4965_rxon_cmd);
1852 default:
1853 return len;
1854 }
1855 }
1856
1857 static u16 iwl4965_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1858 {
1859 struct iwl4965_addsta_cmd *addsta = (struct iwl4965_addsta_cmd *)data;
1860 addsta->mode = cmd->mode;
1861 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
1862 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
1863 addsta->station_flags = cmd->station_flags;
1864 addsta->station_flags_msk = cmd->station_flags_msk;
1865 addsta->tid_disable_tx = cmd->tid_disable_tx;
1866 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
1867 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
1868 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
1869 addsta->reserved1 = cpu_to_le16(0);
1870 addsta->reserved2 = cpu_to_le32(0);
1871
1872 return (u16)sizeof(struct iwl4965_addsta_cmd);
1873 }
1874
1875 static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp)
1876 {
1877 return le32_to_cpup(&tx_resp->u.status + tx_resp->frame_count) & MAX_SN;
1878 }
1879
1880 /**
1881 * iwl4965_tx_status_reply_tx - Handle Tx response for frames in aggregation queue
1882 */
1883 static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv,
1884 struct iwl_ht_agg *agg,
1885 struct iwl4965_tx_resp *tx_resp,
1886 int txq_id, u16 start_idx)
1887 {
1888 u16 status;
1889 struct agg_tx_status *frame_status = tx_resp->u.agg_status;
1890 struct ieee80211_tx_info *info = NULL;
1891 struct ieee80211_hdr *hdr = NULL;
1892 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1893 int i, sh, idx;
1894 u16 seq;
1895 if (agg->wait_for_ba)
1896 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
1897
1898 agg->frame_count = tx_resp->frame_count;
1899 agg->start_idx = start_idx;
1900 agg->rate_n_flags = rate_n_flags;
1901 agg->bitmap = 0;
1902
1903 /* num frames attempted by Tx command */
1904 if (agg->frame_count == 1) {
1905 /* Only one frame was attempted; no block-ack will arrive */
1906 status = le16_to_cpu(frame_status[0].status);
1907 idx = start_idx;
1908
1909 /* FIXME: code repetition */
1910 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
1911 agg->frame_count, agg->start_idx, idx);
1912
1913 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1914 info->status.rates[0].count = tx_resp->failure_frame + 1;
1915 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1916 info->flags |= iwl_is_tx_success(status) ?
1917 IEEE80211_TX_STAT_ACK : 0;
1918 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1919 /* FIXME: code repetition end */
1920
1921 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
1922 status & 0xff, tx_resp->failure_frame);
1923 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
1924
1925 agg->wait_for_ba = 0;
1926 } else {
1927 /* Two or more frames were attempted; expect block-ack */
1928 u64 bitmap = 0;
1929 int start = agg->start_idx;
1930
1931 /* Construct bit-map of pending frames within Tx window */
1932 for (i = 0; i < agg->frame_count; i++) {
1933 u16 sc;
1934 status = le16_to_cpu(frame_status[i].status);
1935 seq = le16_to_cpu(frame_status[i].sequence);
1936 idx = SEQ_TO_INDEX(seq);
1937 txq_id = SEQ_TO_QUEUE(seq);
1938
1939 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1940 AGG_TX_STATE_ABORT_MSK))
1941 continue;
1942
1943 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1944 agg->frame_count, txq_id, idx);
1945
1946 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1947 if (!hdr) {
1948 IWL_ERR(priv,
1949 "BUG_ON idx doesn't point to valid skb"
1950 " idx=%d, txq_id=%d\n", idx, txq_id);
1951 return -1;
1952 }
1953
1954 sc = le16_to_cpu(hdr->seq_ctrl);
1955 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1956 IWL_ERR(priv,
1957 "BUG_ON idx doesn't match seq control"
1958 " idx=%d, seq_idx=%d, seq=%d\n",
1959 idx, SEQ_TO_SN(sc), hdr->seq_ctrl);
1960 return -1;
1961 }
1962
1963 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
1964 i, idx, SEQ_TO_SN(sc));
1965
1966 sh = idx - start;
1967 if (sh > 64) {
1968 sh = (start - idx) + 0xff;
1969 bitmap = bitmap << sh;
1970 sh = 0;
1971 start = idx;
1972 } else if (sh < -64)
1973 sh = 0xff - (start - idx);
1974 else if (sh < 0) {
1975 sh = start - idx;
1976 start = idx;
1977 bitmap = bitmap << sh;
1978 sh = 0;
1979 }
1980 bitmap |= 1ULL << sh;
1981 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
1982 start, (unsigned long long)bitmap);
1983 }
1984
1985 agg->bitmap = bitmap;
1986 agg->start_idx = start;
1987 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
1988 agg->frame_count, agg->start_idx,
1989 (unsigned long long)agg->bitmap);
1990
1991 if (bitmap)
1992 agg->wait_for_ba = 1;
1993 }
1994 return 0;
1995 }
1996
1997 /**
1998 * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response
1999 */
2000 static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
2001 struct iwl_rx_mem_buffer *rxb)
2002 {
2003 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2004 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
2005 int txq_id = SEQ_TO_QUEUE(sequence);
2006 int index = SEQ_TO_INDEX(sequence);
2007 struct iwl_tx_queue *txq = &priv->txq[txq_id];
2008 struct ieee80211_hdr *hdr;
2009 struct ieee80211_tx_info *info;
2010 struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
2011 u32 status = le32_to_cpu(tx_resp->u.status);
2012 int tid = MAX_TID_COUNT;
2013 int sta_id;
2014 int freed;
2015 u8 *qc = NULL;
2016
2017 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
2018 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
2019 "is out of range [0-%d] %d %d\n", txq_id,
2020 index, txq->q.n_bd, txq->q.write_ptr,
2021 txq->q.read_ptr);
2022 return;
2023 }
2024
2025 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
2026 memset(&info->status, 0, sizeof(info->status));
2027
2028 hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
2029 if (ieee80211_is_data_qos(hdr->frame_control)) {
2030 qc = ieee80211_get_qos_ctl(hdr);
2031 tid = qc[0] & 0xf;
2032 }
2033
2034 sta_id = iwl_get_ra_sta_id(priv, hdr);
2035 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
2036 IWL_ERR(priv, "Station not known\n");
2037 return;
2038 }
2039
2040 if (txq->sched_retry) {
2041 const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp);
2042 struct iwl_ht_agg *agg = NULL;
2043
2044 WARN_ON(!qc);
2045
2046 agg = &priv->stations[sta_id].tid[tid].agg;
2047
2048 iwl4965_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
2049
2050 /* check if BAR is needed */
2051 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
2052 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
2053
2054 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
2055 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
2056 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim scd_ssn "
2057 "%d index %d\n", scd_ssn , index);
2058 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
2059 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
2060
2061 if (priv->mac80211_registered &&
2062 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
2063 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
2064 if (agg->state == IWL_AGG_OFF)
2065 iwl_wake_queue(priv, txq_id);
2066 else
2067 iwl_wake_queue(priv, txq->swq_id);
2068 }
2069 }
2070 } else {
2071 info->status.rates[0].count = tx_resp->failure_frame + 1;
2072 info->flags |= iwl_is_tx_success(status) ?
2073 IEEE80211_TX_STAT_ACK : 0;
2074 iwl_hwrate_to_tx_control(priv,
2075 le32_to_cpu(tx_resp->rate_n_flags),
2076 info);
2077
2078 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) "
2079 "rate_n_flags 0x%x retries %d\n",
2080 txq_id,
2081 iwl_get_tx_fail_reason(status), status,
2082 le32_to_cpu(tx_resp->rate_n_flags),
2083 tx_resp->failure_frame);
2084
2085 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
2086 if (qc && likely(sta_id != IWL_INVALID_STATION))
2087 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
2088
2089 if (priv->mac80211_registered &&
2090 (iwl_queue_space(&txq->q) > txq->q.low_mark))
2091 iwl_wake_queue(priv, txq_id);
2092 }
2093
2094 if (qc && likely(sta_id != IWL_INVALID_STATION))
2095 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
2096
2097 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
2098 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
2099 }
2100
2101 static int iwl4965_calc_rssi(struct iwl_priv *priv,
2102 struct iwl_rx_phy_res *rx_resp)
2103 {
2104 /* data from PHY/DSP regarding signal strength, etc.,
2105 * contents are always there, not configurable by host. */
2106 struct iwl4965_rx_non_cfg_phy *ncphy =
2107 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
2108 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL49_AGC_DB_MASK)
2109 >> IWL49_AGC_DB_POS;
2110
2111 u32 valid_antennae =
2112 (le16_to_cpu(rx_resp->phy_flags) & IWL49_RX_PHY_FLAGS_ANTENNAE_MASK)
2113 >> IWL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
2114 u8 max_rssi = 0;
2115 u32 i;
2116
2117 /* Find max rssi among 3 possible receivers.
2118 * These values are measured by the digital signal processor (DSP).
2119 * They should stay fairly constant even as the signal strength varies,
2120 * if the radio's automatic gain control (AGC) is working right.
2121 * AGC value (see below) will provide the "interesting" info. */
2122 for (i = 0; i < 3; i++)
2123 if (valid_antennae & (1 << i))
2124 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
2125
2126 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
2127 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
2128 max_rssi, agc);
2129
2130 /* dBm = max_rssi dB - agc dB - constant.
2131 * Higher AGC (higher radio gain) means lower signal. */
2132 return max_rssi - agc - IWL49_RSSI_OFFSET;
2133 }
2134
2135
2136 /* Set up 4965-specific Rx frame reply handlers */
2137 static void iwl4965_rx_handler_setup(struct iwl_priv *priv)
2138 {
2139 /* Legacy Rx frames */
2140 priv->rx_handlers[REPLY_RX] = iwl_rx_reply_rx;
2141 /* Tx response */
2142 priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx;
2143 }
2144
2145 static void iwl4965_setup_deferred_work(struct iwl_priv *priv)
2146 {
2147 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
2148 }
2149
2150 static void iwl4965_cancel_deferred_work(struct iwl_priv *priv)
2151 {
2152 cancel_work_sync(&priv->txpower_work);
2153 }
2154
2155 #define IWL4965_UCODE_GET(item) \
2156 static u32 iwl4965_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2157 u32 api_ver) \
2158 { \
2159 return le32_to_cpu(ucode->u.v1.item); \
2160 }
2161
2162 static u32 iwl4965_ucode_get_header_size(u32 api_ver)
2163 {
2164 return UCODE_HEADER_SIZE(1);
2165 }
2166 static u32 iwl4965_ucode_get_build(const struct iwl_ucode_header *ucode,
2167 u32 api_ver)
2168 {
2169 return 0;
2170 }
2171 static u8 *iwl4965_ucode_get_data(const struct iwl_ucode_header *ucode,
2172 u32 api_ver)
2173 {
2174 return (u8 *) ucode->u.v1.data;
2175 }
2176
2177 IWL4965_UCODE_GET(inst_size);
2178 IWL4965_UCODE_GET(data_size);
2179 IWL4965_UCODE_GET(init_size);
2180 IWL4965_UCODE_GET(init_data_size);
2181 IWL4965_UCODE_GET(boot_size);
2182
2183 static struct iwl_hcmd_ops iwl4965_hcmd = {
2184 .rxon_assoc = iwl4965_send_rxon_assoc,
2185 .commit_rxon = iwl_commit_rxon,
2186 .set_rxon_chain = iwl_set_rxon_chain,
2187 };
2188
2189 static struct iwl_ucode_ops iwl4965_ucode = {
2190 .get_header_size = iwl4965_ucode_get_header_size,
2191 .get_build = iwl4965_ucode_get_build,
2192 .get_inst_size = iwl4965_ucode_get_inst_size,
2193 .get_data_size = iwl4965_ucode_get_data_size,
2194 .get_init_size = iwl4965_ucode_get_init_size,
2195 .get_init_data_size = iwl4965_ucode_get_init_data_size,
2196 .get_boot_size = iwl4965_ucode_get_boot_size,
2197 .get_data = iwl4965_ucode_get_data,
2198 };
2199 static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
2200 .get_hcmd_size = iwl4965_get_hcmd_size,
2201 .build_addsta_hcmd = iwl4965_build_addsta_hcmd,
2202 .chain_noise_reset = iwl4965_chain_noise_reset,
2203 .gain_computation = iwl4965_gain_computation,
2204 .rts_tx_cmd_flag = iwlcore_rts_tx_cmd_flag,
2205 .calc_rssi = iwl4965_calc_rssi,
2206 };
2207
2208 static struct iwl_lib_ops iwl4965_lib = {
2209 .set_hw_params = iwl4965_hw_set_hw_params,
2210 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
2211 .txq_set_sched = iwl4965_txq_set_sched,
2212 .txq_agg_enable = iwl4965_txq_agg_enable,
2213 .txq_agg_disable = iwl4965_txq_agg_disable,
2214 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
2215 .txq_free_tfd = iwl_hw_txq_free_tfd,
2216 .txq_init = iwl_hw_tx_queue_init,
2217 .rx_handler_setup = iwl4965_rx_handler_setup,
2218 .setup_deferred_work = iwl4965_setup_deferred_work,
2219 .cancel_deferred_work = iwl4965_cancel_deferred_work,
2220 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
2221 .alive_notify = iwl4965_alive_notify,
2222 .init_alive_start = iwl4965_init_alive_start,
2223 .load_ucode = iwl4965_load_bsm,
2224 .dump_nic_event_log = iwl_dump_nic_event_log,
2225 .dump_nic_error_log = iwl_dump_nic_error_log,
2226 .apm_ops = {
2227 .init = iwl4965_apm_init,
2228 .stop = iwl_apm_stop,
2229 .config = iwl4965_nic_config,
2230 .set_pwr_src = iwl_set_pwr_src,
2231 },
2232 .eeprom_ops = {
2233 .regulatory_bands = {
2234 EEPROM_REGULATORY_BAND_1_CHANNELS,
2235 EEPROM_REGULATORY_BAND_2_CHANNELS,
2236 EEPROM_REGULATORY_BAND_3_CHANNELS,
2237 EEPROM_REGULATORY_BAND_4_CHANNELS,
2238 EEPROM_REGULATORY_BAND_5_CHANNELS,
2239 EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS,
2240 EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS
2241 },
2242 .verify_signature = iwlcore_eeprom_verify_signature,
2243 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
2244 .release_semaphore = iwlcore_eeprom_release_semaphore,
2245 .calib_version = iwl4965_eeprom_calib_version,
2246 .query_addr = iwlcore_eeprom_query_addr,
2247 },
2248 .send_tx_power = iwl4965_send_tx_power,
2249 .update_chain_flags = iwl_update_chain_flags,
2250 .post_associate = iwl_post_associate,
2251 .config_ap = iwl_config_ap,
2252 .isr = iwl_isr_legacy,
2253 .temp_ops = {
2254 .temperature = iwl4965_temperature_calib,
2255 .set_ct_kill = iwl4965_set_ct_threshold,
2256 },
2257 };
2258
2259 static struct iwl_ops iwl4965_ops = {
2260 .ucode = &iwl4965_ucode,
2261 .lib = &iwl4965_lib,
2262 .hcmd = &iwl4965_hcmd,
2263 .utils = &iwl4965_hcmd_utils,
2264 .led = &iwlagn_led_ops,
2265 };
2266
2267 struct iwl_cfg iwl4965_agn_cfg = {
2268 .name = "4965AGN",
2269 .fw_name_pre = IWL4965_FW_PRE,
2270 .ucode_api_max = IWL4965_UCODE_API_MAX,
2271 .ucode_api_min = IWL4965_UCODE_API_MIN,
2272 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
2273 .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
2274 .eeprom_ver = EEPROM_4965_EEPROM_VERSION,
2275 .eeprom_calib_ver = EEPROM_4965_TX_POWER_VERSION,
2276 .ops = &iwl4965_ops,
2277 .num_of_queues = IWL49_NUM_QUEUES,
2278 .num_of_ampdu_queues = IWL49_NUM_AMPDU_QUEUES,
2279 .mod_params = &iwl4965_mod_params,
2280 .use_isr_legacy = true,
2281 .ht_greenfield_support = false,
2282 .broken_powersave = true,
2283 .led_compensation = 61,
2284 .chain_noise_num_beacons = IWL4965_CAL_NUM_BEACONS,
2285 };
2286
2287 /* Module firmware */
2288 MODULE_FIRMWARE(IWL4965_MODULE_FIRMWARE(IWL4965_UCODE_API_MAX));
2289
2290 module_param_named(antenna, iwl4965_mod_params.antenna, int, S_IRUGO);
2291 MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
2292 module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, S_IRUGO);
2293 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
2294 module_param_named(
2295 disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, S_IRUGO);
2296 MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
2297
2298 module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, S_IRUGO);
2299 MODULE_PARM_DESC(queues_num, "number of hw queues.");
2300 /* 11n */
2301 module_param_named(11n_disable, iwl4965_mod_params.disable_11n, int, S_IRUGO);
2302 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
2303 module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K,
2304 int, S_IRUGO);
2305 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
2306
2307 module_param_named(fw_restart4965, iwl4965_mod_params.restart_fw, int, S_IRUGO);
2308 MODULE_PARM_DESC(fw_restart4965, "restart firmware in case of error");
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