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On Tue, Nov 06, 2007 at 02:33:53AM -0800, akpm@linux-foundation.org wrote:
[mmotm.git] / drivers / net / wireless / iwlwifi / iwl-5000.c
blob955116542717750736bf64ef2d117c1ef3e572c5
1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 *
24 *****************************************************************************/
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/pci.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/sched.h>
33 #include <linux/skbuff.h>
34 #include <linux/netdevice.h>
35 #include <linux/wireless.h>
36 #include <net/mac80211.h>
37 #include <linux/etherdevice.h>
38 #include <asm/unaligned.h>
39
40 #include "iwl-eeprom.h"
41 #include "iwl-dev.h"
42 #include "iwl-core.h"
43 #include "iwl-io.h"
44 #include "iwl-sta.h"
45 #include "iwl-helpers.h"
46 #include "iwl-agn-led.h"
47 #include "iwl-5000-hw.h"
48 #include "iwl-6000-hw.h"
49
50 /* Highest firmware API version supported */
51 #define IWL5000_UCODE_API_MAX 2
52 #define IWL5150_UCODE_API_MAX 2
53
54 /* Lowest firmware API version supported */
55 #define IWL5000_UCODE_API_MIN 1
56 #define IWL5150_UCODE_API_MIN 1
57
58 #define IWL5000_FW_PRE "iwlwifi-5000-"
59 #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
60 #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
61
62 #define IWL5150_FW_PRE "iwlwifi-5150-"
63 #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
64 #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
65
66 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
67 IWL_TX_FIFO_AC3,
68 IWL_TX_FIFO_AC2,
69 IWL_TX_FIFO_AC1,
70 IWL_TX_FIFO_AC0,
71 IWL50_CMD_FIFO_NUM,
72 IWL_TX_FIFO_HCCA_1,
73 IWL_TX_FIFO_HCCA_2
74 };
75
76 int iwl5000_apm_init(struct iwl_priv *priv)
77 {
78 int ret = 0;
79
80 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
81 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
82
83 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
84 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
85 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
86
87 /* Set FH wait threshold to maximum (HW error during stress W/A) */
88 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
89
90 /* enable HAP INTA to move device L1a -> L0s */
91 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
92 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
93
94 if (priv->cfg->need_pll_cfg)
95 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
96
97 /* set "initialization complete" bit to move adapter
98 * D0U* --> D0A* state */
99 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
100
101 /* wait for clock stabilization */
102 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
103 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
104 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
105 if (ret < 0) {
106 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
107 return ret;
108 }
109
110 /* enable DMA */
111 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
112
113 udelay(20);
114
115 /* disable L1-Active */
116 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
117 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
118
119 return ret;
120 }
121
122 /* NIC configuration for 5000 series */
123 void iwl5000_nic_config(struct iwl_priv *priv)
124 {
125 unsigned long flags;
126 u16 radio_cfg;
127 u16 lctl;
128
129 spin_lock_irqsave(&priv->lock, flags);
130
131 lctl = iwl_pcie_link_ctl(priv);
132
133 /* HW bug W/A */
134 /* L1-ASPM is enabled by BIOS */
135 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
136 /* L1-APSM enabled: disable L0S */
137 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
138 else
139 /* L1-ASPM disabled: enable L0S */
140 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
141
142 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
143
144 /* write radio config values to register */
145 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_RF_CONFIG_TYPE_MAX)
146 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
147 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
148 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
149 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
150
151 /* set CSR_HW_CONFIG_REG for uCode use */
152 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
153 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
154 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
155
156 /* W/A : NIC is stuck in a reset state after Early PCIe power off
157 * (PCIe power is lost before PERST# is asserted),
158 * causing ME FW to lose ownership and not being able to obtain it back.
159 */
160 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
161 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
162 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
163
164
165 spin_unlock_irqrestore(&priv->lock, flags);
166 }
167
168
169 /*
170 * EEPROM
171 */
172 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
173 {
174 u16 offset = 0;
175
176 if ((address & INDIRECT_ADDRESS) == 0)
177 return address;
178
179 switch (address & INDIRECT_TYPE_MSK) {
180 case INDIRECT_HOST:
181 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
182 break;
183 case INDIRECT_GENERAL:
184 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
185 break;
186 case INDIRECT_REGULATORY:
187 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
188 break;
189 case INDIRECT_CALIBRATION:
190 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
191 break;
192 case INDIRECT_PROCESS_ADJST:
193 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
194 break;
195 case INDIRECT_OTHERS:
196 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
197 break;
198 default:
199 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
200 address & INDIRECT_TYPE_MSK);
201 break;
202 }
203
204 /* translate the offset from words to byte */
205 return (address & ADDRESS_MSK) + (offset << 1);
206 }
207
208 u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
209 {
210 struct iwl_eeprom_calib_hdr {
211 u8 version;
212 u8 pa_type;
213 u16 voltage;
214 } *hdr;
215
216 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
217 EEPROM_5000_CALIB_ALL);
218 return hdr->version;
219
220 }
221
222 static void iwl5000_gain_computation(struct iwl_priv *priv,
223 u32 average_noise[NUM_RX_CHAINS],
224 u16 min_average_noise_antenna_i,
225 u32 min_average_noise,
226 u8 default_chain)
227 {
228 int i;
229 s32 delta_g;
230 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
231
232 /*
233 * Find Gain Code for the chains based on "default chain"
234 */
235 for (i = default_chain + 1; i < NUM_RX_CHAINS; i++) {
236 if ((data->disconn_array[i])) {
237 data->delta_gain_code[i] = 0;
238 continue;
239 }
240 delta_g = (1000 * ((s32)average_noise[0] -
241 (s32)average_noise[i])) / 1500;
242 /* bound gain by 2 bits value max, 3rd bit is sign */
243 data->delta_gain_code[i] =
244 min(abs(delta_g), (long) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
245
246 if (delta_g < 0)
247 /* set negative sign */
248 data->delta_gain_code[i] |= (1 << 2);
249 }
250
251 IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d ANT_C = %d\n",
252 data->delta_gain_code[1], data->delta_gain_code[2]);
253
254 if (!data->radio_write) {
255 struct iwl_calib_chain_noise_gain_cmd cmd;
256
257 memset(&cmd, 0, sizeof(cmd));
258
259 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
260 cmd.hdr.first_group = 0;
261 cmd.hdr.groups_num = 1;
262 cmd.hdr.data_valid = 1;
263 cmd.delta_gain_1 = data->delta_gain_code[1];
264 cmd.delta_gain_2 = data->delta_gain_code[2];
265 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
266 sizeof(cmd), &cmd, NULL);
267
268 data->radio_write = 1;
269 data->state = IWL_CHAIN_NOISE_CALIBRATED;
270 }
271
272 data->chain_noise_a = 0;
273 data->chain_noise_b = 0;
274 data->chain_noise_c = 0;
275 data->chain_signal_a = 0;
276 data->chain_signal_b = 0;
277 data->chain_signal_c = 0;
278 data->beacon_count = 0;
279 }
280
281 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
282 {
283 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
284 int ret;
285
286 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
287 struct iwl_calib_chain_noise_reset_cmd cmd;
288 memset(&cmd, 0, sizeof(cmd));
289
290 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
291 cmd.hdr.first_group = 0;
292 cmd.hdr.groups_num = 1;
293 cmd.hdr.data_valid = 1;
294 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
295 sizeof(cmd), &cmd);
296 if (ret)
297 IWL_ERR(priv,
298 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
299 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
300 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
301 }
302 }
303
304 void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
305 __le32 *tx_flags)
306 {
307 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
308 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
309 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
310 else
311 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
312 }
313
314 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
315 .min_nrg_cck = 95,
316 .max_nrg_cck = 0, /* not used, set to 0 */
317 .auto_corr_min_ofdm = 90,
318 .auto_corr_min_ofdm_mrc = 170,
319 .auto_corr_min_ofdm_x1 = 120,
320 .auto_corr_min_ofdm_mrc_x1 = 240,
321
322 .auto_corr_max_ofdm = 120,
323 .auto_corr_max_ofdm_mrc = 210,
324 .auto_corr_max_ofdm_x1 = 155,
325 .auto_corr_max_ofdm_mrc_x1 = 290,
326
327 .auto_corr_min_cck = 125,
328 .auto_corr_max_cck = 200,
329 .auto_corr_min_cck_mrc = 170,
330 .auto_corr_max_cck_mrc = 400,
331 .nrg_th_cck = 95,
332 .nrg_th_ofdm = 95,
333
334 .barker_corr_th_min = 190,
335 .barker_corr_th_min_mrc = 390,
336 .nrg_th_cca = 62,
337 };
338
339 static struct iwl_sensitivity_ranges iwl5150_sensitivity = {
340 .min_nrg_cck = 95,
341 .max_nrg_cck = 0, /* not used, set to 0 */
342 .auto_corr_min_ofdm = 90,
343 .auto_corr_min_ofdm_mrc = 170,
344 .auto_corr_min_ofdm_x1 = 105,
345 .auto_corr_min_ofdm_mrc_x1 = 220,
346
347 .auto_corr_max_ofdm = 120,
348 .auto_corr_max_ofdm_mrc = 210,
349 /* max = min for performance bug in 5150 DSP */
350 .auto_corr_max_ofdm_x1 = 105,
351 .auto_corr_max_ofdm_mrc_x1 = 220,
352
353 .auto_corr_min_cck = 125,
354 .auto_corr_max_cck = 200,
355 .auto_corr_min_cck_mrc = 170,
356 .auto_corr_max_cck_mrc = 400,
357 .nrg_th_cck = 95,
358 .nrg_th_ofdm = 95,
359
360 .barker_corr_th_min = 190,
361 .barker_corr_th_min_mrc = 390,
362 .nrg_th_cca = 62,
363 };
364
365 const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
366 size_t offset)
367 {
368 u32 address = eeprom_indirect_address(priv, offset);
369 BUG_ON(address >= priv->cfg->eeprom_size);
370 return &priv->eeprom[address];
371 }
372
373 static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
374 {
375 const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
376 s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) -
377 iwl_temp_calib_to_offset(priv);
378
379 priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
380 }
381
382 static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
383 {
384 /* want Celsius */
385 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
386 }
387
388 /*
389 * Calibration
390 */
391 static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
392 {
393 struct iwl_calib_xtal_freq_cmd cmd;
394 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
395
396 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
397 cmd.hdr.first_group = 0;
398 cmd.hdr.groups_num = 1;
399 cmd.hdr.data_valid = 1;
400 cmd.cap_pin1 = (u8)xtal_calib[0];
401 cmd.cap_pin2 = (u8)xtal_calib[1];
402 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
403 (u8 *)&cmd, sizeof(cmd));
404 }
405
406 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
407 {
408 struct iwl_calib_cfg_cmd calib_cfg_cmd;
409 struct iwl_host_cmd cmd = {
410 .id = CALIBRATION_CFG_CMD,
411 .len = sizeof(struct iwl_calib_cfg_cmd),
412 .data = &calib_cfg_cmd,
413 };
414
415 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
416 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
417 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
418 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
419 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
420
421 return iwl_send_cmd(priv, &cmd);
422 }
423
424 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
425 struct iwl_rx_mem_buffer *rxb)
426 {
427 struct iwl_rx_packet *pkt = rxb_addr(rxb);
428 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
429 int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
430 int index;
431
432 /* reduce the size of the length field itself */
433 len -= 4;
434
435 /* Define the order in which the results will be sent to the runtime
436 * uCode. iwl_send_calib_results sends them in a row according to their
437 * index. We sort them here */
438 switch (hdr->op_code) {
439 case IWL_PHY_CALIBRATE_DC_CMD:
440 index = IWL_CALIB_DC;
441 break;
442 case IWL_PHY_CALIBRATE_LO_CMD:
443 index = IWL_CALIB_LO;
444 break;
445 case IWL_PHY_CALIBRATE_TX_IQ_CMD:
446 index = IWL_CALIB_TX_IQ;
447 break;
448 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
449 index = IWL_CALIB_TX_IQ_PERD;
450 break;
451 case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
452 index = IWL_CALIB_BASE_BAND;
453 break;
454 default:
455 IWL_ERR(priv, "Unknown calibration notification %d\n",
456 hdr->op_code);
457 return;
458 }
459 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
460 }
461
462 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
463 struct iwl_rx_mem_buffer *rxb)
464 {
465 IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
466 queue_work(priv->workqueue, &priv->restart);
467 }
468
469 /*
470 * ucode
471 */
472 static int iwl5000_load_section(struct iwl_priv *priv,
473 struct fw_desc *image,
474 u32 dst_addr)
475 {
476 dma_addr_t phy_addr = image->p_addr;
477 u32 byte_cnt = image->len;
478
479 iwl_write_direct32(priv,
480 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
481 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
482
483 iwl_write_direct32(priv,
484 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
485
486 iwl_write_direct32(priv,
487 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
488 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
489
490 iwl_write_direct32(priv,
491 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
492 (iwl_get_dma_hi_addr(phy_addr)
493 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
494
495 iwl_write_direct32(priv,
496 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
497 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
498 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
499 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
500
501 iwl_write_direct32(priv,
502 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
503 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
504 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
505 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
506
507 return 0;
508 }
509
510 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
511 struct fw_desc *inst_image,
512 struct fw_desc *data_image)
513 {
514 int ret = 0;
515
516 ret = iwl5000_load_section(priv, inst_image,
517 IWL50_RTC_INST_LOWER_BOUND);
518 if (ret)
519 return ret;
520
521 IWL_DEBUG_INFO(priv, "INST uCode section being loaded...\n");
522 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
523 priv->ucode_write_complete, 5 * HZ);
524 if (ret == -ERESTARTSYS) {
525 IWL_ERR(priv, "Could not load the INST uCode section due "
526 "to interrupt\n");
527 return ret;
528 }
529 if (!ret) {
530 IWL_ERR(priv, "Could not load the INST uCode section\n");
531 return -ETIMEDOUT;
532 }
533
534 priv->ucode_write_complete = 0;
535
536 ret = iwl5000_load_section(
537 priv, data_image, IWL50_RTC_DATA_LOWER_BOUND);
538 if (ret)
539 return ret;
540
541 IWL_DEBUG_INFO(priv, "DATA uCode section being loaded...\n");
542
543 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
544 priv->ucode_write_complete, 5 * HZ);
545 if (ret == -ERESTARTSYS) {
546 IWL_ERR(priv, "Could not load the INST uCode section due "
547 "to interrupt\n");
548 return ret;
549 } else if (!ret) {
550 IWL_ERR(priv, "Could not load the DATA uCode section\n");
551 return -ETIMEDOUT;
552 } else
553 ret = 0;
554
555 priv->ucode_write_complete = 0;
556
557 return ret;
558 }
559
560 int iwl5000_load_ucode(struct iwl_priv *priv)
561 {
562 int ret = 0;
563
564 /* check whether init ucode should be loaded, or rather runtime ucode */
565 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
566 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
567 ret = iwl5000_load_given_ucode(priv,
568 &priv->ucode_init, &priv->ucode_init_data);
569 if (!ret) {
570 IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
571 priv->ucode_type = UCODE_INIT;
572 }
573 } else {
574 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
575 "Loading runtime ucode...\n");
576 ret = iwl5000_load_given_ucode(priv,
577 &priv->ucode_code, &priv->ucode_data);
578 if (!ret) {
579 IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
580 priv->ucode_type = UCODE_RT;
581 }
582 }
583
584 return ret;
585 }
586
587 void iwl5000_init_alive_start(struct iwl_priv *priv)
588 {
589 int ret = 0;
590
591 /* Check alive response for "valid" sign from uCode */
592 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
593 /* We had an error bringing up the hardware, so take it
594 * all the way back down so we can try again */
595 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
596 goto restart;
597 }
598
599 /* initialize uCode was loaded... verify inst image.
600 * This is a paranoid check, because we would not have gotten the
601 * "initialize" alive if code weren't properly loaded. */
602 if (iwl_verify_ucode(priv)) {
603 /* Runtime instruction load was bad;
604 * take it all the way back down so we can try again */
605 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
606 goto restart;
607 }
608
609 iwl_clear_stations_table(priv);
610 ret = priv->cfg->ops->lib->alive_notify(priv);
611 if (ret) {
612 IWL_WARN(priv,
613 "Could not complete ALIVE transition: %d\n", ret);
614 goto restart;
615 }
616
617 iwl5000_send_calib_cfg(priv);
618 return;
619
620 restart:
621 /* real restart (first load init_ucode) */
622 queue_work(priv->workqueue, &priv->restart);
623 }
624
625 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
626 int txq_id, u32 index)
627 {
628 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
629 (index & 0xff) | (txq_id << 8));
630 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
631 }
632
633 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
634 struct iwl_tx_queue *txq,
635 int tx_fifo_id, int scd_retry)
636 {
637 int txq_id = txq->q.id;
638 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
639
640 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
641 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
642 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
643 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
644 IWL50_SCD_QUEUE_STTS_REG_MSK);
645
646 txq->sched_retry = scd_retry;
647
648 IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
649 active ? "Activate" : "Deactivate",
650 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
651 }
652
653 static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
654 {
655 struct iwl_wimax_coex_cmd coex_cmd;
656
657 memset(&coex_cmd, 0, sizeof(coex_cmd));
658
659 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
660 sizeof(coex_cmd), &coex_cmd);
661 }
662
663 int iwl5000_alive_notify(struct iwl_priv *priv)
664 {
665 u32 a;
666 unsigned long flags;
667 int i, chan;
668 u32 reg_val;
669
670 spin_lock_irqsave(&priv->lock, flags);
671
672 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
673 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
674 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
675 a += 4)
676 iwl_write_targ_mem(priv, a, 0);
677 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
678 a += 4)
679 iwl_write_targ_mem(priv, a, 0);
680 for (; a < priv->scd_base_addr +
681 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
682 iwl_write_targ_mem(priv, a, 0);
683
684 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
685 priv->scd_bc_tbls.dma >> 10);
686
687 /* Enable DMA channel */
688 for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
689 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
690 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
691 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
692
693 /* Update FH chicken bits */
694 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
695 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
696 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
697
698 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
699 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
700 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
701
702 /* initiate the queues */
703 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
704 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
705 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
706 iwl_write_targ_mem(priv, priv->scd_base_addr +
707 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
708 iwl_write_targ_mem(priv, priv->scd_base_addr +
709 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
710 sizeof(u32),
711 ((SCD_WIN_SIZE <<
712 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
713 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
714 ((SCD_FRAME_LIMIT <<
715 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
716 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
717 }
718
719 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
720 IWL_MASK(0, priv->hw_params.max_txq_num));
721
722 /* Activate all Tx DMA/FIFO channels */
723 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
724
725 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
726
727 /* map qos queues to fifos one-to-one */
728 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
729 int ac = iwl5000_default_queue_to_tx_fifo[i];
730 iwl_txq_ctx_activate(priv, i);
731 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
732 }
733 /* TODO - need to initialize those FIFOs inside the loop above,
734 * not only mark them as active */
735 iwl_txq_ctx_activate(priv, 4);
736 iwl_txq_ctx_activate(priv, 7);
737 iwl_txq_ctx_activate(priv, 8);
738 iwl_txq_ctx_activate(priv, 9);
739
740 spin_unlock_irqrestore(&priv->lock, flags);
741
742
743 iwl5000_send_wimax_coex(priv);
744
745 iwl5000_set_Xtal_calib(priv);
746 iwl_send_calib_results(priv);
747
748 return 0;
749 }
750
751 int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
752 {
753 if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES &&
754 priv->cfg->mod_params->num_of_queues <= IWL50_NUM_QUEUES)
755 priv->cfg->num_of_queues =
756 priv->cfg->mod_params->num_of_queues;
757
758 priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
759 priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
760 priv->hw_params.scd_bc_tbls_size =
761 priv->cfg->num_of_queues *
762 sizeof(struct iwl5000_scd_bc_tbl);
763 priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
764 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
765 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
766
767 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
768 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
769
770 priv->hw_params.max_bsm_size = 0;
771 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
772 BIT(IEEE80211_BAND_5GHZ);
773 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
774
775 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
776 priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
777 priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
778 priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
779
780 if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
781 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
782
783 /* Set initial sensitivity parameters */
784 /* Set initial calibration set */
785 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
786 case CSR_HW_REV_TYPE_5150:
787 priv->hw_params.sens = &iwl5150_sensitivity;
788 priv->hw_params.calib_init_cfg =
789 BIT(IWL_CALIB_DC) |
790 BIT(IWL_CALIB_LO) |
791 BIT(IWL_CALIB_TX_IQ) |
792 BIT(IWL_CALIB_BASE_BAND);
793
794 break;
795 default:
796 priv->hw_params.sens = &iwl5000_sensitivity;
797 priv->hw_params.calib_init_cfg =
798 BIT(IWL_CALIB_XTAL) |
799 BIT(IWL_CALIB_LO) |
800 BIT(IWL_CALIB_TX_IQ) |
801 BIT(IWL_CALIB_TX_IQ_PERD) |
802 BIT(IWL_CALIB_BASE_BAND);
803 break;
804 }
805
806 return 0;
807 }
808
809 /**
810 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
811 */
812 void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
813 struct iwl_tx_queue *txq,
814 u16 byte_cnt)
815 {
816 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
817 int write_ptr = txq->q.write_ptr;
818 int txq_id = txq->q.id;
819 u8 sec_ctl = 0;
820 u8 sta_id = 0;
821 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
822 __le16 bc_ent;
823
824 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
825
826 if (txq_id != IWL_CMD_QUEUE_NUM) {
827 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
828 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
829
830 switch (sec_ctl & TX_CMD_SEC_MSK) {
831 case TX_CMD_SEC_CCM:
832 len += CCMP_MIC_LEN;
833 break;
834 case TX_CMD_SEC_TKIP:
835 len += TKIP_ICV_LEN;
836 break;
837 case TX_CMD_SEC_WEP:
838 len += WEP_IV_LEN + WEP_ICV_LEN;
839 break;
840 }
841 }
842
843 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
844
845 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
846
847 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
848 scd_bc_tbl[txq_id].
849 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
850 }
851
852 void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
853 struct iwl_tx_queue *txq)
854 {
855 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
856 int txq_id = txq->q.id;
857 int read_ptr = txq->q.read_ptr;
858 u8 sta_id = 0;
859 __le16 bc_ent;
860
861 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
862
863 if (txq_id != IWL_CMD_QUEUE_NUM)
864 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
865
866 bc_ent = cpu_to_le16(1 | (sta_id << 12));
867 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
868
869 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
870 scd_bc_tbl[txq_id].
871 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
872 }
873
874 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
875 u16 txq_id)
876 {
877 u32 tbl_dw_addr;
878 u32 tbl_dw;
879 u16 scd_q2ratid;
880
881 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
882
883 tbl_dw_addr = priv->scd_base_addr +
884 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
885
886 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
887
888 if (txq_id & 0x1)
889 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
890 else
891 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
892
893 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
894
895 return 0;
896 }
897 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
898 {
899 /* Simply stop the queue, but don't change any configuration;
900 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
901 iwl_write_prph(priv,
902 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
903 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
904 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
905 }
906
907 int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
908 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
909 {
910 unsigned long flags;
911 u16 ra_tid;
912
913 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
914 (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
915 <= txq_id)) {
916 IWL_WARN(priv,
917 "queue number out of range: %d, must be %d to %d\n",
918 txq_id, IWL50_FIRST_AMPDU_QUEUE,
919 IWL50_FIRST_AMPDU_QUEUE +
920 priv->cfg->num_of_ampdu_queues - 1);
921 return -EINVAL;
922 }
923
924 ra_tid = BUILD_RAxTID(sta_id, tid);
925
926 /* Modify device's station table to Tx this TID */
927 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
928
929 spin_lock_irqsave(&priv->lock, flags);
930
931 /* Stop this Tx queue before configuring it */
932 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
933
934 /* Map receiver-address / traffic-ID to this queue */
935 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
936
937 /* Set this queue as a chain-building queue */
938 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
939
940 /* enable aggregations for the queue */
941 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
942
943 /* Place first TFD at index corresponding to start sequence number.
944 * Assumes that ssn_idx is valid (!= 0xFFF) */
945 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
946 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
947 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
948
949 /* Set up Tx window size and frame limit for this queue */
950 iwl_write_targ_mem(priv, priv->scd_base_addr +
951 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
952 sizeof(u32),
953 ((SCD_WIN_SIZE <<
954 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
955 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
956 ((SCD_FRAME_LIMIT <<
957 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
958 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
959
960 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
961
962 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
963 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
964
965 spin_unlock_irqrestore(&priv->lock, flags);
966
967 return 0;
968 }
969
970 int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
971 u16 ssn_idx, u8 tx_fifo)
972 {
973 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
974 (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
975 <= txq_id)) {
976 IWL_ERR(priv,
977 "queue number out of range: %d, must be %d to %d\n",
978 txq_id, IWL50_FIRST_AMPDU_QUEUE,
979 IWL50_FIRST_AMPDU_QUEUE +
980 priv->cfg->num_of_ampdu_queues - 1);
981 return -EINVAL;
982 }
983
984 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
985
986 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
987
988 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
989 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
990 /* supposes that ssn_idx is valid (!= 0xFFF) */
991 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
992
993 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
994 iwl_txq_ctx_deactivate(priv, txq_id);
995 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
996
997 return 0;
998 }
999
1000 u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1001 {
1002 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1003 struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data;
1004 memcpy(addsta, cmd, size);
1005 /* resrved in 5000 */
1006 addsta->rate_n_flags = cpu_to_le16(0);
1007 return size;
1008 }
1009
1010
1011 /*
1012 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1013 * must be called under priv->lock and mac access
1014 */
1015 void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
1016 {
1017 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
1018 }
1019
1020
1021 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1022 {
1023 return le32_to_cpup((__le32 *)&tx_resp->status +
1024 tx_resp->frame_count) & MAX_SN;
1025 }
1026
1027 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1028 struct iwl_ht_agg *agg,
1029 struct iwl5000_tx_resp *tx_resp,
1030 int txq_id, u16 start_idx)
1031 {
1032 u16 status;
1033 struct agg_tx_status *frame_status = &tx_resp->status;
1034 struct ieee80211_tx_info *info = NULL;
1035 struct ieee80211_hdr *hdr = NULL;
1036 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1037 int i, sh, idx;
1038 u16 seq;
1039
1040 if (agg->wait_for_ba)
1041 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
1042
1043 agg->frame_count = tx_resp->frame_count;
1044 agg->start_idx = start_idx;
1045 agg->rate_n_flags = rate_n_flags;
1046 agg->bitmap = 0;
1047
1048 /* # frames attempted by Tx command */
1049 if (agg->frame_count == 1) {
1050 /* Only one frame was attempted; no block-ack will arrive */
1051 status = le16_to_cpu(frame_status[0].status);
1052 idx = start_idx;
1053
1054 /* FIXME: code repetition */
1055 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
1056 agg->frame_count, agg->start_idx, idx);
1057
1058 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1059 info->status.rates[0].count = tx_resp->failure_frame + 1;
1060 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1061 info->flags |= iwl_is_tx_success(status) ?
1062 IEEE80211_TX_STAT_ACK : 0;
1063 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1064
1065 /* FIXME: code repetition end */
1066
1067 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
1068 status & 0xff, tx_resp->failure_frame);
1069 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
1070
1071 agg->wait_for_ba = 0;
1072 } else {
1073 /* Two or more frames were attempted; expect block-ack */
1074 u64 bitmap = 0;
1075 int start = agg->start_idx;
1076
1077 /* Construct bit-map of pending frames within Tx window */
1078 for (i = 0; i < agg->frame_count; i++) {
1079 u16 sc;
1080 status = le16_to_cpu(frame_status[i].status);
1081 seq = le16_to_cpu(frame_status[i].sequence);
1082 idx = SEQ_TO_INDEX(seq);
1083 txq_id = SEQ_TO_QUEUE(seq);
1084
1085 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1086 AGG_TX_STATE_ABORT_MSK))
1087 continue;
1088
1089 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1090 agg->frame_count, txq_id, idx);
1091
1092 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1093 if (!hdr) {
1094 IWL_ERR(priv,
1095 "BUG_ON idx doesn't point to valid skb"
1096 " idx=%d, txq_id=%d\n", idx, txq_id);
1097 return -1;
1098 }
1099
1100 sc = le16_to_cpu(hdr->seq_ctrl);
1101 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1102 IWL_ERR(priv,
1103 "BUG_ON idx doesn't match seq control"
1104 " idx=%d, seq_idx=%d, seq=%d\n",
1105 idx, SEQ_TO_SN(sc),
1106 hdr->seq_ctrl);
1107 return -1;
1108 }
1109
1110 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
1111 i, idx, SEQ_TO_SN(sc));
1112
1113 sh = idx - start;
1114 if (sh > 64) {
1115 sh = (start - idx) + 0xff;
1116 bitmap = bitmap << sh;
1117 sh = 0;
1118 start = idx;
1119 } else if (sh < -64)
1120 sh = 0xff - (start - idx);
1121 else if (sh < 0) {
1122 sh = start - idx;
1123 start = idx;
1124 bitmap = bitmap << sh;
1125 sh = 0;
1126 }
1127 bitmap |= 1ULL << sh;
1128 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
1129 start, (unsigned long long)bitmap);
1130 }
1131
1132 agg->bitmap = bitmap;
1133 agg->start_idx = start;
1134 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
1135 agg->frame_count, agg->start_idx,
1136 (unsigned long long)agg->bitmap);
1137
1138 if (bitmap)
1139 agg->wait_for_ba = 1;
1140 }
1141 return 0;
1142 }
1143
1144 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1145 struct iwl_rx_mem_buffer *rxb)
1146 {
1147 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1148 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1149 int txq_id = SEQ_TO_QUEUE(sequence);
1150 int index = SEQ_TO_INDEX(sequence);
1151 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1152 struct ieee80211_tx_info *info;
1153 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1154 u32 status = le16_to_cpu(tx_resp->status.status);
1155 int tid;
1156 int sta_id;
1157 int freed;
1158
1159 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1160 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
1161 "is out of range [0-%d] %d %d\n", txq_id,
1162 index, txq->q.n_bd, txq->q.write_ptr,
1163 txq->q.read_ptr);
1164 return;
1165 }
1166
1167 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1168 memset(&info->status, 0, sizeof(info->status));
1169
1170 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1171 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
1172
1173 if (txq->sched_retry) {
1174 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1175 struct iwl_ht_agg *agg = NULL;
1176
1177 agg = &priv->stations[sta_id].tid[tid].agg;
1178
1179 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1180
1181 /* check if BAR is needed */
1182 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1183 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1184
1185 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1186 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1187 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
1188 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1189 scd_ssn , index, txq_id, txq->swq_id);
1190
1191 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1192 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1193
1194 if (priv->mac80211_registered &&
1195 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1196 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
1197 if (agg->state == IWL_AGG_OFF)
1198 iwl_wake_queue(priv, txq_id);
1199 else
1200 iwl_wake_queue(priv, txq->swq_id);
1201 }
1202 }
1203 } else {
1204 BUG_ON(txq_id != txq->swq_id);
1205
1206 info->status.rates[0].count = tx_resp->failure_frame + 1;
1207 info->flags |= iwl_is_tx_success(status) ?
1208 IEEE80211_TX_STAT_ACK : 0;
1209 iwl_hwrate_to_tx_control(priv,
1210 le32_to_cpu(tx_resp->rate_n_flags),
1211 info);
1212
1213 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
1214 "0x%x retries %d\n",
1215 txq_id,
1216 iwl_get_tx_fail_reason(status), status,
1217 le32_to_cpu(tx_resp->rate_n_flags),
1218 tx_resp->failure_frame);
1219
1220 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1221 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1222 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1223
1224 if (priv->mac80211_registered &&
1225 (iwl_queue_space(&txq->q) > txq->q.low_mark))
1226 iwl_wake_queue(priv, txq_id);
1227 }
1228
1229 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1230 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1231
1232 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1233 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
1234 }
1235
1236 /* Currently 5000 is the superset of everything */
1237 u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1238 {
1239 return len;
1240 }
1241
1242 void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1243 {
1244 /* in 5000 the tx power calibration is done in uCode */
1245 priv->disable_tx_power_cal = 1;
1246 }
1247
1248 void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1249 {
1250 /* init calibration handlers */
1251 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1252 iwl5000_rx_calib_result;
1253 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1254 iwl5000_rx_calib_complete;
1255 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1256 }
1257
1258
1259 int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1260 {
1261 return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
1262 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1263 }
1264
1265 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1266 {
1267 int ret = 0;
1268 struct iwl5000_rxon_assoc_cmd rxon_assoc;
1269 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1270 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1271
1272 if ((rxon1->flags == rxon2->flags) &&
1273 (rxon1->filter_flags == rxon2->filter_flags) &&
1274 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1275 (rxon1->ofdm_ht_single_stream_basic_rates ==
1276 rxon2->ofdm_ht_single_stream_basic_rates) &&
1277 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1278 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1279 (rxon1->ofdm_ht_triple_stream_basic_rates ==
1280 rxon2->ofdm_ht_triple_stream_basic_rates) &&
1281 (rxon1->acquisition_data == rxon2->acquisition_data) &&
1282 (rxon1->rx_chain == rxon2->rx_chain) &&
1283 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1284 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1285 return 0;
1286 }
1287
1288 rxon_assoc.flags = priv->staging_rxon.flags;
1289 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1290 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1291 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1292 rxon_assoc.reserved1 = 0;
1293 rxon_assoc.reserved2 = 0;
1294 rxon_assoc.reserved3 = 0;
1295 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1296 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1297 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1298 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1299 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1300 rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1301 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1302 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1303
1304 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1305 sizeof(rxon_assoc), &rxon_assoc, NULL);
1306 if (ret)
1307 return ret;
1308
1309 return ret;
1310 }
1311 int iwl5000_send_tx_power(struct iwl_priv *priv)
1312 {
1313 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1314 u8 tx_ant_cfg_cmd;
1315
1316 /* half dBm need to multiply */
1317 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1318 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1319 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1320
1321 if (IWL_UCODE_API(priv->ucode_ver) == 1)
1322 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
1323 else
1324 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
1325
1326 return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
1327 sizeof(tx_power_cmd), &tx_power_cmd,
1328 NULL);
1329 }
1330
1331 void iwl5000_temperature(struct iwl_priv *priv)
1332 {
1333 /* store temperature from statistics (in Celsius) */
1334 priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1335 iwl_tt_handler(priv);
1336 }
1337
1338 static void iwl5150_temperature(struct iwl_priv *priv)
1339 {
1340 u32 vt = 0;
1341 s32 offset = iwl_temp_calib_to_offset(priv);
1342
1343 vt = le32_to_cpu(priv->statistics.general.temperature);
1344 vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
1345 /* now vt hold the temperature in Kelvin */
1346 priv->temperature = KELVIN_TO_CELSIUS(vt);
1347 iwl_tt_handler(priv);
1348 }
1349
1350 /* Calc max signal level (dBm) among 3 possible receivers */
1351 int iwl5000_calc_rssi(struct iwl_priv *priv,
1352 struct iwl_rx_phy_res *rx_resp)
1353 {
1354 /* data from PHY/DSP regarding signal strength, etc.,
1355 * contents are always there, not configurable by host
1356 */
1357 struct iwl5000_non_cfg_phy *ncphy =
1358 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1359 u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1360 u8 agc;
1361
1362 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1363 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1364
1365 /* Find max rssi among 3 possible receivers.
1366 * These values are measured by the digital signal processor (DSP).
1367 * They should stay fairly constant even as the signal strength varies,
1368 * if the radio's automatic gain control (AGC) is working right.
1369 * AGC value (see below) will provide the "interesting" info.
1370 */
1371 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1372 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1373 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1374 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1375 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1376
1377 max_rssi = max_t(u32, rssi_a, rssi_b);
1378 max_rssi = max_t(u32, max_rssi, rssi_c);
1379
1380 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1381 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1382
1383 /* dBm = max_rssi dB - agc dB - constant.
1384 * Higher AGC (higher radio gain) means lower signal. */
1385 return max_rssi - agc - IWL49_RSSI_OFFSET;
1386 }
1387
1388 static int iwl5000_send_tx_ant_config(struct iwl_priv *priv, u8 valid_tx_ant)
1389 {
1390 struct iwl_tx_ant_config_cmd tx_ant_cmd = {
1391 .valid = cpu_to_le32(valid_tx_ant),
1392 };
1393
1394 if (IWL_UCODE_API(priv->ucode_ver) > 1) {
1395 IWL_DEBUG_HC(priv, "select valid tx ant: %u\n", valid_tx_ant);
1396 return iwl_send_cmd_pdu(priv, TX_ANT_CONFIGURATION_CMD,
1397 sizeof(struct iwl_tx_ant_config_cmd),
1398 &tx_ant_cmd);
1399 } else {
1400 IWL_DEBUG_HC(priv, "TX_ANT_CONFIGURATION_CMD not supported\n");
1401 return -EOPNOTSUPP;
1402 }
1403 }
1404
1405
1406 #define IWL5000_UCODE_GET(item) \
1407 static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\
1408 u32 api_ver) \
1409 { \
1410 if (api_ver <= 2) \
1411 return le32_to_cpu(ucode->u.v1.item); \
1412 return le32_to_cpu(ucode->u.v2.item); \
1413 }
1414
1415 static u32 iwl5000_ucode_get_header_size(u32 api_ver)
1416 {
1417 if (api_ver <= 2)
1418 return UCODE_HEADER_SIZE(1);
1419 return UCODE_HEADER_SIZE(2);
1420 }
1421
1422 static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode,
1423 u32 api_ver)
1424 {
1425 if (api_ver <= 2)
1426 return 0;
1427 return le32_to_cpu(ucode->u.v2.build);
1428 }
1429
1430 static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode,
1431 u32 api_ver)
1432 {
1433 if (api_ver <= 2)
1434 return (u8 *) ucode->u.v1.data;
1435 return (u8 *) ucode->u.v2.data;
1436 }
1437
1438 IWL5000_UCODE_GET(inst_size);
1439 IWL5000_UCODE_GET(data_size);
1440 IWL5000_UCODE_GET(init_size);
1441 IWL5000_UCODE_GET(init_data_size);
1442 IWL5000_UCODE_GET(boot_size);
1443
1444 struct iwl_hcmd_ops iwl5000_hcmd = {
1445 .rxon_assoc = iwl5000_send_rxon_assoc,
1446 .commit_rxon = iwl_commit_rxon,
1447 .set_rxon_chain = iwl_set_rxon_chain,
1448 .set_tx_ant = iwl5000_send_tx_ant_config,
1449 };
1450
1451 struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1452 .get_hcmd_size = iwl5000_get_hcmd_size,
1453 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1454 .gain_computation = iwl5000_gain_computation,
1455 .chain_noise_reset = iwl5000_chain_noise_reset,
1456 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1457 .calc_rssi = iwl5000_calc_rssi,
1458 };
1459
1460 struct iwl_ucode_ops iwl5000_ucode = {
1461 .get_header_size = iwl5000_ucode_get_header_size,
1462 .get_build = iwl5000_ucode_get_build,
1463 .get_inst_size = iwl5000_ucode_get_inst_size,
1464 .get_data_size = iwl5000_ucode_get_data_size,
1465 .get_init_size = iwl5000_ucode_get_init_size,
1466 .get_init_data_size = iwl5000_ucode_get_init_data_size,
1467 .get_boot_size = iwl5000_ucode_get_boot_size,
1468 .get_data = iwl5000_ucode_get_data,
1469 };
1470
1471 struct iwl_lib_ops iwl5000_lib = {
1472 .set_hw_params = iwl5000_hw_set_hw_params,
1473 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1474 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1475 .txq_set_sched = iwl5000_txq_set_sched,
1476 .txq_agg_enable = iwl5000_txq_agg_enable,
1477 .txq_agg_disable = iwl5000_txq_agg_disable,
1478 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1479 .txq_free_tfd = iwl_hw_txq_free_tfd,
1480 .txq_init = iwl_hw_tx_queue_init,
1481 .rx_handler_setup = iwl5000_rx_handler_setup,
1482 .setup_deferred_work = iwl5000_setup_deferred_work,
1483 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1484 .dump_nic_event_log = iwl_dump_nic_event_log,
1485 .dump_nic_error_log = iwl_dump_nic_error_log,
1486 .load_ucode = iwl5000_load_ucode,
1487 .init_alive_start = iwl5000_init_alive_start,
1488 .alive_notify = iwl5000_alive_notify,
1489 .send_tx_power = iwl5000_send_tx_power,
1490 .update_chain_flags = iwl_update_chain_flags,
1491 .apm_ops = {
1492 .init = iwl5000_apm_init,
1493 .stop = iwl_apm_stop,
1494 .config = iwl5000_nic_config,
1495 .set_pwr_src = iwl_set_pwr_src,
1496 },
1497 .eeprom_ops = {
1498 .regulatory_bands = {
1499 EEPROM_5000_REG_BAND_1_CHANNELS,
1500 EEPROM_5000_REG_BAND_2_CHANNELS,
1501 EEPROM_5000_REG_BAND_3_CHANNELS,
1502 EEPROM_5000_REG_BAND_4_CHANNELS,
1503 EEPROM_5000_REG_BAND_5_CHANNELS,
1504 EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1505 EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1506 },
1507 .verify_signature = iwlcore_eeprom_verify_signature,
1508 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1509 .release_semaphore = iwlcore_eeprom_release_semaphore,
1510 .calib_version = iwl5000_eeprom_calib_version,
1511 .query_addr = iwl5000_eeprom_query_addr,
1512 },
1513 .post_associate = iwl_post_associate,
1514 .isr = iwl_isr_ict,
1515 .config_ap = iwl_config_ap,
1516 .temp_ops = {
1517 .temperature = iwl5000_temperature,
1518 .set_ct_kill = iwl5000_set_ct_threshold,
1519 },
1520 };
1521
1522 static struct iwl_lib_ops iwl5150_lib = {
1523 .set_hw_params = iwl5000_hw_set_hw_params,
1524 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1525 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1526 .txq_set_sched = iwl5000_txq_set_sched,
1527 .txq_agg_enable = iwl5000_txq_agg_enable,
1528 .txq_agg_disable = iwl5000_txq_agg_disable,
1529 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1530 .txq_free_tfd = iwl_hw_txq_free_tfd,
1531 .txq_init = iwl_hw_tx_queue_init,
1532 .rx_handler_setup = iwl5000_rx_handler_setup,
1533 .setup_deferred_work = iwl5000_setup_deferred_work,
1534 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1535 .dump_nic_event_log = iwl_dump_nic_event_log,
1536 .dump_nic_error_log = iwl_dump_nic_error_log,
1537 .load_ucode = iwl5000_load_ucode,
1538 .init_alive_start = iwl5000_init_alive_start,
1539 .alive_notify = iwl5000_alive_notify,
1540 .send_tx_power = iwl5000_send_tx_power,
1541 .update_chain_flags = iwl_update_chain_flags,
1542 .apm_ops = {
1543 .init = iwl5000_apm_init,
1544 .stop = iwl_apm_stop,
1545 .config = iwl5000_nic_config,
1546 .set_pwr_src = iwl_set_pwr_src,
1547 },
1548 .eeprom_ops = {
1549 .regulatory_bands = {
1550 EEPROM_5000_REG_BAND_1_CHANNELS,
1551 EEPROM_5000_REG_BAND_2_CHANNELS,
1552 EEPROM_5000_REG_BAND_3_CHANNELS,
1553 EEPROM_5000_REG_BAND_4_CHANNELS,
1554 EEPROM_5000_REG_BAND_5_CHANNELS,
1555 EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1556 EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1557 },
1558 .verify_signature = iwlcore_eeprom_verify_signature,
1559 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1560 .release_semaphore = iwlcore_eeprom_release_semaphore,
1561 .calib_version = iwl5000_eeprom_calib_version,
1562 .query_addr = iwl5000_eeprom_query_addr,
1563 },
1564 .post_associate = iwl_post_associate,
1565 .isr = iwl_isr_ict,
1566 .config_ap = iwl_config_ap,
1567 .temp_ops = {
1568 .temperature = iwl5150_temperature,
1569 .set_ct_kill = iwl5150_set_ct_threshold,
1570 },
1571 };
1572
1573 static struct iwl_ops iwl5000_ops = {
1574 .ucode = &iwl5000_ucode,
1575 .lib = &iwl5000_lib,
1576 .hcmd = &iwl5000_hcmd,
1577 .utils = &iwl5000_hcmd_utils,
1578 .led = &iwlagn_led_ops,
1579 };
1580
1581 static struct iwl_ops iwl5150_ops = {
1582 .ucode = &iwl5000_ucode,
1583 .lib = &iwl5150_lib,
1584 .hcmd = &iwl5000_hcmd,
1585 .utils = &iwl5000_hcmd_utils,
1586 .led = &iwlagn_led_ops,
1587 };
1588
1589 struct iwl_mod_params iwl50_mod_params = {
1590 .amsdu_size_8K = 1,
1591 .restart_fw = 1,
1592 /* the rest are 0 by default */
1593 };
1594
1595
1596 struct iwl_cfg iwl5300_agn_cfg = {
1597 .name = "5300AGN",
1598 .fw_name_pre = IWL5000_FW_PRE,
1599 .ucode_api_max = IWL5000_UCODE_API_MAX,
1600 .ucode_api_min = IWL5000_UCODE_API_MIN,
1601 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1602 .ops = &iwl5000_ops,
1603 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1604 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1605 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1606 .num_of_queues = IWL50_NUM_QUEUES,
1607 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1608 .mod_params = &iwl50_mod_params,
1609 .valid_tx_ant = ANT_ABC,
1610 .valid_rx_ant = ANT_ABC,
1611 .need_pll_cfg = true,
1612 .ht_greenfield_support = true,
1613 .led_compensation = 51,
1614 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1615 };
1616
1617 struct iwl_cfg iwl5100_bg_cfg = {
1618 .name = "5100BG",
1619 .fw_name_pre = IWL5000_FW_PRE,
1620 .ucode_api_max = IWL5000_UCODE_API_MAX,
1621 .ucode_api_min = IWL5000_UCODE_API_MIN,
1622 .sku = IWL_SKU_G,
1623 .ops = &iwl5000_ops,
1624 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1625 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1626 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1627 .num_of_queues = IWL50_NUM_QUEUES,
1628 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1629 .mod_params = &iwl50_mod_params,
1630 .valid_tx_ant = ANT_B,
1631 .valid_rx_ant = ANT_AB,
1632 .need_pll_cfg = true,
1633 .ht_greenfield_support = true,
1634 .led_compensation = 51,
1635 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1636 };
1637
1638 struct iwl_cfg iwl5100_abg_cfg = {
1639 .name = "5100ABG",
1640 .fw_name_pre = IWL5000_FW_PRE,
1641 .ucode_api_max = IWL5000_UCODE_API_MAX,
1642 .ucode_api_min = IWL5000_UCODE_API_MIN,
1643 .sku = IWL_SKU_A|IWL_SKU_G,
1644 .ops = &iwl5000_ops,
1645 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1646 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1647 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1648 .num_of_queues = IWL50_NUM_QUEUES,
1649 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1650 .mod_params = &iwl50_mod_params,
1651 .valid_tx_ant = ANT_B,
1652 .valid_rx_ant = ANT_AB,
1653 .need_pll_cfg = true,
1654 .ht_greenfield_support = true,
1655 .led_compensation = 51,
1656 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1657 };
1658
1659 struct iwl_cfg iwl5100_agn_cfg = {
1660 .name = "5100AGN",
1661 .fw_name_pre = IWL5000_FW_PRE,
1662 .ucode_api_max = IWL5000_UCODE_API_MAX,
1663 .ucode_api_min = IWL5000_UCODE_API_MIN,
1664 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1665 .ops = &iwl5000_ops,
1666 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1667 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1668 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1669 .num_of_queues = IWL50_NUM_QUEUES,
1670 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1671 .mod_params = &iwl50_mod_params,
1672 .valid_tx_ant = ANT_B,
1673 .valid_rx_ant = ANT_AB,
1674 .need_pll_cfg = true,
1675 .ht_greenfield_support = true,
1676 .led_compensation = 51,
1677 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1678 };
1679
1680 struct iwl_cfg iwl5350_agn_cfg = {
1681 .name = "5350AGN",
1682 .fw_name_pre = IWL5000_FW_PRE,
1683 .ucode_api_max = IWL5000_UCODE_API_MAX,
1684 .ucode_api_min = IWL5000_UCODE_API_MIN,
1685 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1686 .ops = &iwl5000_ops,
1687 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1688 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1689 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1690 .num_of_queues = IWL50_NUM_QUEUES,
1691 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1692 .mod_params = &iwl50_mod_params,
1693 .valid_tx_ant = ANT_ABC,
1694 .valid_rx_ant = ANT_ABC,
1695 .need_pll_cfg = true,
1696 .ht_greenfield_support = true,
1697 .led_compensation = 51,
1698 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1699 };
1700
1701 struct iwl_cfg iwl5150_agn_cfg = {
1702 .name = "5150AGN",
1703 .fw_name_pre = IWL5150_FW_PRE,
1704 .ucode_api_max = IWL5150_UCODE_API_MAX,
1705 .ucode_api_min = IWL5150_UCODE_API_MIN,
1706 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1707 .ops = &iwl5150_ops,
1708 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1709 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1710 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1711 .num_of_queues = IWL50_NUM_QUEUES,
1712 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1713 .mod_params = &iwl50_mod_params,
1714 .valid_tx_ant = ANT_A,
1715 .valid_rx_ant = ANT_AB,
1716 .need_pll_cfg = true,
1717 .ht_greenfield_support = true,
1718 .led_compensation = 51,
1719 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1720 };
1721
1722 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1723 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
1724
1725 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, S_IRUGO);
1726 MODULE_PARM_DESC(swcrypto50,
1727 "using software crypto engine (default 0 [hardware])\n");
1728 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, S_IRUGO);
1729 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1730 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, S_IRUGO);
1731 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1732 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K,
1733 int, S_IRUGO);
1734 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1735 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, S_IRUGO);
1736 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");
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