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On Tue, Nov 06, 2007 at 02:33:53AM -0800, akpm@linux-foundation.org wrote:
[mmotm.git] / drivers / net / wireless / iwlwifi / iwl-tx.c
blob0bda1967f210dd14289b02f4a858361c4812f3be
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30 #include <linux/etherdevice.h>
31 #include <linux/sched.h>
32 #include <net/mac80211.h>
33 #include "iwl-eeprom.h"
34 #include "iwl-dev.h"
35 #include "iwl-core.h"
36 #include "iwl-sta.h"
37 #include "iwl-io.h"
38 #include "iwl-helpers.h"
39
40 static const u16 default_tid_to_tx_fifo[] = {
41 IWL_TX_FIFO_AC1,
42 IWL_TX_FIFO_AC0,
43 IWL_TX_FIFO_AC0,
44 IWL_TX_FIFO_AC1,
45 IWL_TX_FIFO_AC2,
46 IWL_TX_FIFO_AC2,
47 IWL_TX_FIFO_AC3,
48 IWL_TX_FIFO_AC3,
49 IWL_TX_FIFO_NONE,
50 IWL_TX_FIFO_NONE,
51 IWL_TX_FIFO_NONE,
52 IWL_TX_FIFO_NONE,
53 IWL_TX_FIFO_NONE,
54 IWL_TX_FIFO_NONE,
55 IWL_TX_FIFO_NONE,
56 IWL_TX_FIFO_NONE,
57 IWL_TX_FIFO_AC3
58 };
59
60 static inline int iwl_alloc_dma_ptr(struct iwl_priv *priv,
61 struct iwl_dma_ptr *ptr, size_t size)
62 {
63 ptr->addr = pci_alloc_consistent(priv->pci_dev, size, &ptr->dma);
64 if (!ptr->addr)
65 return -ENOMEM;
66 ptr->size = size;
67 return 0;
68 }
69
70 static inline void iwl_free_dma_ptr(struct iwl_priv *priv,
71 struct iwl_dma_ptr *ptr)
72 {
73 if (unlikely(!ptr->addr))
74 return;
75
76 pci_free_consistent(priv->pci_dev, ptr->size, ptr->addr, ptr->dma);
77 memset(ptr, 0, sizeof(*ptr));
78 }
79
80 /**
81 * iwl_txq_update_write_ptr - Send new write index to hardware
82 */
83 int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
84 {
85 u32 reg = 0;
86 int ret = 0;
87 int txq_id = txq->q.id;
88
89 if (txq->need_update == 0)
90 return ret;
91
92 /* if we're trying to save power */
93 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
94 /* wake up nic if it's powered down ...
95 * uCode will wake up, and interrupt us again, so next
96 * time we'll skip this part. */
97 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
98
99 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
100 IWL_DEBUG_INFO(priv, "Requesting wakeup, GP1 = 0x%x\n", reg);
101 iwl_set_bit(priv, CSR_GP_CNTRL,
102 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
103 return ret;
104 }
105
106 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
107 txq->q.write_ptr | (txq_id << 8));
108
109 /* else not in power-save mode, uCode will never sleep when we're
110 * trying to tx (during RFKILL, we're not trying to tx). */
111 } else
112 iwl_write32(priv, HBUS_TARG_WRPTR,
113 txq->q.write_ptr | (txq_id << 8));
114
115 txq->need_update = 0;
116
117 return ret;
118 }
119 EXPORT_SYMBOL(iwl_txq_update_write_ptr);
120
121
122 /**
123 * iwl_tx_queue_free - Deallocate DMA queue.
124 * @txq: Transmit queue to deallocate.
125 *
126 * Empty queue by removing and destroying all BD's.
127 * Free all buffers.
128 * 0-fill, but do not free "txq" descriptor structure.
129 */
130 void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
131 {
132 struct iwl_tx_queue *txq = &priv->txq[txq_id];
133 struct iwl_queue *q = &txq->q;
134 struct pci_dev *dev = priv->pci_dev;
135 int i, len;
136
137 if (q->n_bd == 0)
138 return;
139
140 /* first, empty all BD's */
141 for (; q->write_ptr != q->read_ptr;
142 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
143 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
144
145 len = sizeof(struct iwl_device_cmd) * q->n_window;
146
147 /* De-alloc array of command/tx buffers */
148 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
149 kfree(txq->cmd[i]);
150
151 /* De-alloc circular buffer of TFDs */
152 if (txq->q.n_bd)
153 pci_free_consistent(dev, priv->hw_params.tfd_size *
154 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
155
156 /* De-alloc array of per-TFD driver data */
157 kfree(txq->txb);
158 txq->txb = NULL;
159
160 /* deallocate arrays */
161 kfree(txq->cmd);
162 kfree(txq->meta);
163 txq->cmd = NULL;
164 txq->meta = NULL;
165
166 /* 0-fill queue descriptor structure */
167 memset(txq, 0, sizeof(*txq));
168 }
169 EXPORT_SYMBOL(iwl_tx_queue_free);
170
171 /**
172 * iwl_cmd_queue_free - Deallocate DMA queue.
173 * @txq: Transmit queue to deallocate.
174 *
175 * Empty queue by removing and destroying all BD's.
176 * Free all buffers.
177 * 0-fill, but do not free "txq" descriptor structure.
178 */
179 void iwl_cmd_queue_free(struct iwl_priv *priv)
180 {
181 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
182 struct iwl_queue *q = &txq->q;
183 struct pci_dev *dev = priv->pci_dev;
184 int i, len;
185
186 if (q->n_bd == 0)
187 return;
188
189 len = sizeof(struct iwl_device_cmd) * q->n_window;
190 len += IWL_MAX_SCAN_SIZE;
191
192 /* De-alloc array of command/tx buffers */
193 for (i = 0; i <= TFD_CMD_SLOTS; i++)
194 kfree(txq->cmd[i]);
195
196 /* De-alloc circular buffer of TFDs */
197 if (txq->q.n_bd)
198 pci_free_consistent(dev, priv->hw_params.tfd_size *
199 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
200
201 /* deallocate arrays */
202 kfree(txq->cmd);
203 kfree(txq->meta);
204 txq->cmd = NULL;
205 txq->meta = NULL;
206
207 /* 0-fill queue descriptor structure */
208 memset(txq, 0, sizeof(*txq));
209 }
210 EXPORT_SYMBOL(iwl_cmd_queue_free);
211
212 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
213 * DMA services
214 *
215 * Theory of operation
216 *
217 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
218 * of buffer descriptors, each of which points to one or more data buffers for
219 * the device to read from or fill. Driver and device exchange status of each
220 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
221 * entries in each circular buffer, to protect against confusing empty and full
222 * queue states.
223 *
224 * The device reads or writes the data in the queues via the device's several
225 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
226 *
227 * For Tx queue, there are low mark and high mark limits. If, after queuing
228 * the packet for Tx, free space become < low mark, Tx queue stopped. When
229 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
230 * Tx queue resumed.
231 *
232 * See more detailed info in iwl-4965-hw.h.
233 ***************************************************/
234
235 int iwl_queue_space(const struct iwl_queue *q)
236 {
237 int s = q->read_ptr - q->write_ptr;
238
239 if (q->read_ptr > q->write_ptr)
240 s -= q->n_bd;
241
242 if (s <= 0)
243 s += q->n_window;
244 /* keep some reserve to not confuse empty and full situations */
245 s -= 2;
246 if (s < 0)
247 s = 0;
248 return s;
249 }
250 EXPORT_SYMBOL(iwl_queue_space);
251
252
253 /**
254 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
255 */
256 static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
257 int count, int slots_num, u32 id)
258 {
259 q->n_bd = count;
260 q->n_window = slots_num;
261 q->id = id;
262
263 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
264 * and iwl_queue_dec_wrap are broken. */
265 BUG_ON(!is_power_of_2(count));
266
267 /* slots_num must be power-of-two size, otherwise
268 * get_cmd_index is broken. */
269 BUG_ON(!is_power_of_2(slots_num));
270
271 q->low_mark = q->n_window / 4;
272 if (q->low_mark < 4)
273 q->low_mark = 4;
274
275 q->high_mark = q->n_window / 8;
276 if (q->high_mark < 2)
277 q->high_mark = 2;
278
279 q->write_ptr = q->read_ptr = 0;
280
281 return 0;
282 }
283
284 /**
285 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
286 */
287 static int iwl_tx_queue_alloc(struct iwl_priv *priv,
288 struct iwl_tx_queue *txq, u32 id)
289 {
290 struct pci_dev *dev = priv->pci_dev;
291 size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
292
293 /* Driver private data, only for Tx (not command) queues,
294 * not shared with device. */
295 if (id != IWL_CMD_QUEUE_NUM) {
296 txq->txb = kmalloc(sizeof(txq->txb[0]) *
297 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
298 if (!txq->txb) {
299 IWL_ERR(priv, "kmalloc for auxiliary BD "
300 "structures failed\n");
301 goto error;
302 }
303 } else {
304 txq->txb = NULL;
305 }
306
307 /* Circular buffer of transmit frame descriptors (TFDs),
308 * shared with device */
309 txq->tfds = pci_alloc_consistent(dev, tfd_sz, &txq->q.dma_addr);
310
311 if (!txq->tfds) {
312 IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz);
313 goto error;
314 }
315 txq->q.id = id;
316
317 return 0;
318
319 error:
320 kfree(txq->txb);
321 txq->txb = NULL;
322
323 return -ENOMEM;
324 }
325
326 /**
327 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
328 */
329 int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
330 int slots_num, u32 txq_id)
331 {
332 int i, len;
333 int ret;
334 int actual_slots = slots_num;
335
336 /*
337 * Alloc buffer array for commands (Tx or other types of commands).
338 * For the command queue (#4), allocate command space + one big
339 * command for scan, since scan command is very huge; the system will
340 * not have two scans at the same time, so only one is needed.
341 * For normal Tx queues (all other queues), no super-size command
342 * space is needed.
343 */
344 if (txq_id == IWL_CMD_QUEUE_NUM)
345 actual_slots++;
346
347 txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots,
348 GFP_KERNEL);
349 txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots,
350 GFP_KERNEL);
351
352 if (!txq->meta || !txq->cmd)
353 goto out_free_arrays;
354
355 len = sizeof(struct iwl_device_cmd);
356 for (i = 0; i < actual_slots; i++) {
357 /* only happens for cmd queue */
358 if (i == slots_num)
359 len += IWL_MAX_SCAN_SIZE;
360
361 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
362 if (!txq->cmd[i])
363 goto err;
364 }
365
366 /* Alloc driver data array and TFD circular buffer */
367 ret = iwl_tx_queue_alloc(priv, txq, txq_id);
368 if (ret)
369 goto err;
370
371 txq->need_update = 0;
372
373 /* aggregation TX queues will get their ID when aggregation begins */
374 if (txq_id <= IWL_TX_FIFO_AC3)
375 txq->swq_id = txq_id;
376
377 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
378 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
379 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
380
381 /* Initialize queue's high/low-water marks, and head/tail indexes */
382 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
383
384 /* Tell device where to find queue */
385 priv->cfg->ops->lib->txq_init(priv, txq);
386
387 return 0;
388 err:
389 for (i = 0; i < actual_slots; i++)
390 kfree(txq->cmd[i]);
391 out_free_arrays:
392 kfree(txq->meta);
393 kfree(txq->cmd);
394
395 return -ENOMEM;
396 }
397 EXPORT_SYMBOL(iwl_tx_queue_init);
398
399 /**
400 * iwl_hw_txq_ctx_free - Free TXQ Context
401 *
402 * Destroy all TX DMA queues and structures
403 */
404 void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
405 {
406 int txq_id;
407
408 /* Tx queues */
409 if (priv->txq)
410 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
411 txq_id++)
412 if (txq_id == IWL_CMD_QUEUE_NUM)
413 iwl_cmd_queue_free(priv);
414 else
415 iwl_tx_queue_free(priv, txq_id);
416 iwl_free_dma_ptr(priv, &priv->kw);
417
418 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
419
420 /* free tx queue structure */
421 iwl_free_txq_mem(priv);
422 }
423 EXPORT_SYMBOL(iwl_hw_txq_ctx_free);
424
425 /**
426 * iwl_txq_ctx_reset - Reset TX queue context
427 * Destroys all DMA structures and initialize them again
428 *
429 * @param priv
430 * @return error code
431 */
432 int iwl_txq_ctx_reset(struct iwl_priv *priv)
433 {
434 int ret = 0;
435 int txq_id, slots_num;
436 unsigned long flags;
437
438 /* Free all tx/cmd queues and keep-warm buffer */
439 iwl_hw_txq_ctx_free(priv);
440
441 ret = iwl_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
442 priv->hw_params.scd_bc_tbls_size);
443 if (ret) {
444 IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
445 goto error_bc_tbls;
446 }
447 /* Alloc keep-warm buffer */
448 ret = iwl_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
449 if (ret) {
450 IWL_ERR(priv, "Keep Warm allocation failed\n");
451 goto error_kw;
452 }
453
454 /* allocate tx queue structure */
455 ret = iwl_alloc_txq_mem(priv);
456 if (ret)
457 goto error;
458
459 spin_lock_irqsave(&priv->lock, flags);
460
461 /* Turn off all Tx DMA fifos */
462 priv->cfg->ops->lib->txq_set_sched(priv, 0);
463
464 /* Tell NIC where to find the "keep warm" buffer */
465 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
466
467 spin_unlock_irqrestore(&priv->lock, flags);
468
469 /* Alloc and init all Tx queues, including the command queue (#4) */
470 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
471 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
472 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
473 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
474 txq_id);
475 if (ret) {
476 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
477 goto error;
478 }
479 }
480
481 return ret;
482
483 error:
484 iwl_hw_txq_ctx_free(priv);
485 iwl_free_dma_ptr(priv, &priv->kw);
486 error_kw:
487 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
488 error_bc_tbls:
489 return ret;
490 }
491
492 /**
493 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
494 */
495 void iwl_txq_ctx_stop(struct iwl_priv *priv)
496 {
497 int ch;
498 unsigned long flags;
499
500 /* Turn off all Tx DMA fifos */
501 spin_lock_irqsave(&priv->lock, flags);
502
503 priv->cfg->ops->lib->txq_set_sched(priv, 0);
504
505 /* Stop each Tx DMA channel, and wait for it to be idle */
506 for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
507 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
508 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
509 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
510 1000);
511 }
512 spin_unlock_irqrestore(&priv->lock, flags);
513
514 /* Deallocate memory for all Tx queues */
515 iwl_hw_txq_ctx_free(priv);
516 }
517 EXPORT_SYMBOL(iwl_txq_ctx_stop);
518
519 /*
520 * handle build REPLY_TX command notification.
521 */
522 static void iwl_tx_cmd_build_basic(struct iwl_priv *priv,
523 struct iwl_tx_cmd *tx_cmd,
524 struct ieee80211_tx_info *info,
525 struct ieee80211_hdr *hdr,
526 u8 std_id)
527 {
528 __le16 fc = hdr->frame_control;
529 __le32 tx_flags = tx_cmd->tx_flags;
530
531 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
532 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
533 tx_flags |= TX_CMD_FLG_ACK_MSK;
534 if (ieee80211_is_mgmt(fc))
535 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
536 if (ieee80211_is_probe_resp(fc) &&
537 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
538 tx_flags |= TX_CMD_FLG_TSF_MSK;
539 } else {
540 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
541 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
542 }
543
544 if (ieee80211_is_back_req(fc))
545 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
546
547
548 tx_cmd->sta_id = std_id;
549 if (ieee80211_has_morefrags(fc))
550 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
551
552 if (ieee80211_is_data_qos(fc)) {
553 u8 *qc = ieee80211_get_qos_ctl(hdr);
554 tx_cmd->tid_tspec = qc[0] & 0xf;
555 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
556 } else {
557 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
558 }
559
560 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
561
562 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
563 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
564
565 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
566 if (ieee80211_is_mgmt(fc)) {
567 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
568 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
569 else
570 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
571 } else {
572 tx_cmd->timeout.pm_frame_timeout = 0;
573 }
574
575 tx_cmd->driver_txop = 0;
576 tx_cmd->tx_flags = tx_flags;
577 tx_cmd->next_frame_len = 0;
578 }
579
580 #define RTS_HCCA_RETRY_LIMIT 3
581 #define RTS_DFAULT_RETRY_LIMIT 60
582
583 static void iwl_tx_cmd_build_rate(struct iwl_priv *priv,
584 struct iwl_tx_cmd *tx_cmd,
585 struct ieee80211_tx_info *info,
586 __le16 fc, int is_hcca)
587 {
588 u32 rate_flags;
589 int rate_idx;
590 u8 rts_retry_limit;
591 u8 data_retry_limit;
592 u8 rate_plcp;
593
594 /* Set retry limit on DATA packets and Probe Responses*/
595 if (ieee80211_is_probe_resp(fc))
596 data_retry_limit = 3;
597 else
598 data_retry_limit = IWL_DEFAULT_TX_RETRY;
599 tx_cmd->data_retry_limit = data_retry_limit;
600
601 /* Set retry limit on RTS packets */
602 rts_retry_limit = (is_hcca) ? RTS_HCCA_RETRY_LIMIT :
603 RTS_DFAULT_RETRY_LIMIT;
604 if (data_retry_limit < rts_retry_limit)
605 rts_retry_limit = data_retry_limit;
606 tx_cmd->rts_retry_limit = rts_retry_limit;
607
608 /* DATA packets will use the uCode station table for rate/antenna
609 * selection */
610 if (ieee80211_is_data(fc)) {
611 tx_cmd->initial_rate_index = 0;
612 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
613 return;
614 }
615
616 /**
617 * If the current TX rate stored in mac80211 has the MCS bit set, it's
618 * not really a TX rate. Thus, we use the lowest supported rate for
619 * this band. Also use the lowest supported rate if the stored rate
620 * index is invalid.
621 */
622 rate_idx = info->control.rates[0].idx;
623 if (info->control.rates[0].flags & IEEE80211_TX_RC_MCS ||
624 (rate_idx < 0) || (rate_idx > IWL_RATE_COUNT_LEGACY))
625 rate_idx = rate_lowest_index(&priv->bands[info->band],
626 info->control.sta);
627 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
628 if (info->band == IEEE80211_BAND_5GHZ)
629 rate_idx += IWL_FIRST_OFDM_RATE;
630 /* Get PLCP rate for tx_cmd->rate_n_flags */
631 rate_plcp = iwl_rates[rate_idx].plcp;
632 /* Zero out flags for this packet */
633 rate_flags = 0;
634
635 /* Set CCK flag as needed */
636 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
637 rate_flags |= RATE_MCS_CCK_MSK;
638
639 /* Set up RTS and CTS flags for certain packets */
640 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
641 case cpu_to_le16(IEEE80211_STYPE_AUTH):
642 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
643 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
644 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
645 if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) {
646 tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
647 tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK;
648 }
649 break;
650 default:
651 break;
652 }
653
654 /* Set up antennas */
655 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
656 rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
657
658 /* Set the rate in the TX cmd */
659 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
660 }
661
662 static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
663 struct ieee80211_tx_info *info,
664 struct iwl_tx_cmd *tx_cmd,
665 struct sk_buff *skb_frag,
666 int sta_id)
667 {
668 struct ieee80211_key_conf *keyconf = info->control.hw_key;
669
670 switch (keyconf->alg) {
671 case ALG_CCMP:
672 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
673 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
674 if (info->flags & IEEE80211_TX_CTL_AMPDU)
675 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
676 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
677 break;
678
679 case ALG_TKIP:
680 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
681 ieee80211_get_tkip_key(keyconf, skb_frag,
682 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
683 IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n");
684 break;
685
686 case ALG_WEP:
687 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
688 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
689
690 if (keyconf->keylen == WEP_KEY_LEN_128)
691 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
692
693 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
694
695 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
696 "with key %d\n", keyconf->keyidx);
697 break;
698
699 default:
700 IWL_ERR(priv, "Unknown encode alg %d\n", keyconf->alg);
701 break;
702 }
703 }
704
705 /*
706 * start REPLY_TX command process
707 */
708 int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
709 {
710 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
711 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
712 struct iwl_tx_queue *txq;
713 struct iwl_queue *q;
714 struct iwl_device_cmd *out_cmd;
715 struct iwl_cmd_meta *out_meta;
716 struct iwl_tx_cmd *tx_cmd;
717 int swq_id, txq_id;
718 dma_addr_t phys_addr;
719 dma_addr_t txcmd_phys;
720 dma_addr_t scratch_phys;
721 u16 len, len_org, firstlen, secondlen;
722 u16 seq_number = 0;
723 __le16 fc;
724 u8 hdr_len;
725 u8 sta_id;
726 u8 wait_write_ptr = 0;
727 u8 tid = 0;
728 u8 *qc = NULL;
729 unsigned long flags;
730 int ret;
731
732 spin_lock_irqsave(&priv->lock, flags);
733 if (iwl_is_rfkill(priv)) {
734 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
735 goto drop_unlock;
736 }
737
738 fc = hdr->frame_control;
739
740 #ifdef CONFIG_IWLWIFI_DEBUG
741 if (ieee80211_is_auth(fc))
742 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
743 else if (ieee80211_is_assoc_req(fc))
744 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
745 else if (ieee80211_is_reassoc_req(fc))
746 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
747 #endif
748
749 /* drop all non-injected data frame if we are not associated */
750 if (ieee80211_is_data(fc) &&
751 !(info->flags & IEEE80211_TX_CTL_INJECTED) &&
752 (!iwl_is_associated(priv) ||
753 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id) ||
754 !priv->assoc_station_added)) {
755 IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n");
756 goto drop_unlock;
757 }
758
759 hdr_len = ieee80211_hdrlen(fc);
760
761 /* Find (or create) index into station table for destination station */
762 if (info->flags & IEEE80211_TX_CTL_INJECTED)
763 sta_id = priv->hw_params.bcast_sta_id;
764 else
765 sta_id = iwl_get_sta_id(priv, hdr);
766 if (sta_id == IWL_INVALID_STATION) {
767 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
768 hdr->addr1);
769 goto drop_unlock;
770 }
771
772 IWL_DEBUG_TX(priv, "station Id %d\n", sta_id);
773
774 txq_id = skb_get_queue_mapping(skb);
775 if (ieee80211_is_data_qos(fc)) {
776 qc = ieee80211_get_qos_ctl(hdr);
777 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
778 if (unlikely(tid >= MAX_TID_COUNT))
779 goto drop_unlock;
780 seq_number = priv->stations[sta_id].tid[tid].seq_number;
781 seq_number &= IEEE80211_SCTL_SEQ;
782 hdr->seq_ctrl = hdr->seq_ctrl &
783 cpu_to_le16(IEEE80211_SCTL_FRAG);
784 hdr->seq_ctrl |= cpu_to_le16(seq_number);
785 seq_number += 0x10;
786 /* aggregation is on for this <sta,tid> */
787 if (info->flags & IEEE80211_TX_CTL_AMPDU)
788 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
789 }
790
791 txq = &priv->txq[txq_id];
792 swq_id = txq->swq_id;
793 q = &txq->q;
794
795 if (unlikely(iwl_queue_space(q) < q->high_mark))
796 goto drop_unlock;
797
798 if (ieee80211_is_data_qos(fc))
799 priv->stations[sta_id].tid[tid].tfds_in_queue++;
800
801 /* Set up driver data for this TFD */
802 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
803 txq->txb[q->write_ptr].skb[0] = skb;
804
805 /* Set up first empty entry in queue's array of Tx/cmd buffers */
806 out_cmd = txq->cmd[q->write_ptr];
807 out_meta = &txq->meta[q->write_ptr];
808 tx_cmd = &out_cmd->cmd.tx;
809 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
810 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
811
812 /*
813 * Set up the Tx-command (not MAC!) header.
814 * Store the chosen Tx queue and TFD index within the sequence field;
815 * after Tx, uCode's Tx response will return this value so driver can
816 * locate the frame within the tx queue and do post-tx processing.
817 */
818 out_cmd->hdr.cmd = REPLY_TX;
819 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
820 INDEX_TO_SEQ(q->write_ptr)));
821
822 /* Copy MAC header from skb into command buffer */
823 memcpy(tx_cmd->hdr, hdr, hdr_len);
824
825
826 /* Total # bytes to be transmitted */
827 len = (u16)skb->len;
828 tx_cmd->len = cpu_to_le16(len);
829
830 if (info->control.hw_key)
831 iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
832
833 /* TODO need this for burst mode later on */
834 iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, sta_id);
835 iwl_dbg_log_tx_data_frame(priv, len, hdr);
836
837 /* set is_hcca to 0; it probably will never be implemented */
838 iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, 0);
839
840 iwl_update_stats(priv, true, fc, len);
841 /*
842 * Use the first empty entry in this queue's command buffer array
843 * to contain the Tx command and MAC header concatenated together
844 * (payload data will be in another buffer).
845 * Size of this varies, due to varying MAC header length.
846 * If end is not dword aligned, we'll have 2 extra bytes at the end
847 * of the MAC header (device reads on dword boundaries).
848 * We'll tell device about this padding later.
849 */
850 len = sizeof(struct iwl_tx_cmd) +
851 sizeof(struct iwl_cmd_header) + hdr_len;
852
853 len_org = len;
854 firstlen = len = (len + 3) & ~3;
855
856 if (len_org != len)
857 len_org = 1;
858 else
859 len_org = 0;
860
861 /* Tell NIC about any 2-byte padding after MAC header */
862 if (len_org)
863 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
864
865 /* Physical address of this Tx command's header (not MAC header!),
866 * within command buffer array. */
867 txcmd_phys = pci_map_single(priv->pci_dev,
868 &out_cmd->hdr, len,
869 PCI_DMA_BIDIRECTIONAL);
870 pci_unmap_addr_set(out_meta, mapping, txcmd_phys);
871 pci_unmap_len_set(out_meta, len, len);
872 /* Add buffer containing Tx command and MAC(!) header to TFD's
873 * first entry */
874 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
875 txcmd_phys, len, 1, 0);
876
877 if (!ieee80211_has_morefrags(hdr->frame_control)) {
878 txq->need_update = 1;
879 if (qc)
880 priv->stations[sta_id].tid[tid].seq_number = seq_number;
881 } else {
882 wait_write_ptr = 1;
883 txq->need_update = 0;
884 }
885
886 /* Set up TFD's 2nd entry to point directly to remainder of skb,
887 * if any (802.11 null frames have no payload). */
888 secondlen = len = skb->len - hdr_len;
889 if (len) {
890 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
891 len, PCI_DMA_TODEVICE);
892 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
893 phys_addr, len,
894 0, 0);
895 }
896
897 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
898 offsetof(struct iwl_tx_cmd, scratch);
899
900 len = sizeof(struct iwl_tx_cmd) +
901 sizeof(struct iwl_cmd_header) + hdr_len;
902 /* take back ownership of DMA buffer to enable update */
903 pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys,
904 len, PCI_DMA_BIDIRECTIONAL);
905 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
906 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
907
908 IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n",
909 le16_to_cpu(out_cmd->hdr.sequence));
910 IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx_cmd->tx_flags));
911 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
912 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
913
914 /* Set up entry for this TFD in Tx byte-count array */
915 if (info->flags & IEEE80211_TX_CTL_AMPDU)
916 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq,
917 le16_to_cpu(tx_cmd->len));
918
919 pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys,
920 len, PCI_DMA_BIDIRECTIONAL);
921
922 trace_iwlwifi_dev_tx(priv,
923 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
924 sizeof(struct iwl_tfd),
925 &out_cmd->hdr, firstlen,
926 skb->data + hdr_len, secondlen);
927
928 /* Tell device the write index *just past* this latest filled TFD */
929 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
930 ret = iwl_txq_update_write_ptr(priv, txq);
931 spin_unlock_irqrestore(&priv->lock, flags);
932
933 if (ret)
934 return ret;
935
936 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
937 if (wait_write_ptr) {
938 spin_lock_irqsave(&priv->lock, flags);
939 txq->need_update = 1;
940 iwl_txq_update_write_ptr(priv, txq);
941 spin_unlock_irqrestore(&priv->lock, flags);
942 } else {
943 iwl_stop_queue(priv, txq->swq_id);
944 }
945 }
946
947 return 0;
948
949 drop_unlock:
950 spin_unlock_irqrestore(&priv->lock, flags);
951 return -1;
952 }
953 EXPORT_SYMBOL(iwl_tx_skb);
954
955 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
956
957 /**
958 * iwl_enqueue_hcmd - enqueue a uCode command
959 * @priv: device private data point
960 * @cmd: a point to the ucode command structure
961 *
962 * The function returns < 0 values to indicate the operation is
963 * failed. On success, it turns the index (> 0) of command in the
964 * command queue.
965 */
966 int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
967 {
968 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
969 struct iwl_queue *q = &txq->q;
970 struct iwl_device_cmd *out_cmd;
971 struct iwl_cmd_meta *out_meta;
972 dma_addr_t phys_addr;
973 unsigned long flags;
974 int len, ret;
975 u32 idx;
976 u16 fix_size;
977
978 cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
979 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
980
981 /* If any of the command structures end up being larger than
982 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
983 * we will need to increase the size of the TFD entries */
984 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
985 !(cmd->flags & CMD_SIZE_HUGE));
986
987 if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) {
988 IWL_DEBUG_INFO(priv, "Not sending command - RF/CT KILL\n");
989 return -EIO;
990 }
991
992 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
993 IWL_ERR(priv, "No space for Tx\n");
994 if (iwl_within_ct_kill_margin(priv))
995 iwl_tt_enter_ct_kill(priv);
996 else {
997 IWL_ERR(priv, "Restarting adapter due to queue full\n");
998 queue_work(priv->workqueue, &priv->restart);
999 }
1000 return -ENOSPC;
1001 }
1002
1003 spin_lock_irqsave(&priv->hcmd_lock, flags);
1004
1005 idx = get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
1006 out_cmd = txq->cmd[idx];
1007 out_meta = &txq->meta[idx];
1008
1009 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1010 out_meta->flags = cmd->flags;
1011 if (cmd->flags & CMD_WANT_SKB)
1012 out_meta->source = cmd;
1013 if (cmd->flags & CMD_ASYNC)
1014 out_meta->callback = cmd->callback;
1015
1016 out_cmd->hdr.cmd = cmd->id;
1017 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
1018
1019 /* At this point, the out_cmd now has all of the incoming cmd
1020 * information */
1021
1022 out_cmd->hdr.flags = 0;
1023 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
1024 INDEX_TO_SEQ(q->write_ptr));
1025 if (cmd->flags & CMD_SIZE_HUGE)
1026 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
1027 len = sizeof(struct iwl_device_cmd);
1028 len += (idx == TFD_CMD_SLOTS) ? IWL_MAX_SCAN_SIZE : 0;
1029
1030
1031 #ifdef CONFIG_IWLWIFI_DEBUG
1032 switch (out_cmd->hdr.cmd) {
1033 case REPLY_TX_LINK_QUALITY_CMD:
1034 case SENSITIVITY_CMD:
1035 IWL_DEBUG_HC_DUMP(priv, "Sending command %s (#%x), seq: 0x%04X, "
1036 "%d bytes at %d[%d]:%d\n",
1037 get_cmd_string(out_cmd->hdr.cmd),
1038 out_cmd->hdr.cmd,
1039 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1040 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1041 break;
1042 default:
1043 IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
1044 "%d bytes at %d[%d]:%d\n",
1045 get_cmd_string(out_cmd->hdr.cmd),
1046 out_cmd->hdr.cmd,
1047 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1048 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1049 }
1050 #endif
1051 txq->need_update = 1;
1052
1053 if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl)
1054 /* Set up entry in queue's byte count circular buffer */
1055 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
1056
1057 phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr,
1058 fix_size, PCI_DMA_BIDIRECTIONAL);
1059 pci_unmap_addr_set(out_meta, mapping, phys_addr);
1060 pci_unmap_len_set(out_meta, len, fix_size);
1061
1062 trace_iwlwifi_dev_hcmd(priv, &out_cmd->hdr, fix_size, cmd->flags);
1063
1064 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
1065 phys_addr, fix_size, 1,
1066 U32_PAD(cmd->len));
1067
1068 /* Increment and update queue's write index */
1069 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1070 ret = iwl_txq_update_write_ptr(priv, txq);
1071
1072 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
1073 return ret ? ret : idx;
1074 }
1075
1076 int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1077 {
1078 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1079 struct iwl_queue *q = &txq->q;
1080 struct iwl_tx_info *tx_info;
1081 int nfreed = 0;
1082
1083 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1084 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1085 "is out of range [0-%d] %d %d.\n", txq_id,
1086 index, q->n_bd, q->write_ptr, q->read_ptr);
1087 return 0;
1088 }
1089
1090 for (index = iwl_queue_inc_wrap(index, q->n_bd);
1091 q->read_ptr != index;
1092 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1093
1094 tx_info = &txq->txb[txq->q.read_ptr];
1095 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
1096 tx_info->skb[0] = NULL;
1097
1098 if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
1099 priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);
1100
1101 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
1102 nfreed++;
1103 }
1104 return nfreed;
1105 }
1106 EXPORT_SYMBOL(iwl_tx_queue_reclaim);
1107
1108
1109 /**
1110 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
1111 *
1112 * When FW advances 'R' index, all entries between old and new 'R' index
1113 * need to be reclaimed. As result, some free space forms. If there is
1114 * enough free space (> low mark), wake the stack that feeds us.
1115 */
1116 static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id,
1117 int idx, int cmd_idx)
1118 {
1119 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1120 struct iwl_queue *q = &txq->q;
1121 int nfreed = 0;
1122
1123 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
1124 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1125 "is out of range [0-%d] %d %d.\n", txq_id,
1126 idx, q->n_bd, q->write_ptr, q->read_ptr);
1127 return;
1128 }
1129
1130 pci_unmap_single(priv->pci_dev,
1131 pci_unmap_addr(&txq->meta[cmd_idx], mapping),
1132 pci_unmap_len(&txq->meta[cmd_idx], len),
1133 PCI_DMA_BIDIRECTIONAL);
1134
1135 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
1136 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1137
1138 if (nfreed++ > 0) {
1139 IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
1140 q->write_ptr, q->read_ptr);
1141 queue_work(priv->workqueue, &priv->restart);
1142 }
1143
1144 }
1145 }
1146
1147 /**
1148 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
1149 * @rxb: Rx buffer to reclaim
1150 *
1151 * If an Rx buffer has an async callback associated with it the callback
1152 * will be executed. The attached skb (if present) will only be freed
1153 * if the callback returns 1
1154 */
1155 void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1156 {
1157 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1158 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1159 int txq_id = SEQ_TO_QUEUE(sequence);
1160 int index = SEQ_TO_INDEX(sequence);
1161 int cmd_index;
1162 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
1163 struct iwl_device_cmd *cmd;
1164 struct iwl_cmd_meta *meta;
1165
1166 /* If a Tx command is being handled and it isn't in the actual
1167 * command queue then there a command routing bug has been introduced
1168 * in the queue management code. */
1169 if (WARN(txq_id != IWL_CMD_QUEUE_NUM,
1170 "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n",
1171 txq_id, sequence,
1172 priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr,
1173 priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) {
1174 iwl_print_hex_error(priv, pkt, 32);
1175 return;
1176 }
1177
1178 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
1179 cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
1180 meta = &priv->txq[IWL_CMD_QUEUE_NUM].meta[cmd_index];
1181
1182 /* Input error checking is done when commands are added to queue. */
1183 if (meta->flags & CMD_WANT_SKB) {
1184 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
1185 rxb->page = NULL;
1186 } else if (meta->callback)
1187 meta->callback(priv, cmd, pkt);
1188
1189 iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index);
1190
1191 if (!(meta->flags & CMD_ASYNC)) {
1192 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1193 wake_up_interruptible(&priv->wait_command_queue);
1194 }
1195 }
1196 EXPORT_SYMBOL(iwl_tx_cmd_complete);
1197
1198 /*
1199 * Find first available (lowest unused) Tx Queue, mark it "active".
1200 * Called only when finding queue for aggregation.
1201 * Should never return anything < 7, because they should already
1202 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
1203 */
1204 static int iwl_txq_ctx_activate_free(struct iwl_priv *priv)
1205 {
1206 int txq_id;
1207
1208 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1209 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
1210 return txq_id;
1211 return -1;
1212 }
1213
1214 int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn)
1215 {
1216 int sta_id;
1217 int tx_fifo;
1218 int txq_id;
1219 int ret;
1220 unsigned long flags;
1221 struct iwl_tid_data *tid_data;
1222
1223 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1224 tx_fifo = default_tid_to_tx_fifo[tid];
1225 else
1226 return -EINVAL;
1227
1228 IWL_WARN(priv, "%s on ra = %pM tid = %d\n",
1229 __func__, ra, tid);
1230
1231 sta_id = iwl_find_station(priv, ra);
1232 if (sta_id == IWL_INVALID_STATION) {
1233 IWL_ERR(priv, "Start AGG on invalid station\n");
1234 return -ENXIO;
1235 }
1236 if (unlikely(tid >= MAX_TID_COUNT))
1237 return -EINVAL;
1238
1239 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
1240 IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n");
1241 return -ENXIO;
1242 }
1243
1244 txq_id = iwl_txq_ctx_activate_free(priv);
1245 if (txq_id == -1) {
1246 IWL_ERR(priv, "No free aggregation queue available\n");
1247 return -ENXIO;
1248 }
1249
1250 spin_lock_irqsave(&priv->sta_lock, flags);
1251 tid_data = &priv->stations[sta_id].tid[tid];
1252 *ssn = SEQ_TO_SN(tid_data->seq_number);
1253 tid_data->agg.txq_id = txq_id;
1254 priv->txq[txq_id].swq_id = iwl_virtual_agg_queue_num(tx_fifo, txq_id);
1255 spin_unlock_irqrestore(&priv->sta_lock, flags);
1256
1257 ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
1258 sta_id, tid, *ssn);
1259 if (ret)
1260 return ret;
1261
1262 if (tid_data->tfds_in_queue == 0) {
1263 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1264 tid_data->agg.state = IWL_AGG_ON;
1265 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1266 } else {
1267 IWL_DEBUG_HT(priv, "HW queue is NOT empty: %d packets in HW queue\n",
1268 tid_data->tfds_in_queue);
1269 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1270 }
1271 return ret;
1272 }
1273 EXPORT_SYMBOL(iwl_tx_agg_start);
1274
1275 int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid)
1276 {
1277 int tx_fifo_id, txq_id, sta_id, ssn = -1;
1278 struct iwl_tid_data *tid_data;
1279 int ret, write_ptr, read_ptr;
1280 unsigned long flags;
1281
1282 if (!ra) {
1283 IWL_ERR(priv, "ra = NULL\n");
1284 return -EINVAL;
1285 }
1286
1287 if (unlikely(tid >= MAX_TID_COUNT))
1288 return -EINVAL;
1289
1290 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1291 tx_fifo_id = default_tid_to_tx_fifo[tid];
1292 else
1293 return -EINVAL;
1294
1295 sta_id = iwl_find_station(priv, ra);
1296
1297 if (sta_id == IWL_INVALID_STATION) {
1298 IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid);
1299 return -ENXIO;
1300 }
1301
1302 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
1303 IWL_WARN(priv, "Stopping AGG while state not IWL_AGG_ON\n");
1304
1305 tid_data = &priv->stations[sta_id].tid[tid];
1306 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1307 txq_id = tid_data->agg.txq_id;
1308 write_ptr = priv->txq[txq_id].q.write_ptr;
1309 read_ptr = priv->txq[txq_id].q.read_ptr;
1310
1311 /* The queue is not empty */
1312 if (write_ptr != read_ptr) {
1313 IWL_DEBUG_HT(priv, "Stopping a non empty AGG HW QUEUE\n");
1314 priv->stations[sta_id].tid[tid].agg.state =
1315 IWL_EMPTYING_HW_QUEUE_DELBA;
1316 return 0;
1317 }
1318
1319 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1320 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1321
1322 spin_lock_irqsave(&priv->lock, flags);
1323 ret = priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
1324 tx_fifo_id);
1325 spin_unlock_irqrestore(&priv->lock, flags);
1326
1327 if (ret)
1328 return ret;
1329
1330 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1331
1332 return 0;
1333 }
1334 EXPORT_SYMBOL(iwl_tx_agg_stop);
1335
1336 int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id)
1337 {
1338 struct iwl_queue *q = &priv->txq[txq_id].q;
1339 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1340 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1341
1342 switch (priv->stations[sta_id].tid[tid].agg.state) {
1343 case IWL_EMPTYING_HW_QUEUE_DELBA:
1344 /* We are reclaiming the last packet of the */
1345 /* aggregated HW queue */
1346 if ((txq_id == tid_data->agg.txq_id) &&
1347 (q->read_ptr == q->write_ptr)) {
1348 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1349 int tx_fifo = default_tid_to_tx_fifo[tid];
1350 IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n");
1351 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
1352 ssn, tx_fifo);
1353 tid_data->agg.state = IWL_AGG_OFF;
1354 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1355 }
1356 break;
1357 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1358 /* We are reclaiming the last packet of the queue */
1359 if (tid_data->tfds_in_queue == 0) {
1360 IWL_DEBUG_HT(priv, "HW queue empty: continue ADDBA flow\n");
1361 tid_data->agg.state = IWL_AGG_ON;
1362 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1363 }
1364 break;
1365 }
1366 return 0;
1367 }
1368 EXPORT_SYMBOL(iwl_txq_check_empty);
1369
1370 /**
1371 * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack
1372 *
1373 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1374 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1375 */
1376 static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1377 struct iwl_ht_agg *agg,
1378 struct iwl_compressed_ba_resp *ba_resp)
1379
1380 {
1381 int i, sh, ack;
1382 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1383 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1384 u64 bitmap;
1385 int successes = 0;
1386 struct ieee80211_tx_info *info;
1387
1388 if (unlikely(!agg->wait_for_ba)) {
1389 IWL_ERR(priv, "Received BA when not expected\n");
1390 return -EINVAL;
1391 }
1392
1393 /* Mark that the expected block-ack response arrived */
1394 agg->wait_for_ba = 0;
1395 IWL_DEBUG_TX_REPLY(priv, "BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1396
1397 /* Calculate shift to align block-ack bits with our Tx window bits */
1398 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4);
1399 if (sh < 0) /* tbw something is wrong with indices */
1400 sh += 0x100;
1401
1402 /* don't use 64-bit values for now */
1403 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1404
1405 if (agg->frame_count > (64 - sh)) {
1406 IWL_DEBUG_TX_REPLY(priv, "more frames than bitmap size");
1407 return -1;
1408 }
1409
1410 /* check for success or failure according to the
1411 * transmitted bitmap and block-ack bitmap */
1412 bitmap &= agg->bitmap;
1413
1414 /* For each frame attempted in aggregation,
1415 * update driver's record of tx frame's status. */
1416 for (i = 0; i < agg->frame_count ; i++) {
1417 ack = bitmap & (1ULL << i);
1418 successes += !!ack;
1419 IWL_DEBUG_TX_REPLY(priv, "%s ON i=%d idx=%d raw=%d\n",
1420 ack ? "ACK" : "NACK", i, (agg->start_idx + i) & 0xff,
1421 agg->start_idx + i);
1422 }
1423
1424 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
1425 memset(&info->status, 0, sizeof(info->status));
1426 info->flags |= IEEE80211_TX_STAT_ACK;
1427 info->flags |= IEEE80211_TX_STAT_AMPDU;
1428 info->status.ampdu_ack_map = successes;
1429 info->status.ampdu_ack_len = agg->frame_count;
1430 iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
1431
1432 IWL_DEBUG_TX_REPLY(priv, "Bitmap %llx\n", (unsigned long long)bitmap);
1433
1434 return 0;
1435 }
1436
1437 /**
1438 * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1439 *
1440 * Handles block-acknowledge notification from device, which reports success
1441 * of frames sent via aggregation.
1442 */
1443 void iwl_rx_reply_compressed_ba(struct iwl_priv *priv,
1444 struct iwl_rx_mem_buffer *rxb)
1445 {
1446 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1447 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1448 struct iwl_tx_queue *txq = NULL;
1449 struct iwl_ht_agg *agg;
1450 int index;
1451 int sta_id;
1452 int tid;
1453
1454 /* "flow" corresponds to Tx queue */
1455 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1456
1457 /* "ssn" is start of block-ack Tx window, corresponds to index
1458 * (in Tx queue's circular buffer) of first TFD/frame in window */
1459 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1460
1461 if (scd_flow >= priv->hw_params.max_txq_num) {
1462 IWL_ERR(priv,
1463 "BUG_ON scd_flow is bigger than number of queues\n");
1464 return;
1465 }
1466
1467 txq = &priv->txq[scd_flow];
1468 sta_id = ba_resp->sta_id;
1469 tid = ba_resp->tid;
1470 agg = &priv->stations[sta_id].tid[tid].agg;
1471
1472 /* Find index just before block-ack window */
1473 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1474
1475 /* TODO: Need to get this copy more safely - now good for debug */
1476
1477 IWL_DEBUG_TX_REPLY(priv, "REPLY_COMPRESSED_BA [%d] Received from %pM, "
1478 "sta_id = %d\n",
1479 agg->wait_for_ba,
1480 (u8 *) &ba_resp->sta_addr_lo32,
1481 ba_resp->sta_id);
1482 IWL_DEBUG_TX_REPLY(priv, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1483 "%d, scd_ssn = %d\n",
1484 ba_resp->tid,
1485 ba_resp->seq_ctl,
1486 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1487 ba_resp->scd_flow,
1488 ba_resp->scd_ssn);
1489 IWL_DEBUG_TX_REPLY(priv, "DAT start_idx = %d, bitmap = 0x%llx \n",
1490 agg->start_idx,
1491 (unsigned long long)agg->bitmap);
1492
1493 /* Update driver's record of ACK vs. not for each frame in window */
1494 iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1495
1496 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1497 * block-ack window (we assume that they've been successfully
1498 * transmitted ... if not, it's too late anyway). */
1499 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1500 /* calculate mac80211 ampdu sw queue to wake */
1501 int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
1502 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1503
1504 if ((iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1505 priv->mac80211_registered &&
1506 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
1507 iwl_wake_queue(priv, txq->swq_id);
1508
1509 iwl_txq_check_empty(priv, sta_id, tid, scd_flow);
1510 }
1511 }
1512 EXPORT_SYMBOL(iwl_rx_reply_compressed_ba);
1513
1514 #ifdef CONFIG_IWLWIFI_DEBUG
1515 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1516
1517 const char *iwl_get_tx_fail_reason(u32 status)
1518 {
1519 switch (status & TX_STATUS_MSK) {
1520 case TX_STATUS_SUCCESS:
1521 return "SUCCESS";
1522 TX_STATUS_ENTRY(SHORT_LIMIT);
1523 TX_STATUS_ENTRY(LONG_LIMIT);
1524 TX_STATUS_ENTRY(FIFO_UNDERRUN);
1525 TX_STATUS_ENTRY(MGMNT_ABORT);
1526 TX_STATUS_ENTRY(NEXT_FRAG);
1527 TX_STATUS_ENTRY(LIFE_EXPIRE);
1528 TX_STATUS_ENTRY(DEST_PS);
1529 TX_STATUS_ENTRY(ABORTED);
1530 TX_STATUS_ENTRY(BT_RETRY);
1531 TX_STATUS_ENTRY(STA_INVALID);
1532 TX_STATUS_ENTRY(FRAG_DROPPED);
1533 TX_STATUS_ENTRY(TID_DISABLE);
1534 TX_STATUS_ENTRY(FRAME_FLUSHED);
1535 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
1536 TX_STATUS_ENTRY(TX_LOCKED);
1537 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
1538 }
1539
1540 return "UNKNOWN";
1541 }
1542 EXPORT_SYMBOL(iwl_get_tx_fail_reason);
1543 #endif /* CONFIG_IWLWIFI_DEBUG */
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